Tolerant 500K Used Gates CMOS Gates MG2RT Description M

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Tolerant 500K Used Gates CMOS Gates MG2RT Description M

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Full Range Matrices 700K Cells Drawn CMOS, Metal Layers, Gates DPRAM Compilers Library Optimized Synthesis, Floor Plan Automatic Test Generation (ATG) Volts Operation: Single Dual Supply Mode High Speed Performances: max. NAND2 Propagation Delay max. min. Toggle Frequency 4.5V, 2.7V Programmable Available Request High System Frequency Skew Control: max. Clock Generation 4.5V Clock Tree Synthesis Software Power Consumption: µW/Gate/MHz µW/Gate/MHz Matrices with Fully Programmable Pads Standard I/Os Versatile Cell: Input, Output, I/O, Supply, Oscillator CMOS/TTL/PCI Interface Latch-up Protected Wide Selection MQFPs CLGA Packages Pins High Noise Immunity: with Slew Rate Control Internal Decoupling Signal Filtering between Periphery Core Application Dependent Supply Routing Several Independant Supply Sources Delivery Form with 94.6 Pitch Advanced Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence®, Mentor®, Vital® Synopsys® Reference Platforms EDIF VHDL Reference Formats Available Military Space Quality Grades (SCC, MIL-PRF-38535) Latch-up Immune with 5962-00B02
Tolerant 500K Used Gates CMOS Gates
MG2RT
Description
MG2RT series micron, array based, CMOS product family. Several arrays 700K cells cover system integration needs. MG2RT manufactured using micron drawn, metal layer CMOS process. base cell architecture MG2RT series provides high routability logic with extremely dense compiled memories: DPRAM. generated using synthesis tools. instance, largest array capable integrating 128K bits DPRAM with 128K bits over 300,000 random gates. Accurate control clock distribution achieved hardware (Clock Tree Synthesis) software. noise prevention techniques applied array periphery: Three more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, swing differential I/Os, contribute improve noise immunity reduce emission level. MG2RT supported advanced software environment based industry standards linking proprietary commercial tools. Cadence, Mentor, Synopsys andVHDL reference front-end tools. Floor planning associated with timing-driven layout provides short back-end cycle.
Rev. 4115G-AERO-03/02
MG2RT library allows straight forward migration from MG1RT Gates. netlist based this library simulated either MG2RT MG2RTP: MG2, must SEU-free cells. Table List Available MG2RT Matrix
Type MG2044E MG2091E MG2140E MG2194E MG2265E MG2360E MG2480E MG2700E
Total Cells 44616 91464 140322 193800 264375 361680 481143 698523
Usable Gates 33000 68000 105000 145000 198000 271000 360000 524000
Maximum
Total Pads
Note:
Check availability.
Libraries
MG2RT cell library been designed take full advantage features offered both logic test synthesis tools. Design testability assured full support SCAN, JTAG (IEEE 1149) BIST methodologies. More complex macro functions available VHDL, such Two-wire Interface (TWI), UART, Timer.
Block Generators
Block generators used create customer specific simulation model metallisation pattern regular functions like RAM, DPRAM, FIFO. basic cell architecture allows cell DPRAM. main characteristics these generators summarised below.
Typical Characteristics Kbits) Function DPRAM Maximum Size (bits) Bits/Word 1-36 1-36 Access Time (ns) Used Cells
MG2RT
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MG2RT
Buffer Interfacing
Flexibility Inputs
buffers configured input, output, bi-directional, oscillator supply. level translator located close each buffer. Input buffers with CMOS thresholds non-inverting feature versions with without hysteresis. CMOS input buffers incorporate pull-up pull down terminators. special purposes, buffer allowing direct input matrix core available. Several kinds CMOS output drivers offered: fast buffers with drive noise buffers with drive
Outputs
Clock Generation
Clock Generation
Atmel offers different types oscillators: high frequency crystal oscillator oscillators. devices, mark-space ratio better than 40/60 start-up time less than
Frequency (MHz) Oscillators Xtal Xtal Xtal Xtal 100M Xtal Typical Consumption (mA)
Request)
Check availability.
4115G-AERO-03/02
Power Supply Noise Protection
speed density SCMOS3/2RT technology causes large switching current spikes example when: either high current output buffers switch simultaneously, gates switching within window
Sharp edges high currents cause some parisitic elements packaging become significant. this frequency range, package inductance series resistance should taken into account. known that inductor slows down settling time current causes voltage drops power supply lines. These drops affect behavior circuit itself disturb external application (ground bounce). order improve noise immunity core matrix, several mechanisms have been implemented inside arrays. kinds protection have been added: limit buffer switching noise other protect buffers against switching noise coming from matrix.
Buffers Switching Protection
Three features implemented limit noise generated switching current: power supplies input output buffers separated. rise fall times output buffers controlled internal regulator. design rule concerning number buffers connected same power supply line been imposed.
Matrix Switching Current Protection
This noise disturbance caused large number gates switching simultaneously. allow this without impacting functionality circuit, three features have been added: Decoupling capacitors integrated directly silicon reduce power supply drop. power supply network been implemented matrix. This solution reduces number parasitic elements such inductance resistance constitutes artificial Ground plane. mesh network supplies approximately cells. pass filter been added between matrix input output buffer. This limits transmission noise coming from ground supply matrix external world output buffers.
Power Consumption
power consumption MG2RT array three factors: leakage (P1), core (P2) (P3) consumption.
Leakage (Standby) Power Consumption
consumption leakage currents defined (VDD VSS) ICCSB NCELL Where ICCSB leakage current through polarized basic gate NCELL number used cells.
MG2RT
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MG2RT
Core Power Consumption
power consumption switching cells core matrix defined CELL PGATE ACTIVITY Where NCELL number used cells, data toggling frequency, which equal half clock frequency random data GATE power consumption cell. PGATE
ACTIVITY fraction total number cells toggling cycle. (VDD VSS)2/2
Capacitance Power
total output capacitance expressed drain capacitance driver, wiring capacitance gate capacitance inputs. Worst case value: µW/gate/MHz Commutation Power (VDD VSS) Idsohm Where Idsohm current flowing into driver between supply ground during commutation. Idsohm about Pmos saturation current. Worst case value: µW/gate/MHz
Power Consumption
power consumption I/Os (VDD VSS) Fi/2 With equals number buffers running output capacitance. Note: signal clock, data with random values, F/4.
4115G-AERO-03/02
Table Typical Power Consumption Example
Matrix Used gates (70%) Frequency Standby Power Iccsb (125°C) (VDD VSS) ICCSB NCELL Core Power Power Consumption Cell Cactivity NCELL PGATE Cactivity Power Total Number Buffers Number Outputs Buffers (NI) Output Capacitance (VDD VSS) Fi/2 Total Power 2.59W 0.81W
MG2700E 490K
MG2700E 490K
µW/Gate/MHz 1960
0.58 µW/Gate/MHz
MG2RT
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MG2RT
Packaging
Atmel offers wide range packaging options which listed below:
Pins(2) Packaging Package Type MLCC min/max Lead Spacing (mils) 25.6
CERAMIC
MQFP
CLGA(1)
Note:
plastic, call factory; this customer decision plastic packages environmental conditions which beyond those which they have been developed. Ceramic Land Grid Array: contact factory. Contact Atmel local design centers check availability used matrix package.
4115G-AERO-03/02
Design Flows Tools
Design Flows Modes generic design flow MG2RT array illustrated below.
down design methodology proposed which starts with high level system description refined successive design steps. each step, structural verification performed which includes following tasks: Gate level logic simulation comparison with high level simulation results. Design test rule check. Power consumption analysis. Timing analysis (only after floor plan). System specification, preferably VHDL form. Functional description level. Logic synthesis. Floor planning bonding diagram generation. Test/Scan insertion, and/or fault simulation. Physical cell placement, JTAG insertion clock tree synthesis. Routing.
main design stages are:
meet various requirements designers, several interface levels between customer Atmel possible. each possible design modes review meeting required data transfer from user Atmel. cases final routing verifications performed Atmel. design acceptance formalized design review which authorizes Atmel proceed with sample manufacturing.
MG2RT
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MG2RT
Figure MG2RT Design Flow
System Specifications
Simulation
Logic synthesis
Floor Plan Bonding diagram
Scan insertion Fault Simulation
Placement
JTAG insertion Clock Tree Synthesis
Routing
Backannotated Simulation
Sign-off
Samples Manufacturing Test
4115G-AERO-03/02
Design Tool Design Kits (DK)
basic content design described table below. interface formats from Atmel rely IEEE industry standard: VHDL functional descriptions VHDL EDIF netlists Tabular, .CAP simulation results (VITAL format) back annotation physical floor plan information
design supported several commercial tools listed below. Design Support Cadence (VHDL gate) Mentor (VHDL gate) Synopsys (VHDL gate) Vital (VHDL gate)
Table Design Description
Design Tool library Design manual libraries VHDL library blocks Synthesis library Gate level simulation library Design rules analyser Power consumption analyser Floor plan library Timing analyser library Package bonding software Scan path JTAG insertion fault simulation library MISS
Atmel Software Name
Third Party Tools
STAR COMET
Note:
Refer "Design kits cross reference tables" ATD-TS-WF-R0181
MG2RT
4115G-AERO-03/02
MG2RT
Electrical Characteristics
Absolute Maximum Ratings
Ambient temperature under bias (TA) Military +125°C Junction temperature.TJ 20°C Storage temperature. +150°C TTL/CMOS: Supply voltage -0.5V voltage .-0.5V 0.5V
Note: Stresses above those listed cause permanent damage device. Exposure absolute maximum rating conditions extended period affect device reliability.
Characteristics
Table Specified
Symbol Parameter Input voltage CMOS input input Input HIGH voltage CMOS input input Output voltage Output high voltage CMOS Schmitt trigger positive threshold CMOS input input Schmitt trigger negative threshold CMOS input input CMOS hysteresis 25°C/5V hysteresis 25°C/5V Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP ICCSB ICCOP Leakage current cell Operating current cell 0.39 Unit Conditions
-12, mA(1)
-12, mA(1)
Delta
-120
µA/MHz BOUT12 VOUT 4.5V VOUT
10.0 0.53
Note:
According buffer: Bout12, Bout6, Bout3.
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Table Specified
Symbol Parameter Input voltage LVCMOS input LVTTL input Input HIGH voltage LVCMOS input LVTTL input Output voltage Output high voltage Schmitt trigger positive threshold LVCMOS input LVTTL input Schmitt trigger negative threshold LVCMOS input LVTTL input CMOS hysteresis 25°C/5V hysteresis 25°C/5V Input leakage pull up/down Pull Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP ICCSB ICCOP Leakage current cell Operating current cell Unit Conditions
IOL= mA(1)
IOH= mA(1)
Delta
BOUT12 µA/MHz VOUT VOUT
Note:
According buffer: Bout12, Bout6, Bout3.
MG2RT
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MG2RT
Characteristics
Table Characteristics 25°C, Process typical (all values
Buffer BOUT12 Description Output buffer with drive Load Tphl Tplh BOUT3 Output buffer with drive Tphl Tplh BOUTQ noise output buffer with drive Tphl Tplh B3STA3 3-state output buffer with drive Tphl Tplh B3STA12 3-state output buffer with drive Tphl Tplh B3STAQ noise 3-state output buffer with drive Tphl 4.42 6.34 2.79 3.01 3.72 4.61 4.89 2.64 6.44 4.07 4.36 4.73 6.24 7.35 4.86 2.97 6.36 4.48 2.76 4.63 3.64 7.22 Transition Tplh 2.53 3.91
4115G-AERO-03/02
Table Characteristics 25°C, Process typical (all values
Cell BINCMOS Description CMOS input buffer Load Tphl Tplh BINTTL input buffer Tphl Tplh Inverter Tphl Tplh NAND2 input NAND Tphl Tplh Tphl FDFF flip-flop, Tplh BUF4X High drive internal buffer Tphl Tplh NOR2 2-Input gate Tphl OAI22 4-input INVERT gate Tplh Tphl Tplh OSFF flip-flop with scan input, Tphl 0.56 -0.34 -0.6 0.42 0.83 1.00 0.54 1.23 1.38 0.37 0.68 0.45 1.14 0.58 0.65 0.81 1.08 0.33 -0.12 0.76 0.44 -0.24 0.66 0.68 1.21 1.02 0.42 0.73 0.53 1.11 0.52 0.75 1.06 1.31 Transition Tplh 0.77 1.14
MG2RT
4115G-AERO-03/02
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4115G-AERO-03/02

Tolerant 500K Used Gates CMOS Gates MG2RT Description M

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