Quad 2-input NAND gate Rev. January 2010 Product data sheet
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74HC00; 74HCT00
Quad 2-input NAND gate
Rev. January 2010 Product data sheet
74HC00; 74HCT00 high-speed Si-gate CMOS devices that comply with JEDEC standard They compatible with Low-power Schottky (LSTTL). 74HC00; 74HCT00 provides quad 2-input NAND function.
Features
Input levels: 74HC00: CMOS level 74HCT00: level protection: JESD22-A114F exceeds JESD22-A115-A exceeds Multiple package options Specified from from +125
Ordering information
Table Ordering information Package Temperature range 74HC00N 74HCT00N 74HC00D 74HCT00D 74HC00DB 74HCT00DB 74HC00PW 74HCT00PW 74HC00BQ 74HCT00BQ +125 DHVQFN14 +125 TSSOP14 +125 SSOP14 +125 SO14 plastic small outline package; leads; body width plastic shrink small outline package; leads; body width plastic thin shrink small outline package; leads; body width SOT108-1 SOT337-1 SOT402-1 +125 Name DIP14 Description plastic dual in-line package; leads (300 mil) Version SOT27-1 Type number
plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; leads; terminals; body 0.85
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Functional diagram
mna212
mna246
mna211
Logic symbol
logic symbol
Logic diagram (one gate)
Pinning information
Pinning
74HC00 74HCT00
terminal index area GND(1)
001aal324
B.V. 2010. rights reserved.
74HC00 74HCT00
001aal323
Transparent view
substrate attached this using conductive attach material. used supply input. recommended that connection made all.
configuration DIP14, SO14 (T)SSOP14
configuration DHVQFN14
description
Table Symbol
74HC_HCT00_4
description Description data input data input data output ground supply voltage
Rev. January 2010
Product data sheet
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Functional description
Table Input
Function table[1] Output
HIGH voltage level; voltage level; don't care.
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Voltages referenced (ground Symbol IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP14 package SO14, (T)SSOP14 DHVQFN14 packages
Conditions -0.5 -0.5 -0.5
-0.5
+150
Unit
input output voltage ratings exceeded input output current ratings observed. DIP14 package: Ptot derates linearly with mW/K above SO14 package: Ptot derates linearly with mW/K above (T)SSOP14 packages: Ptot derates linearly with mW/K above DHVQFN14 packages: Ptot derates linearly with mW/K above
Recommended operating conditions
Table Recommended operating conditions Voltages referenced (ground Symbol Parameter Tamb supply voltage input voltage output voltage ambient temperature Conditions 74HC00 +125 74HCT00 +125 Unit
74HC_HCT00_4
B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Table Recommended operating conditions .continued Voltages referenced (ground .continued Symbol Parameter input transition rise fall rate Conditions 74HC00 1.67 74HCT00 1.67 ns/V ns/V ns/V Unit
Static characteristics
Table Static characteristics recommended operating conditions; voltages referenced (ground Symbol Parameter 74HC00 HIGH-level input voltage LOW-level input voltage HIGH-level output voltage -4.0 -5.2 LOW-level output voltage input leakage current supply current input capacitance GND; GND; 0.15 0.16 0.33 0.33 4.32 5.81 3.84 5.34 3.15 1.35 3.15 1.35 Conditions +125 Unit
74HC_HCT00_4
B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Table Static characteristics .continued recommended operating conditions; voltages referenced (ground Symbol Parameter 74HCT00 HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VIL; -4.0 LOW-level output voltage VIL; input leakage current supply current additional supply current GND; GND; input pin; other inputs GND; 0.15 0.33 4.32 3.84 Conditions +125 Unit
input capacitance
Dynamic characteristics
Table Dynamic characteristics load circuit Figure Symbol Parameter Conditions 74HC00 propagation delay Figure transition time Figure power dissipation capacitance package;
+125 Unit (125
74HC_HCT00_4
B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Table Dynamic characteristics load circuit Figure Symbol Parameter Conditions 74HCT00 propagation delay Figure transition time power dissipation capacitance Figure package;
+125 Unit (125
same tPHL tPLH. same tTHL tTLH. used determine dynamic power dissipation VCC2 VCC2 where: input frequency MHz; output frequency MHz; output load capacitance supply voltage number inputs switching; VCC2 outputs.
Waveforms
input tPHL output tTHL tTLH
001aai814
tPLH
Measurement points given Table typical voltage output levels that occur with output load.
Table Type 74HC00 74HCT00
Input output propagation delays Measurement points Input 0.5VCC Output 0.5VCC 0.1VCC 0.1VCC 0.9VCC 0.9VCC
74HC_HCT00_4
B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
negative pulse
positive pulse
001aah768
Test data given Table Definitions test circuit: termination resistance should equal output impedance pulse generator. load capacitance including probe capacitance.
Table Type 74HC00 74HCT00
Load circuitry measuring switching times Test data Input Load tPLH, tPHL tPLH, tPHL Test
74HC_HCT00_4
B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Package outline
DIP14: plastic dual in-line package; leads (300 mil) SOT27-1
seating plane
index
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches max. 0.17 min. 0.51 0.02 max. 0.13 1.73 1.13 0.068 0.044 0.53 0.38 0.021 0.015 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 0.39 0.33 0.254 0.01 max. 0.087
Note Plastic metal protrusions 0.25 (0.01 inch) maximum side included. OUTLINE VERSION SOT27-1 REFERENCES 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Package outline SOT27-1 (DIP14)
74HC_HCT00_4 B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
SO14: plastic small outline package; leads; body width
SOT108-1
index
detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT max. 1.75 0.25 0.10 1.45 1.25 0.25
0.01
0.49 0.36
0.25 0.19
8.75 8.55
0.16 0.15
1.27
0.05
1.05
0.028 0.024
0.25 0.01
0.25
0.01
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
Note Plastic metal protrusions 0.15 (0.006 inch) maximum side included. OUTLINE VERSION SOT108-1 REFERENCES
076E06
JEDEC
MS-012
JEITA
EUROPEAN PROJECTION
ISSUE DATE
99-12-27 03-02-19
Package outline SOT108-1 (SO14)
74HC_HCT00_4 B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
SSOP14: plastic shrink small outline package; leads; body width
SOT337-1
index
detail
scale
DIMENSIONS original dimensions) UNIT max. 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 0.65 1.25 1.03 0.63 0.13
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT337-1 REFERENCES JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Package outline SOT337-1 (SSOP14)
74HC_HCT00_4 B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
TSSOP14: plastic thin shrink small outline package; leads; body width
SOT402-1
index
detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13 0.72 0.38
Notes Plastic metal protrusions 0.15 maximum side included. Plastic interlead protrusions 0.25 maximum side included. OUTLINE VERSION SOT402-1 REFERENCES JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Package outline SOT402-1 (TSSOP14)
74HC_HCT00_4 B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; leads; SOT762-1 terminals; body 0.85
terminal index area
detail
terminal index area
scale
DIMENSIONS original dimensions) UNIT A(1) max. 0.05 0.00 0.30 0.18 1.65 1.35 1.15 0.85 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included. OUTLINE VERSION SOT762-1 REFERENCES -JEDEC MO-241 JEITA -EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Package outline SOT762-1 (DHVQFN14)
74HC_HCT00_4 B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Abbreviations
Table Acronym CMOS LSTTL Abbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic
Revision history
Table Revision history Release date 20100111 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT00_3 Document 74HC_HCT00_4 Modifications:
format this data sheet been redesigned comply with identity guidelines Semiconductors. Legal texts have been adapted company name where appropriate. Product data sheet Product specification 74HC_HCT00_CNV_2
74HC_HCT00_3 74HC_HCT00_CNV_2
20030630 19970826
74HC_HCT00_4
B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
15.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
damage. Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights. Export control This document well item(s) described herein subject export control regulations. Export might require prior authorization from national authorities.
15.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental
15.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners.
Contact information
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com
74HC_HCT00_4
B.V. 2010. rights reserved.
Product data sheet
Rev. January 2010
Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Contents
15.1 15.2 15.3 15.4 General description Features Ordering information Functional diagram Pinning information Pinning description Functional description Limiting values. Recommended operating conditions. Static characteristics. Dynamic characteristics Waveforms Package outline Abbreviations Revision history Legal information. Data sheet status Definitions Disclaimers Trademarks. Contact information. Contents
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2010.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: January 2010 Document identifier: 74HC_HCT00_4
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