Application Brief M-015 HCTL-1100/8051 Interfaces This appli
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Interfacing HCTL-1100 8051
Application Brief M-015
HCTL-1100/8051
Interfaces This application brief offers different approaches interfacing HCTL-1100 8051 microcontroller family. first approach uses 8051's address/data/ control communicate with HCTL-1100 second approach uses 8051's ports communicate with HCTL-1100. choice which interface most appropriate your application should based whether your current design utilizing 8051's structure. your 8051 design utilizing bus, makes sense HCTL-1100 interface circuit. This approach requires only additional chips. your 8051 design completely based with external memory, makes sense port interface. interface requires additional glue logic. routines slightly more complicated interface than interface. These routines seen software listings provided with this application brief. There only marginal performance difference between approaches. execution times these routines listed Table These execution times include stack operations subroutine overhead. HCTL-1100 interface circuit capable supporting four HCTL-1100s with additional logic. port based design requires more than HCTL-1100, interface would require only additional port lines chip. These lines would control (Output Enable) (Chip Select) each individual HCTL-1100s. there inadequate number port lines available this purpose, separate decoder chip could used. such chip 74LS138 3-to-8 decoder which capable handling four HCTL-1100s.
Table Execution Times Read Operation Port Interface Clock Per. Interface Clock Per. Write Operation Clock Per. Clock Per.
SYNC
SIGN PULSE
EA/VP
RESET
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE/P INT0 INT1
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 8051
RESET
INDEX PROF INIT LIMIT STOP
HCTL 1100
2MHz
Figure Interfacing HCTL-1100 8051 Using Ports
;HCTL-1100 READ/WRITE ROUTINES ;THIS SOFTWARE USED CONJUNCTION WITH HCTL-1100/8051 ;PORT INTERFACE ;SUBROUTINE RD1100 ;READS HCTL POINTED RETURNS VALUE RD1100: SETB P2.0 LINE READ SETB SETB SETB
(Continues)
P1,B P2.3 P2.3 P1,#0FFH P2.2 P2.2
LATCH ADDRESS PULSE
PULSE DELAY ALLOW ENOUGH TIME 1MHz HCTL-1100 FASTER
P2.1 A,P0 P2.1
OE=0 DATA FROM 1100 OE=1
;SUBROUTINE WR1100 ;LOADS HCTL-1100 REGISTER POINTED WITH VALUE WR1100: SETB SETB SETB ;SUBROUTINE RS1100 ;THIS SUBROUTINE RESETS HCTL-1100 WITH PULSE. THIS ;ENOUGH TIME RESET 1MHz HCTL-1100 FASTER. RS1100: SETB P2,#0FH P0,#0FFH P2.4 READ, OE=1, CS=1, AE=1 P1=HIGH RESET PULSE REMOVE NOP'S 2MHz HCTL-1100 P1,B P2.3 P2.3 P1,#0FFH P2.0 P1,A P2.2 P2.2 P2.0 P1,#0FFH LATCH ADDR PULSE
LINE WRITE SEND DATA PULSE RETURN READ MODE
P2.4
BRING RESET LINE HIGH
SYNC
SIGN PULSE
74LS00
CHIP CHIP RESET INDEX PROF INIT LIMIT STOP
74LS00 ADDR DEC\ 74LS00
HCTL-1100 CHIP2\ CHIP2\ CHIP3\ CHIP3\ CHIP4\ CHIP4\
74LS138 74LS00
2MHz
RESET 8051 HCTL-1100
74LS00
74LS138
DENOTES ACTIVE SIGNAL
Figure Interfacing HCTL-1100 8051 Using Address/Data Bus.
;HCTL-1100 READ/WRITE ROUTINES ;THIS SOFTWARE USED CONJUNCTION WITH HCTL-1100 ;BUS INTERFACE HCTL-1100 ADDRESS OE1100 060H CS1100 061H
BASE ADDRESS 6000H BASE ADDRESS 6100H
;SUBROUTINE RD1100 ;READS HCTL POINTED RETURNS VALUE RD1100: PUSH PUSH MOVX MOVX DPH,#CS1100 DPL,B A,@DPTR SAVE DATA POINTER
POINT BASE ADDRESS LOAD ADDRESS LOWER BITS DATA POINTER LATCH HCTL-1100 ADDRESS ALLOW ENOUGH TIME 1MHz (NOT REQUIRED 2MHz HCTL-1100 CLK) POINT BASE ADDRESS READ BYTE FROM HCTL-1100 RESTORE DATA POINTER
DPH,#OE1100 A,@DPTR
;SUBROUTINE WR1100 ;LOADS HCTL-1100 REGISTER POINTED WITH VALUE WR1100: PUSH PUSH MOVX SAVE DATA POINTER
DPTR,#CS1100 POINT BASE ADDRESS DPL,B LOAD ADDRESS LOWER BITS DATA POINTER @DPTR,A WRITE BYTE HCTL-1100 RESTORE DATA POINTER
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