Si9142 Synchronous Buck Controller High Performance Processors

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Si9142 Synchronous Buck Controller High Performance Processors

Datasheet Thumbnail

Top Searches for this datasheet

Si9142
Si9142
Synchronous Buck Controller High Performance Processors
FEATURES
Over-Voltage Protection Programmable Over-Current Protection Voltage Mode Control Precision 1.3-V, ±1.6% Reference Drives N-Channel Switch Rectifier 800-µA Quiescent Current kHz) 150-µA Standby Current Integrated "Power Good" Output Synchronization Under-Voltage Lockout
DESCRIPTION
voltage mode, synchronous buck controller designed point-of-use dc/dc conversion high performance server desktop computers. High efficiency accomplished full load driving high- low-side n-channel MOSFETs. input voltage range been designed 4.75 13.2 allow either 1-MHz switching frequency combined with 10-MHz error amplifier provides ultra-fast transient response necessary high performance microprocessor power supply. Si9142 available 20-pin SOIC wide-body package specified operate over commercial 70°C) temperature range. demo board, Si9142DB, available.
FUNCTIONAL BLOCK DIAGRAM
FaxBack 408-970-5600, request 70750 www.siliconix.com
S-60752-Rev. 05-Apr-99
Si9142
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced AGND VSYNC_IN -0.3 VSYNC_OUT -0.3 -0.3 Voltages Referenced PGND VBST -0.3 VPGND VAGND Short Continuous VREF(OUT) Short GND. Continuous Continuous Power Dissipation 25°C)a 20-Pin SOIC Wide-Bodyb. 1.45 Operating Temperature Range. 70°C Storage Temperature Range 125°C Lead Temperature (soldering, sec) 300°C TJMAX 150°C .86°C/W Notes Device mounted with leads soldered welded board. Derate 11.6 mW/°C above 25°C.
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
.4.75 13.2 ROSC (100 kHz) MHz) VL(out), (in) Capacitance VL(out) Load VREF Capacitance VREF Load Analog Digital Inputs
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specifed Parameter Reference
Output Voltage Regulation Line Rejection IREF IREF 1.30 -1.6% 1.30 1.30 +1.6% 4.75 13.2 70°C
Mina
Typb
Maxa
Unit
Oscillator
Operating Frequency Maximum Duty Cycle SYNC High SYNC Sync Open fOSC fOSC -100 1000
Output Drivers
Source/Sink (Peak) 4.75 Driver Driver 1000 1000
Supply
Quiescent Current Standby Current Shutdown fosc 1200
Output Voltage Line Rejection 13.2 4.95 6.05
S-60752-Rev. 05-Apr-99
FaxBack 408-970-5600, request 70750 www.siliconix.com
Si9142
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specifed Parameter SS/Enable
Source Current Fault Sink Current Logic Logic High -2.5 -7.5 4.75 13.2 70°C
Mina
Typb
Maxa
Unit
UVLO
Lockout Voltage Hysteresis Falling
Error Amplifier
Unity-Gain Product Input Bias Current Offset Voltage Output Current VREF VREF Source (VFB VREF) Sink (VFB VREF) -15.0 15.0
PWR_GOOD
VPWR_GOOD High VPWR_GOOD Output Sink Current Typical Hysteresis VREF +12% -12%
Threshold Voltage VREF 4.75 VICS 13.2
Sink Current Notes algebraic convention whereby most negative value minimum most positive maximum. Typical values DESIGN ONLY, guaranteed subject production testing.
FaxBack 408-970-5600, request 70750 www.siliconix.com
S-60752-Rev. 05-Apr-99
Si9142
TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)
S-60752-Rev. 05-Apr-99
FaxBack 408-970-5600, request 70750 www.siliconix.com
Si9142
TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)
FaxBack 408-970-5600, request 70750 www.siliconix.com
S-60752-Rev. 05-Apr-99
Si9142
CONFIGURATION ORDERING INFORMATION
Part Number
Si9142CW
Temperature Range
70°C
Packaging
Bulk
Si9142
Temperature Range
70°C
Board Type
Surface Mount
DESCRIPTION
Number
Symbol
SS/Enable COMP VREF AGND ROSC SYNC PWR_GOOD PGND VL(out) VL(in) Error amplifier non-inverting input
Description
Soft-Start: Capacitor programmable logic level controlled shutdown Feedback Compensation node external feedback circuit Input Voltage: 4.75 13.2 1.30 precision reference Ground: Connect quiet ground. External resistor determine switching frequency internally connected Synchronizing Clock Power_Good window comparator output Power Ground Low-side gate driver synchronous rectifier 5.5-V reference gate drive supply Reference input, connect filter from VL(out) Inductor connection node High-side gate driver power switch Boost capacitor connection node generate high-side gate drive Programmable over current limit
S-60752-Rev. 05-Apr-99
FaxBack 408-970-5600, request 70750 www.siliconix.com
Si9142
TIMING DIAGRAMS
FIGURE Start-up Timing Sequence
FaxBack 408-970-5600, request 70750 www.siliconix.com
S-60752-Rev. 05-Apr-99
Si9142
FIGURE Timing Diagram
FIGURE Timing Diagram
S-60752-Rev. 05-Apr-99
FaxBack 408-970-5600, request 70750 www.siliconix.com
Si9142
DESCRIPTION OPERATION
Si9142 voltage mode synchronous buck controller designed power high performance microprocessor power supply. voltage mode control provides efficiency cost saving advantages over current mode control high output current converters eliminating current sense resistor. Si9142 provides ultra-fast (5-µsec) transient response time necessary protection circuits demanded microprocessor supply designers. Non-Inverting Input non-inverting input error amplifier. converter output voltages equal greater than connected directly VREF. converter output voltages less than connected VREF through voltage divider. SS/Enable Soft-Start/Enable Soft-start accomplished connecting capacitor from this AGND. soft-start functions constant current source into this capacitor. logic (0.8 this disables output gate drives; oscillator continues function. logic high (2.4 enables output gate drives, assuming input voltage above UVLO threshold, that over-voltage over-current condition exists. Pins COMP Error Amplifier inverting input error amplifier. voltage this also connected internally input terminals PWR_GOOD comparators fault detection protection. error amplifier 10-MHz gainbandwidth when connected 20-pF load with input voltage. COMP output error amplifier. output voltage clamped maximum level avoid long delays saturation during large transient conditions. minimum COMP voltage diode drop below duty cycle voltage; maximum voltage diode drop above duty cycle voltage. Input Voltage should connected input voltage optimum performance. input voltage range Si9142 specified operate with either VDC. order accommodate tolerance possibility using this controller 2-cell notebook applications with battery charger, input voltage rated +15-V absolute maximum. VREF Reference Voltage reference voltage designed produce 1.30 ±1.6% over line temperature range, produce equally tight output regulation converter. reference should decoupled with least 100-nF capacitance. reference capable driving external load. Pins VL(out) VL(in) +5.5-V Linear Regulator VL(out) produces +5.5-V output used gate drive voltage both high- low-side external MOSFETs. gate drive voltage high-side MOSFET bootstrapped (VL(out) VDIODE) above input voltage. VL(out) should bypassed with least decoupling
S-60752-Rev. 05-Apr-99
AGND Analog Ground AGND analog ground power circuitry converter. This ground should separated locally from PGND, should have separate back input bypass capacitors. ROSC Oscillator Timing Resistor resistor from this AGND determines internal switching frequency oscillator. internal circuitry produces frequency accuracy with timing resistor. oscillator capable switching MHz. SYNC Synchronization SYNC signal generated from internal oscillator. When oscillator ramping positive, SYNC will logic high; when oscillator ramping negative, SYNC will logic low. SYNC used synchronize Si9142 external clock. particular, several Si9142s have their SYNC pins shorted together, they will switch same frequency phase, with frequency being fastest oscillator. PWR_GOOD Open Collector Power Good Signal This signals status output voltage. window comparator ±12% voltage pin, with tolerance PWR_GOOD signal open drain output capable sinking Pins PGND Power Ground PGND power ground high power circuitry converter. This ground should separated locally from AGND, should have separate plane back input bypass capacitors. Pins Low- High-Side Gate Drives high-side low-side gate drive external MOSFETs. Both source sink 2.5-A peak with 4.5-V gate drives. timing sequence high- low-side gate drives shown Figure internal break-beforemake time interval (tBBM) nsec prevents shootthrough current external MOSFETs. ringing from gate drive output's trace inductance produce negative voltages much negative with respect PGND. gate drive circuit capable withstanding these negative voltages without functional defects.
FaxBack 408-970-5600, request 70750 www.siliconix.com
Si9142
capacitance, should used other external loads. VL(in) drives internal circuitry. should connected through filter VL(out). Inductor Node node used internally float high-side n-channel MOSFET gate drive. During on-time this MOSFET, gate source voltage will (VL(out) VDIODE). node also used internally negative sense voltage overcurrent protection. Bootstrap Voltage external high-side n-channel MOSFET gate drive voltage derived bootstrapping VL(out) voltage input supply voltage. external 100-nF capacitor connected across pins charged (VL(out) VDIODE) when external low-side MOSFETs Then, when low-side MOSFETs turned off, internally connected order turn high-side MOSFET. turned startup ensure initial charging capacitor. Programmable Over-Current Protection over-current protection circuit senses voltage across external high-side n-channel MOSFET determine presence over-current condition. Current sensing occurs only during on-time this MOSFET. trigger level over-current circuit programmable selecting external resistor value connected from ICS. Once over-current circuit been triggered, disables both output gate drives within nsec. circuit also discharges soft-start capacitor shown timing diagram Figure Under Voltage Lock-Out (UVLO) internal UVLO circuit designed prevent converter from starting when insufficient input voltage present. UVLO disables oscillator, soft-start output drives Si9142 until VL(out) reaches Figure UVLO circuit 200-mV hysteresis prevent turn-on -off oscillations. When oscillator disabled, Si9142 stand-by mode, consumes only supply current. Start-up Timing Sequence Please refer Figure this description. When reaches VL(out) produces least VREF stabilized regulating. UVLO circuit enables oscillator soft-start circuits. Once soft-start voltage exceeds gate drive pulses begin, with duty cycle high-side MOSFET beginning gradually increasing until output voltage regulation.
APPLICATIONS
Setting Current Limit current limit comparing voltage drop across external high-side n-channel MOSFET with voltage dropped across sense resistor connected between ICS. draws constant current, thus equation governing overcurrent threshold
ILimit RMOSFET
Once on-state resistance MOSFET known, selected desired current limit. caution order: since MOSFET will normally quite warm, resistance used equation should maximum resistance elevated temperatures, typical resistance 25°C. designer should also leave adequate margin above normal output current, both account tolerances noise well permit initial high currents while charging output capacitors. Boost Diode application circuit shows 1N4148 diode boost circuit. This provides low-cost component this application. However, advantageous some circuits Schottky diode instead. difference that Schottky less forward drop than regular rectifier, this turn means somewhat greater gate drive voltage external high-side MOSFET. MOSFETs with high gate threshold and/or transconductance, additional gate drive prove very beneficial terms heating MOSFET, turn efficiency converter. 30-V Schottky works well this application. Grounding Si9142 provided with both analog power ground pins (AGND PGND, respectively). Because high gate drive currents Si9142 source, essential that these grounds separated. PGND should attached source external low-side MOSFET; AGND should attached small-signal components circuit, such timing resistor feedback resistor. Each these grounds should back independently input line capacitors, avoid ground loops.
S-60752-Rev. 05-Apr-99
FaxBack 408-970-5600, request 70750 www.siliconix.com
Si9142
FIGURE High Performance Converter
FaxBack 408-970-5600, request 70750 www.siliconix.com
S-60752-Rev. 05-Apr-99

Si9142 Synchronous Buck Controller High Performance Processors

Top Searches for this datasheet

Other recent searches