FS970x Series Data Sheet FS970x Series Data Sheet (V3.8) Dig

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FS970x Series Data Sheet FS970x Series Data Sheet (V3.8) Dig

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FS970x Series Data Sheet
FS970x Series Data Sheet (V3.8)
Digital Multi-function Meter (DMM) Front-end Chip
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FS970x Series Data Sheet TABLE CONTENTS
FS970X INTRODUCTION.4 1.1. FEATURES 1.1.1. General Features (FS9701A/B example).5 1.1.2. Measurement Range (FS9701B example) ELECTRICAL CHARACTERISTICS 2.1. BLOCK-DIAGRAM PACKAGING PINS 3.1. LQFP DEFINITION 3.2. DESCRIPTION TYPICAL APPLICATION CIRCUIT REGULATOR.13 5.1. VOLTAGE DETECTOR 5.2. SAVING MODE 5.3. ON/OFF POWER OUTPUT CLOCK BUZZER GENERATOR.17 6.1. CLOCK GENERATOR 6.2. BUZZER GENERATOR FUNCTION NETWORK.19 7.1. FUNCTION DECODER 7.1.1. Area Network Switch.21 7.2. FIXED VOLTAGE GENERATOR 7.3. POWER SUPPLY 7.4. MULTIPLEXERS PRE-FILTER 7.5. OPERATION AMPLIFIER COMPARATOR 7.5.1. Bandwidth Signal.28 ANALOG DIGITAL CONVERTER (ADC) 8.1. OPERATING THEORY 8.2. TRANSFER FUNCTION NON-IDEAL AFFECT 8.3. FUNCTION GAIN SETUP 8.4. DIGITAL FILTER 8.5. READING OPERATION 8.5.1. High-resolution, low-speed output.34 8.5.2. Low-resolution, high-speed output 8.5.3. Scale-type resistance measurement Analog Bargraph 8.6. CONVERSION DIGITAL OUTPUT EQUIVALENT VOLTAGE 8.7. DIFFERENT OUTPUT CODE DIFFERENT MODELS 8.8. OTHER CONTROL SETTING DIGITAL SIGNAL PROCESS 9.1. FREQUENCY COUNTER.39 9.1.1. reading process frequency counter 9.2. PEAK-HOLD SAMPLING PROCESS
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FS970x Series Data Sheet
MICRO PROCESSOR INTERFACE.41 10.1. CONTROL REGISTER 10.2. INTERRUPT PROCESS 10.3. MEASUREMENT REGISTERS BASIC MEASUREMENT APPLICATION 11.1. DCMV.46 11.1.1 mV.46 11.1.2 mV.47 11.2. VOLTAGE 11.3. VOLTAGE (ACV) 11.4. CURRENT (DCA) 11.5. CURRENT (ACA) 11.6. RESISTOR ().52 11.7. CAPACITOR.53 11.8. DIODE PACKAGE OUTLINE ATTACHMENT OP-AMP SPECIFICATIONS
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FS970x Series Data Sheet
FS970x Introduction
FS970x series Digital Multi-function Meter (DMM) front-end chip. core high resolution ADC, combined with function network, operation amplifier, comparator, digital filter, crystal oscillator circuit, digital control logic micro processor interface. FS970x includes only high-resolution output achieve accurate measurement, high-speed output display graph digital meter measure peak hold. Combined with micro processor, FS970x function auto-range measure DC/AC voltage, DC/AC current, resistance, frequency, peak hold diode, etc. addition, includes several sets programmable direct input expand product applicability (such pressure function, temperature function, etc.) There operation amplifiers built FS970x high impedance buffer DC/AC converter when measuring voltage. These amplifiers with other functions well even acting DC/AC converter. them connected external resistor build amplify circuit. reading from signal into still accuracy excellent noise immunity amplifier.
Max. resolution (counts)/ output (Hz)
Frequency counter
Speed output (HZ) resolution (counts)
AC/DC Converter
Voltage regulator
Diode testing
Voltage
Current
input
Peak hold
Buffer
path
Capacitor
Resistor
FS9701B FS9704B
There different versions FS970x with different specifications functions. With same micro processor FSP01 chip (programs), customers easily quickly develop different levels DDM.
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Chip
5000 80000
Chart FS970x series chips.
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1.1. Features
1.1.1.
FS970x Series Data Sheet
General Features (FS9701A/B example)
Built-in high resolution 5,000 counts, high-resolution low-speed input, times sec. counts, resolution, high-speed input, times sec. Built-in voltage regulator with input, ±3.2V output Under voltage, power consumption under 1.2mA Standby saving mode battery detection Good CMRR 50/60HZ Built-in crystal oscillator circuit beeper driver Standard 4-bit parallel interface directly connect micro processor port programmable direct input channel LQFP package
1.1.2.
Measurement Range (FS9701B example)
500.0 50.00mVDC voltage, high impedance input. 0.5000V, 5.000 50.00 500.0 1000 voltage 500.0 5.000 50.00mA, 500.0 5.000 10.00 current 500.0 5.000 50.00 500.0 5.000 50.00 resistance 0.5000V, 5.000 50.00 500.0 1000 voltage 500.0 5.000 50.00mA, 500.0 5.000 10.00 current 10.00 100.0 1.000 uF,10.00 100.0 capacitor 50.00 500.0 5.000 Khz, 50.00 Khz, 500.0 Khz, 5.000 frequency. Diode forward bias voltage test, with maximum forward voltage above peak hold detector
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FS970x Series Data Sheet
Electrical Characteristics
(VBAT TA=+25, unless otherwise indicated) PARAMETER Zero Input Reading Zero Reading Drift TEST CONDITIONS VIN=0V, 500mV Scale VIN=0V, 0<TA<+70 MIN. TYP. MAX. UNITS Counts Counts Counts Counts
Linearity (Max. deviation from 500mV Scale best straight line fit) Input Common-Mode Rejection Ratio VCM=±1V, VIN=0V, 500mV Scale
Input Common-Mode Voltage VIN=0V, 500mV Scale, Counts Range Noise (p-p Value Exceeding Time) VIN=0V, 500mV Scale
Rollover Error (Difference -VIN=+VIN=500.00mV reading equal positive negative inputs near Full Scale) Input Leakage Current Scale Factor Temperature Coefficient Analog Ground Voltage (With respect VSS) Analog Supply Voltage (With respect VSS) Digital Supply Voltage (With respect VSS) Analog Ground Source Capability Analog Ground Sink Capability Analog Supply Source Capability VBAT Battery Detection Voltage VO=-0.1V VO=0.1V VO=0.1V VIN=0V VIN=500.00mV, 0<TA<+70
ppm/
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PARAMETER VBAT Operating Current
FS970x Series Data Sheet
TEST CONDITIONS VIN=0, 500mV Scale RIN=1K, Scale MIN. TYP. 3000 VIN=0 VIN=0 VIN=0.5V VO=-0.1V, Scale VIN=600mVP-P VIN=40mVrms ENSCHMT=1 Gain=1 VIN=0.4Vrms, 100KHz VIN=0.4Vrms, 50KHz VIN=0.4Vrms, 20KHz VIN=0.4Vrms, 10KHz calibration VIN=0.4Vrms, 50Hz 0.25 0.05 0.01 0.0025 0.23 0.045 0.005 0.07 500K MAX. UNITS
Sleep Current Current ACOP Current Comparator Current OSRC Source Capability Bandwidth ACOP Gain ACOP Bandwidth Comparator
Hysteresis Comparator ACBUF Linearity Error (RL=10M, CL=30pF)
(RL=10K, CL=30pF)
VIN=0.4Vrms, 100KHz VIN=0.4Vrms, 50KHz VIN=0.4Vrms, 20KHz VIN=0.4Vrms, 10KHz calibration VIN=0.4Vrms, 50Hz
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PARAMETER ACBUF Linearity Error (RL=10M, CL=30pF)
FS970x Series Data Sheet
TEST CONDITIONS Gain=10 VIN=0.04Vrms, 20KHz VIN=0.04Vrms, 10KHz VIN=0.04Vrms, 5KHz VIN=0.04Vrms, 1KHz calibration VIN=0.04Vrms, 50Hz 1.14 0.27 1.14 0.27 0.05 MIN. TYP. MAX. UNITS
(RL=10K, CL=30pF)
VIN=0.04Vrms, 20KHz VIN=0.04Vrms, 10KHz VIN=0.04Vrms, 5KHz VIN=0.04Vrms, 1KHz calibration VIN=0.04Vrms, 50Hz
RCTOP Linearity Error
VIN=0.2Vrms, 100Hz calibration VIN=0.2Vrms, 10KHz
Switch Resistance: Parasitic Capacitance Digital Output High Digital Output Digital Input High Digital Input IOUT=-1mA IOUT=1mA
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2.1. Block-diagram
AC-to-DC external network
FS970x Series Data Sheet
Input
Signal Conditioning Network
Function, Range Routers, Opamps, Comparators Source
High resolution input volatge buffers
Digital Signal Processing
(Counters, Filters Control Logic)
Regulation network precise zenner diode
Power Regulator Battery Detector
Microprocessor Interface Control Logic Oscillator Colck generator
Microprocessor (master)
VBAT
Battery VBAT AGND Crystal VBAT
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FS970x Series Data Sheet
Packaging Pins
3.1. LQFP Definition
RST_ IRQO XTALO XTALI VSSD
VBAT
TENM
FCNTI
ONEM
CMP1
HUNK
CMP2
TENK
ONEK
SGND
AGND
FS970x mm/10
OSCO
VDDA
VCCS
VCCR
VDDP
VDDS
ADRF
GNDR
VSSA ACHO REFH RCTO ACLO RCTN CSFB RCTP
3.2. Description
LQFP Type Symbol VSSD XTALI,XTALO IRQO AD<3:0> RST_ Description Global Ground-3.2 terminals crystal oscillator circuit Output terminal BUZZER function Interrupt output terminal when updating data ports Address Data Lines When Active_low, read values from FS970x When Active_low, write values FS970x When Active_Hi, AD<3:0> acts address line When Active_low, enable FS970x interface Digital power supply+1.8 Reset registers when Active_low connector compensation capacitor function
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18-22 23-24 35-36 37-38 39-40 42-43 44-48 55-57 59-61
FS970x Series Data Sheet
terminal pre-filter capacitor terminal resistors router terminal pre-filter capacitor sensing point analog ground Analog ground0 Positive analog power supply+3.0 input DCmV function terminal current function negative terminal reference under resistance measurement input voltage reference Negative analog power supply-3.2 output Zener diode terminal Zener diode function output terminals AC-to-DC function connection buffer OPAMP terminal OPAMP AC-to-DC function output terminal OPAMP AC-to-DC function output terminals rectify function AC-to-DC measurement input terminal output terminal through analog switch control analog ground internal voltage regulator output terminal through analog switch control power supply regulator (+3.0 output regulator+1.8 output terminal through analog switch control Digital power supply+1.8 output crystal oscillator circuit (the output frequency programmable) use. output comparator input terminal frequency counter terminal battery
TENM,ONEM,HUNK, TENK,ONEK FTA,FTB SGND AGND VDDA ADRF VSSA REFH CSFB ACH, ACB, RCTP, RCTN RCTO ACHO, ACLO AX1-AX5 GNDR VDDS VDDP VCCR VCCS OSCO CMP1 FCNTI VBAT
(Digital) (Analog) (Power) (Output) (Input) example, stands Digital Input Output pin.
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FS970x Series Data Sheet
Typical Application Circuit
Buzzer 4.0000 VBAT
mA+uA
XTALI
XTALO
RST_
CKIN
PANEL
VDDS mA+uA 0.99 0.01 VBAT
VDDA
MicroProcessor
PUSH BUTTONS
Other Pripheral
COMMON
IRQO OSCO
FUSE VOLT+OHM+DT
TENM
ADRF
AGND
DCmV
DCV+OHM+DCmV+CA
REFH VDDP CSFB ONEM VCCR
AGND COMMON AGND COMMON
LM385/1.235V
HUNK
VDDS
GNDR TENK ONEK ACLO RCTO
AGND
VBAT 1N914 1N914
S81250 Vout
VDDS
ACHO
VDDS AGND VDDS
SGND RCTP AGND VDDS VSSD VSSA
AGND
AGND
VDDS
AGND
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FS970x Series Data Sheet
Regulator
VBAT
S81250
VDDP
VDDP REFH GNDR AGND
Battery
VCCR
ENGNDR_ VSSA
FS970x Regulator
Graph FS970x Regulator Block-diagram.
FS970x Regulator, shown Graph needs connected with S81250 low-cost regulator convert battery voltage above 6.8V voltage approx. 6.3V. There functions power: positive voltage (negative voltage VSSA) analog circuit regulator), other reference voltage regulators. power digital circuit chip supplied VCC. digital signal ground VSSD. digital signal ground VSSD negative supply analog circuit VSSA chip connected chip foundation thousand ohms. shown Graph FS970x regulator circuit refers respectively voltage VDDP REFH; same time, adjusting voltage VCCR, GNDR supply chip. voltage VCCR GNDR will 3.2V. This analog supply directly supply AD737 enable meter measure true root mean square signal. supply source FS970x selected users, either from chip itself from external connection. analog supply within chip provided VDDA, AGND VSSA. Thus, directly feeding output regulator VCCR, GNDR into VCC, AGND VSSA will supply chip itself. system supply, connected directly VCC, AGND VSSA, instead using VCCR GNDR.
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FS970x Series Data Sheet
power consumption analog static current, with equivalent power consumption. major reason that will affect this power consumption change between each function. power consumption FS970x analog parts designed under 1.2mA digital parts under 0.5mA. even more stringent power consumption design under saving mode, connecting chip's analog supply VDDA VDDS will reduce idle VDDA consumption under saving mode. details about VDDS, please 5.3.
5.1. Voltage Detector
VBAT
360K BATTER 303K AGND VSSD
ENLBS
Graph
Voltage Detector.
voltage detector shown Graph After voltage VBAT divided resistor, will flow into voltage detector. output detector LBO, used judge whether battery voltage VBAT lower than 6.8V. it's lower than 6.8V, output "Hi", meaning that needs battery change. Before reading LBO, ENLBS "Hi". After approx. pull back read LBO. voltage flow into ADC, controlled multiplexers. also directly measured ADC. battery voltage calculated Formula
Formula
Under saving mode, setting ENGNDR_ (MISC2<1>) will turn GNDR order save power consumption.
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5.2. Saving Mode
FS970x Series Data Sheet
FS970x, power-consumption related circuits, except VCCR generator, turned FS970X registers save power. power-consumption related control signals components shown Chart FS970x components turned off, only VCCR regulator will still running. This keeps chip power consumption under According setup Chart power consumption VDDA drift. Therefore, aside from setup procedures Chart supply VDDA should come from VDDS considering saving mode. doing S81250 will only component that consumes power under saving mode. Register Control circuit Saving mode value Related power consumption circuit
Fixed voltage generator
RGD>3:0> SRF<7:6> SCP<0> AFT<6> AFT<4> ADG<7> SETADC<7:6> MISC1<4> MISC1<3> MISC2<1>
MODE<3:0> SOSR<1:0> CMPEN1 RCTEN ACEN ENAD ENVDS, ENVCS ENOSCO_ ENXTL_ ENGNDR_
000x
power supply Comparator Full-wave retifier buffer On/off power output OSCO output Crystal oscillator circuit
AGND voltage regulator
Chart Saving Mode Setup.
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5.3. On/Off Power Output
FS970x Series Data Sheet
VDDP(52)/ VCC(55) VDDS(51)/ VCCS(54)
ENVDS/ ENVCS
Graph On/Off power output.
VDDS VCCS on/off power output VDDP VCC. circuit shown Graph VDDP/VCC flows into PMOS, output from VDDS/VCCS. PMOS on/off status controlled ENVDS/ ENVCS. When under PMOS respectively under open/close status. Connecting VDDA VDDS under saving mode, this will decrease VDDA power consumption
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FS970x Series Data Sheet
Clock Buzzer Generator
6.1. Clock Generator
XTALI 4.0000 XTALO ENXTL_ FSDIV TBDIV ENBP
DIVIDER
CNTBP ENOSCO_
Buzzer
OSCO
OSCO
VBAT 1/FTB 1/FS
Graph Clock Generator.
Clock generator shown Graph connected 4.000 crystal oscillator produce 4.000 clock frequency. then divided FTB, frequencies divider. Among these, used ADC. (please refer details.) used digital circuits, such reference frequency frequency counter (please refer section 9.1). used buzzer initiate buzzing. respectively controlled ENXTAL_. TBDIV FSDIV. true value Chart shown Chart ENXTAL_ TBDIV 1.0000 1.0000 125.0 125.0 FSDIV 166.67 83.33 166.67 83.33
Chart generator true value Chart.
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6.2. Buzzer Generator
FS970x Series Data Sheet
generator controlled ENBP. CNTBP CMP1. true value Chart shown Chart ENBP CNTBP CMP1
Chart true value Chart
output buzzer, BZR, open drain output. connected external pull-up resistor pull "Hi" output required voltage. When ENBP "Hi" CMP1 CNTBP both "Hi", will produce approx. square-wave output initiate buzzer. ENBP CNTBP directly digital interface while value CMP1 related measurement status. Please refer Function Network details. When ENOSCO_=0, square-wave output OSCO fixed 2.000 MHz. When ENOSCO_=1,the fixed output This will save power consumption.
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FS970x Series Data Sheet
Function Network
AGND
FUNCTION
FUN1,2 FUN1 FUN2 AGND 27nF
ACHO
RCTO
RCTN
ACLO
RCTP
AFT<7:0> SCP<7:0> SIN<7:0> SRF<7:0> RGD<7:0> SOSR<1:0> RANGE<3:0> EXTD RCTEN ACDIV ACEN ENSCHMT CAPM CPN<1> SINL<2:0> SRFL<2:0> MODE<3:0>
CPN<0> CMPEN1
ACDIV
SCMPH<3:0> SINH<3:0> SRFH<1:0>
SCMPL<1:0> BPFTR
ACDIV
BPACBF RCTOP ACBUF mA+uA CMPH ACEN SINH<3:0> 0.99 0.01 COMMON SGND SGND SGND ADRF ACBO CMPH endvo INHMUX SINL<2:0> SGND INLMUX SRFH<1:0> ADRF VRHMUX FTIN ACBO RCTEN
BPFTR
SRFL<2:0> AGND AGND VRLMUX
AGND
SCMPH<3:0> ADRF CMPH CAPTG CMPH
DCmV
Vcntd1 Vsrc1 CAPTG CMPEN1 CMPEN2 SCMPL<1:0> AGND Vsrc1 Vcapc2 Vrfh cntd Vcntd1 CMPLMUX CAPM CAPTG Vcapc1 Vcapc2 Vcapd2 CAPL FCNTI CMPL CMP1 CMPEN2 FCNT CMP1
DCmV
DCmV
AGND
Vcapd1 Vcapd2 Vcapc2 Vcapc1 SGND AGND
onek<0> DCV+ACV onek<2> ONEK onek<1>
CMPHMUX
CMPEN2 CMP2 CMP2
AGND TENK
tenk<0> tenk<1>
Vcapd1 CAPMUX
tenk<2> (VDD) hunk<0> HUNK 100K hunk<2> hunk<1> OSRO TBDIV SOSR1:0 CAPTG
OSRC OSRC
Vrefh AGND
ADRF
ADRF
onem<0> 1.5K onem<2> +CAP FUSE VOLT+OHM+ DT+CAP EXCEPT CPN<0> tenm<1> onek<2:0> tenk<2:0> hunk<2:0> tenm<1:0> AGND CPN<1> FUNCTION DECODER onem<2:0> TENM tenm<0> tenm<1> ONEM onem<1> OSRMUX
0000_0000 0000_0000 0000_0000 0000_0000
cntd endvo
Vcntd Vsrc1 Vcapd1 MODE<3:0> RANGE<3:0> Vcapd2 Vcapc2 Vcapc1 Vrfh VSRC REFH TBDIV
0000_0000
REFH
Graph FS970x function network diagram
Function Network, shown Graph includes major parts: function decoder, area network switch, fixed voltage generator, power supply, multiplexers pre-filter, operation amplifier comparator.
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7.1. Function Decoder
FS970x Series Data Sheet
Function decoder includes input MODE RANGE. RANGE controls area network switch determine measurement range, MODE controls function network signal determine measurement mode. shown Chart setup register MODE3:0 (represents MODE<3:0>) decode control signals such cap. sdt. vsr. cntd endvo. also controls measurement mode operation status function network. When High Bandwidth capable processing signal more than MHz, direct output SDV. Refer section 7.5.1 details. Measurement Mode DCmV, DCV, ACV, DIODE High Bandwidth Resistor Continuity Capacitor
Chart
MODE3:0 cntd 0000 0001 0011 100x 101x
endvo
Control Measurement mode
shown Chart area network switch controlled both MODE3:0 RANGE3:0. four bits RANGE directly controls network resistor path: 10k, 100k, same time, path determined Formula
a+b+c+d
Under Range Divider mode, area network becomes decay network. controls area network on/off status determine different measurement range according setup RANGE3:0. Under Resistor mode, area network will become reference resistor initiated appropriate returned supply. selects different reference resistor determine different measurement range according setup RANGE3:0. Resistor represent respectively whether reference resistor parallel with resistor. Under Capacitor mode, area network becomes charge/discharge resistor with power supply. Capacitor also represent whether charge/discharge resistor parallel with resistor.
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Range Mode Range Divider Resistor Resistor Capacitor Capacitor
FS970x Series Data Sheet
MODE3:0 RANGE3:0 onek2:0 tenk2:0 hunk2:0 onem2:0 tenm1:0 00xx 1000 1001 1010 1011 abcd abcd abcd abcd abcd
Chart
Decay network switch.
7.1.1.
Area Network Switch Combining area network switch external high-precision resistor becomes measurement network. transfers signal sensor into suitable voltage range measures signal. function decoder controls measurement range on/off status. Graph Section details. Take DC5V example, using Chart reference, setting MODE3:0=0000 RANGE=0001 will make onek2:0=tenk2:0=hunk2:0=000, onem2:0=011, tenm1:0=01. When corresponding this value area network low-left corner Graph switches under open status except tenm<0>, onem<1>, onem<2>. Thus, connecting external resistor network will make ten-times decay circuit achieve decay function required DC5V.
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7.2. Fixed Voltage Generator
FS970x Series Data Sheet
When under capacity measuring, short testing, resistor measuring, required power supply provided this block. output this block includes Vcntd, Vsrc1, Vcapd1, Vcapd2, Vcapc2, Vcapc1, Vrfh. output voltage controlled TBDIV, shown below. comes from decoding MODE3:0 input function decoder. TBDIV directly register. INPUT TBDIV Vrfh Vcapc1 1.58 Vcapc2 0.64 1.65 OUTPUT Vcapd2 0.56 1.45 Vcapd1 1.52 Vsrc1 0.16 Vcntd 0.04
Chart Voltage output fixed voltage generator.
When TBDIV=0, block refers voltage REFH, shown Chart REFH=1.2V. REFH 0.6V, voltage generated 0.6V, 0.32 0.28 0.08 0.02 When TBDIV=1, refers voltage VDD, shown Chart which voltage output voltage being under normal condition. Vrfh reference voltage power supply when measuring resistance capacity. Vcapc1 Vcapd1 respectively reference voltage charge/discharge comparator Vcapc1 (charging) Vacpd1 (discharging) when measuring capacity. Vcapc2 Vcapd2 second reference voltage charge/discharge comparator. According measuring capacity range, reference voltage selected CAPM setup register. (See Chart details). Vcntd reference voltage comparator under short testing. There special function Vsrc1, users customize according their needs.
7.3. Power Supply
power supply flows directly into decay network, providing voltage shown Chart Among them, determined function decoder. When cap=0, it's under capacity measuring mode. application, represents resistance measurement. this time, output controlled SOSR1:0, shown Chart SOSR1:0 register.
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FS970x Series Data Sheet
When it's under capacity measuring mode. this time, output power supply irrelevant SOSR1:0, controlled TBDIV CAPTG. When TBDIV Vrfh approx. charge/discharge voltage approx.1.2V. When TBDIV=1, Vrfh approx. (VDD), charge/discharge voltage also approx. This improves charge/discharge speed capacity measuring. CAPTG output comparator CMP1. controls charge/discharge selection power supply measuring capacity. When output VDD, thevoltage voltage pins, which will affected on/off resistors path real voltage load will affected load. When output other than VDD, on/off resistor ignored because operation amplifier high gain negative feedback. real voltage load affected load ignored well. Under kinds output, maximum power approx. ±1.2mA.
INPUT TBDIV CAPTG SOSR1:0
OUTPUT OSRO high impendence Vrfh Vrfh (REFH) AGND Vrfh (VDD) AGND
Chart power supply true-value Chart
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FS970x Series Data Sheet
7.4. Multiplexers pre-filter
Through multiplexers such INHMUX, INLMUX, VRHMUX VRLMUX, selectable signals FTIN, INL, VRH, VRL. FTIN first flow through pre-filter, then into full differential amplifier input ADC. same time, they bypass pre-filter flow directly into through BPFTR FTR. Each output path directly controlled registers. Details shown Chart Chart Chart Chart
Name SINH
0000
0001
0010 1010
SGND 0011 1011
0100 1100
0101 1101
0110 1110
ADRF 0111
Name ACBO CMPH SINH 1000 1001
Chart
FTIN multiplexers setup
Name SGND SINL
Chart multiplexers setup.
Name SRFH
ADRF
Chart multiplexers setup.
Name AGND SRFL
AGND
Chart multiplexers setup. signal into comparator selected comparator multiplexers CMPMUX. path controlled registers well, show below.
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Name SCMPH Name SCMPH
FS970x Series Data Sheet
0000 0001 0010 ADRF 0011 0100 0101 Vcntd 0110 1110 Vsrc1 0111 1111
Vcapd1 Vcapd2 Vcapc2 Vcapc1 SGND AGND 1000 1001 1010 1011 1100 1101
Chart CMPH multiplexers setup. negative input CMP1, controlled cap, cntd, SCMPL1:0, CAPM, CAPTG. Details shown Chart When cap=0 cntd=0, output irrelevant CAPM CAPTG. directly selected SCMPL1:0. When cap=0 cntd=1, it's under short testing mode. output fixed Vcntd. When cap=1, it's under capacitor measuring mode. this time, output irrelevant cntd SCMPL1:0. When CAPM=0, means medium capacity measuring. output controlled CAPTG; they Vcapc1 Vcapd1. When CAPM=1, means high capacity measuring. output controlled CAPTG. They Vcapc2 Vcapd2.
OUTPUT
cntd SCMPL1:0 CAPM CAPTG
Vrfh
AGND Vsrc1 Vcapc2
Vcntd Vcapc1 Vcapd1 Vcapc2 Vcapd2
Chart
multiplexers setup.
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7.5. Operation Amplifier Comparator
block composed operation amplifier comparator include buffer block, full-wave rectifiers block, comparator block.
AGND ACBO
ACDIV ACDIV
BPACBF
ACBUF CMPH ACEN
Graph buffer block.
shown Graph buffer block controlled ACBUF ACDIV. becomes gain network when connecting with external resistor. Whether ACBUF works directly controlled ACEN. When ACEN=0, turns buffer output becomes high impedance. Signal enters through CMPH, flows from ACBO 37th ACB. ACDIV same time controls gain. ACDIV=0, gain buffer ACDIV=1, gain buffer determined external network resistor. Typical Application Circuit, gain becomes When gain side wave flowing through buffer will reduced lower than 0.5%. bandwidth limited frequency response full-wave rectifier. signal bandwidth higher than100 kHz, BPACBF=1, will change output source (ACA) instead buffer.
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FS970x Series Data Sheet
ACHO
EXTD
EXTD
ACLO
RCTP RCTN
12.3 RCTO
RCTOP RCTEN
Graph Full-wave rectifier switch block
shown Graph signal, inputting from RCTP going through rectifier, will obtain full differential amplifier signal from ACHO ACLO. will then connected external low-pass filter network arithmetic average. result value, absolute average AC/DC voltage, then flows into displays. full-wave rectifier FS970x built required resistor. rectifier diode controlled EXTD select built-in externally connected. When EXTD=0, means that bandwidth built-in diode 3kHz under precision When EXTD=1, means that bandwidth external diode using 1N914 10kHz under precision increases bandwidth rectifier using faster diode adding high-frequency compensation circuitry full-wave rectifier. enable capability rectifier controlled RCTEN. When RCTEN turning operation amplifier will save power consumption.
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FS970x Series Data Sheet
CMP1 ENSCHMT CMP1 FCNT/ CAPTG
CMPH CMP1EN
Graph Comparator Block-diagram.
shown Graph comparator CMP1 directly enable action control register CMPEN1. Schmidt trigger function comparator selected enable ENSCHMT. When ENSCHMT=0, comparator delay, suitable capacity measurement. When ENSCHMT=1, comparator delay voltage approx. 0.1VRMS, suitable frequency measurement. negative input CPL, shown Chart positive input CMPH, shown Chart output flows directly into frequency counter through FCNT controls charge/discharge function capacity measurement CAPTG shown Chart 14)It also transferred through (SMP 1)by reverser logic value obtained control register. shown Chart 18).
7.5.1.
Bandwidth Signal According section 7.5When providing appropriate frequency compensation decay network, FS970x chip directly process signal under frequency approx. kHz. bandwidth signal over buffer ACBUF FS970x will unable process. Thus, setting BPACBF=1, high-frequency signal will bypass buffer, flow directly from ACA, shown upper left corner Graph However, when bandwidth signal higher than MHz, signal flows from SDV, through CMPHMUX ACA, on/off resistor parastic capact path will decay high-frequency signal dramatically, causing problems frequency response. Therefore, when processing signal higher than MHz, setting MODE3:0=0011 will make endvo=1. this time, signal SDV, through CMOS switch controlled endvo, flows directly from DVO, shown upper left corner Graph
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FS970x Series Data Sheet
Analog Digital Converter (ADC)
8.1. operating theory
This high-resolution adapts modulation delta sigma. samples consecutive analog input signal sampling frequency higher frequency width input signal. will then converted into one-bit code modulation delta sigma. then filters high-frequency noise converter digital filter chip. becomes high-resolution digital coding applied high-resolution DMM. Besides, this kind converter only performs 1-bit transfer analog-end; therefore, it's with better linear characteristics. signal input reference voltage input will full differential amplifier input, with good CMRR, which reject common mode signal.
ANALOG INPUT
ANALOG INTEGRATOR
DIGITAL PASS DECIMATION FILTER COMPARATOR
Dout
Vref -Vref -Vref, Vref, Vref Vref
Graph concept diagram.
shown Graph includes analog differentor integrator, comparator, one-bit digital low-pass filter. analog input signal taken from consecutively
sampled input, deduct directly from expected voltage. difference will then flow into analog integrator, then product predicted digital comparator. will then converted expected voltage+Vref -Vref ADC, reversely feed integrator stable negative feedback. integrator unlimited gain therefore, speed change input signal smaller than speed sampling, average expected voltage signal the- converter will very close input signal. It's considered equivalent under certain resolution. Thus, one-bit digital converted from comparator equal analog signal value Vref. Therefore, take one-bit digital perform arithmetical average digital filter high-resolution digital.
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FS970x Series Data Sheet
8.2. Transfer Function Non-ideal affect
vref
Graph10. ADC.
shown Graph there sets input output voltage input reference voltage input output ideal transfer function
Formula
represents gain value ADC.
However, reality ideal. relationship
Formula
represent respectively gain offset voltage ADC. They both affected
during manufacturing, vary every single chip Under most applications ADC, reference voltage fixed value Vrrf converts variable voltage into equivalent value Vrrf Examples AC/DC voltage measurement AC/DC currency measurement DMM. this kind application, reference voltage fixed; thus, Formula simplified
Formula
Vref
fixed value.
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FS970x Series Data Sheet
However, application DMM, most often used type measurement resistor scale-type measurement. reference voltage will vary with resistor, fixed value. Formula will reflect actual situation, needs modified
Rref
Formula Whereas,
function reference voltage. application measurement
scale-type resistors, will learn that related resistor FS970x includes kinds output: high-resolution, low-speed low-resolution, high-speed. Under high-resolution, low-speed output, offset voltage been eliminated. transfer function converts from ideal linear from Formula Under low-resolution, high-speed output, offset voltage still exists. transfer function comes from either Formula Formula according different condition. Chapter details.
8.3. Function Gain Setup
ADG<0>
ADG<1>
0.25
ADG<2>
signal input
ADG<4>
VREF
0.25
ADG<5>
reference input
ADG<3>
Graph FS970x Gain setup.
shown Graph input FS970x includes four different gain paths.
They
independently controlled ADG<3:0> bits) register. input reference voltage includes different gain paths. They independently controlled ADG<5:4>(2 bits) register. gain values approximation. Precise gain values only available after calibration. With suitable gain option control, kinds measurement applied best dynamic range ADC. Chart shows setup three typical functions ADG<5:0> application DMM.
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FS970x Series Data Sheet
function function function
ADG<5:0>
Reference voltage gainGREFi
01_0011
11_0111
11_1000
Input voltage gain SIGi
Chart
970x Typical function setup.
measurement transfer functions each function
Formula
SIGi REFi
reference voltage each function gain approximation input voltage shown Chart actual precise gain value offset voltage should obtained from calibration.
8.4. Digital Filter
shown Graph 1-bit output from comparator must through digital low-pass filter perform calculation similar arithmetic average become high-resolution multi-bit resolution. transfer function digital filter used 970x
Formula
sin( sin(f
Whereas, number filter (TAP). Assuming sampling frequency 166kHz number filter 16600, frequency response Graph filter shown Graph first zero-point would found
Formula
166000 16600
Thereafter, integer multiple points first zero-point occur zero-point. signal around zero-point will completely filtered filter. frequency responses shown Graph have good suppressing effect noise same token, assuming
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FS970x Series Data Sheet
sampling frequency 83kHz, number filter still 16600, then, first zero-point position calculated There this kind programmable digital filters
FS970x, namely, COMB1 COMB2. Their output SUM1 SUM2 respectively. number COMB1is higher, often used measure high resolution. number COMB2 lower; high-speed, low-resolution output used peak-hold sampling analog graph. numbers COMB1 COMB2 both programmable. They TPS1 TPS2 respectively, shown Chart Taking sampling frequency 166.7 example, location first zero-point calculated Chart
-100 -120 -140 -160
Graph 12Digital filter frequency response
970x
actual resolution each status defined actual measurement. COMB1TPS1 COMB2TPS2
TPSX<1:0> NumberN 0-point frequency NumberN 0-point frequency
Chart
16384 8192 4096 2048
10.17 20.34 40.68 81.40
651.17 1302.34 2604.68 5209.38
Digital Filter number setup zero-point locationFS=166.7 kHz.
Because delay digital filter, bandwidth signal pulse needs greater than four-times output period input signal ADC. example, when TPS2 output period COMB2 will
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FS970x Series Data Sheet
5209
Formula
Therefore, pulse bandwidth input signal must greater than 0.769 that value effectively converted ADC. When sampling frequency (FS) 166.7 kHz, output reading SUM2 from COMB2 detect smallest pulse bandwidth TPS2, shown Chart TPS2<1:0> Output frequency
Detectable smallest pulse bandwidth
0.769
1.53
3.06
0.65 6.12
Chart relationship between detectable smallest pulse bandwidth TPS2.
8.5. Reading operation
described 8.2, circuitry FS970x might drift causes offset voltage because manufacturing process. This might cause variance reading ADC. eliminate offset variance, it's necessary change setup CYS<1:0> register SETADC. There three different working modes. These modes influence reading operation high-resolution low-resolution. They described below: 8.5.1. High-resolution, low-speed output When CYS<1:0>=00, input becomes short; then, read negative value offset voltage from SUM1. When CYS<1:0>=11, equivalent digit value voltage read from SUM1, shown Formula When CYS<1:0>=01, then, reading value SUM1 equal ideal reading linear voltage. transfer function shown Formula used measurement high resolution. When CYS<1:0>01, output frequency SUM1is first zero-point frequency COMB1, shown Formula When CYS<1:0> =01, output frequency equals
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8.5.2.
FS970x Series Data Sheet
Low-resolution, high-speed output When CYS<1:0>=00, input becomes short; then, read negative value offset voltage from SUM2. used self-calibration. When CYS<1:0>=11, equivalent digit value voltage read from SUM2, shown Formula used peak-hold sampling measurement. When CYS<1:0>=01, transfer function resolution output SUM2 should become revision from Formula
Formula
value read from SUM2 when power-on turning rotary, CYS<1:0>=00. Therefore, flow-Chart operation display fast output shown Graph Whereas,
ideal values non-offset voltage, calculated from SUM2. used Bargraph
display kinds high resolution measurement.
Interrupt
read SUM2<15:0>
SUM2<0>=0
SUM2<0>
SUM2<0>=1
SUM2<15:0>-Dos
Dos-SUM2<15:0>
Display
Wait next interrupt
Graph flow-Chart operation display fast output.
output frequency fast same first zero-point frequency COMB2. When sampling frequency =166 kHz, TPS2<1:0>=11, then, output frequency will about
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8.5.3.
FS970x Series Data Sheet
Scale-type resistance measurement Analog Bargraph FS970x equipped with fast output SUM2. application DMM, used Analog Bargraph display. However, shown Formula when performing scale-type resistor measurement, reference voltage feeding longer constant value. Thus, equivalent digital value offset voltage longer constant value, either. varies with resistor. method deduction when performing calculation, described Section 8.5.2, longer adequate. shown Graph reference voltage below varies between range V~1.2 According Formula will vary dramatically, cause problems Analog Bargraph. Generally speaking, Analog Bargraph display approx. digits. accuracy requirement strict; thus, problem solved using section approximation. That say, when measuring resistor, operation Analog Bargraph processed under following three conditions:
1.2V
RREF
0.686
RREF
0.706
RREF
1.176 0.789
RREF
1.198 0.799
RREF
1.20 0.80
RREF
1.20 0.20
RFUSE+PTC
RFUSE+PTC
RFUSE+PTC
RFUSE+PTC
RFUSE+PTC
RFUSE+PTC 0.40
0.343
0.353
0.395
0.399
1.00
AGND
AGND
AGND
AGND
AGND
AGND
Graph converting voltage range scale-type resistor measurement.
condition resistance under obtained setting reference voltage equivalent generated fixed voltage generator chip. shown Chart through ACBUF output, connecting then into VRH. obtained through ACBUF, connecting AX5, through power supply, returning VRH.
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FS970x Series Data Sheet
condition middle resistance between obtained setting reference voltage equivalent Under this condition, value, just like other measuring
value, processed same parameter.
condition high resistance Because various range reference voltage great, value easily approximate number. Therefore obtained reducing Bargrapg display speed using reading high resolution output, reduce digit Bargraph digit.
using method illustrated this section reference voltage between 1.0V when resistor file calibrate under respectively. According different measurement range select different Then using calculation shown 8.5.2, complete calculation digit fast Bargraph display.
8.6. Conversion Digital Output Equivalent Voltage
Take high resolution digital output FS970x, output, SUM1<23:0>, compensation value 2/24bits. Whereas, SUM1<23> symbol positive, negative. floating point locates between SUM1<22> SUM1<21>. Assuming equivalent floating point calculation
SUM1 00.10 1000 0000 0000 0000 0000
Formula
0.125 0.625
Assuming equivalent floating point calculation
11.01 1111 1111 1111 1111 1111
Formula
-(00.10 0000 0000 0000 0000 0001) -0.5000002384
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FS970x Series Data Sheet
shown Formula when gain equals ideal value reference voltage Vref equals 1.00000V. From reading 0010_1000_0000_0000_0000_000, voltage calculated
Vref
1.00000 0.625 0.62500
When reading 1101_1111_1111_1111_1111_1111, voltage calculated
Vref
1.00000 -0.5000002384 -0.50000
However, reality, value affected drifting process, will equal 1.It will vary approx. same time, reference voltage Vref affected reference power dividing resistance, will equal 1.00000V. Therefore, gain variances from components have calibrated.
8.7. different output code different models
FS970x chip series three models with different resolution, 5,000 digits, 20,000 digits, 50,000 digits. digit output codes follows: 5,000 digits 50,000 digits models, when absolute value SUM1, SUM1<21:18> greater than 1010, then, SUM1<21:18>will saturate 1111. equivalent voltage SUM1<21:18>=1010 will approx. 0.625V. 20,000 model, when absolute value SUM1, SUM1<21:18> greater than 0101, then, SUM1<21:18>will saturate 1111. equivalent voltage SUM1<21:18>=1010 will approx. 0.3125V. 5,000 digit model, digital output SUM1<5:1> constant 00000.
8.8. Other Control setting
ENAD(ADG<7>) enabling signal ADC. turns when value turns when value=0. saves power consumption setting value
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FS970x Series Data Sheet
Digital Signal Process
Except digital filter, digital signal process FS970X includes frequency counter peak-hold sampling process.
9.1. Frequency counter
frequency counter FS970x composed time-based counter signal counter. physical value target calculated from these counters. physical values target have signal frequency duty cycle. determined DTON. performs frequency counter when setting "Lo" performs duty cycle measurement when setting "Hi". When performing frequency counter measurement, needs reference time pulse signal FTB, shown Graph frequency target obtained from following formula:
Formula
FINSIG
Whereas values signal counter time-based counter respectively. frequency reference signal, shown Chart FINSIG frequency target signal. When performing duty cycle measurement, relationship between duty cycle DTINSIG follow:
DTINSIG 100%
Formula
have noticed that value independent from reference time pulse frequency. 9.1.1. reading process frequency counter Both controls frequency measurement duty cycle measurement motion frequency counter through FQRST_. When first setting FQRST_ then resetting will trigger action frequency counter. will complete counting approx. seconds. will also advice microprocessor read. After reading KSG, value calculated from Formula Formula Then, repeat reset value next measurement, forth
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FS970x Series Data Sheet
However, whether processed interrupt polling after reset counter, interrupt status meaning counting completed. However, when using frequency counter FS970x chip, when entering counter measurement, after first reset, should read values KSG. doesn't need process values. Thereafter, starts reading process interrupt status bits.
9.2. Peak-hold sampling process
shown Chart reading output value fast meets requirement positive negative peak-hold pulse bandwidth measuring matter naro-second. peak-hold sampling logic FS970x accepts control PKHRST. uses input. composed positive-negative peak-hold comparison device positive-negative peak-hold register. When PKHRST_ equals positive peak-hold register (POSPK) negative peak-hold register (NEGPK) will reset most negative positive value respectively. When PKHRST digit comparison device will compare value SUM2 with value positive peak-hold register (POSPK) negative peak-hold register (NEGPK). When value SUM2 greater than value positive peak-hold register, value positive peak-hold register will updated, otherwise will remain same. When value SUM2 smaller than value negative peak-hold register, value negative peak-hold register will updated, otherwise will remain same. Therefore, after resetting peak-hold sampling logic, PKHRST_ equal interrupt status digit peak-hold sampling then, read values POSPK NEGPK registers. obtain values measuring positive peak-hold negative peak-hold values. Because value peak-hold sampling device derived from value SUM2, should Formula calculate equivalent voltage value operator.
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FS970x Series Data Sheet
Microprocessor interface
970x directly connect microprocessor CS_. WR_. RD_. ALE. AD3. AD2. AD1. AD0, IRQO pins. also control read write functions registers, handle interrupt.
10.1. Control register
control registers 8-bit register, input-output port microprocessor read write. control register will reset initial value when connecting RST_ chip. primary function control register provide microprocessor write control setting chip. Hence, controls action chip. also read value detection.
Block MISC Address Name RGD<7:0> SIN<7:0> SRF<7:0> SCP<7:0> AFT<7:0> ADG<7:0> SETADC MISC1<7:0> MISC2<7:0> INTRG<7:0> EXTD ENAD ENVDS ENBP ENCP_ SOSR<1:0> SCMPH<3:0> RCTEN CPVR ENVCS FSDIV CMP2 CYS<1:0> TBDIV CMP1 ENOSCO_ ACDIV ACEN RANGE<3:0> SINH<3:0> SRFH<1:0> BPFTR SCMPL<1:0> ENSCHMT CAPM ADG<5:0> TPS2<1:0> ENXTL_ CNTBP DTON BPACBF TPS1<1:0> FQRST_ ENGNDR_ PKHRST_ ENLBS MODE<3:0> SINL<2:0> SRFL<2:0> CMPEN2 CPN<1> CMPEN1 CPN<0>
INSTA<3:0>
INTEN<3:0>
Chart
corresponding address table control interrupt register chip.
There are, total, nine 00~08 addresses control line register; shown Chart functions each address briefly illustrated Chart Register RGD<7>0> Function Reference
Controls on/off status measurement mode decay described network function network Section
SIN<7:0>
Controls path pre-filter signal input amplifier Chart Chart Controls path pre-filter reference voltage
Chart Chart
SRF<5:0>
SRF<7:6>
Output option power supply
Chart
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SCP<7:0>
FS970x Series Data Sheet
Controls path enable control multiplexers Chart Chart front-end comparator enable control on/off status operation amplifier some Graph function networks When ENSCHMT Schmidt trigger function enable Section comparator gain setting input Performance setting Section Section Section Section Section
AFT<7:0>
AFT<3>
ADG<5:0> ADG<7:6>
SETADC<7:6> ENVDS ENVCS, on/off power control setting SETADC<5:4> CYS<1:0> elimination mode setting offset voltage SETADC<3:0> TPS1<1:0> TPS2<1:0> number digital filter MISC1<7>
CNTBP CMP1of ENBP MISC2<3> determine action Chart buzzer Setting clock generator controls operating mode Chart Chart capacity measurement Chart DTON FQRST_ counter mode frequency counter Section reset control PKHRST_ reset signal peak-hold sampling circuitry Output compactor voltage detector Section Section
MISC1<6:3>
MISC1<2:1>
MISC1<0> MISC2<6:4> MISC2<2>
When equal signal CMPH directly input from ACA, Section 7.5.1 without going through buffer ENGNDR_ ENLBS enable control basic offset voltage voltage detector.
Chart
MISC2<1:0>
brief illustration function each register FS970x.
read/write sequence each control register shown Graph Because data length bit, requires consecutive times each read write, first MSB, then bits each when next occurred. Thus, will start with again when starting next read/write sequence.
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AD<3:0>
Address, 00~08
FS970x Series Data Sheet
DATA<3:0>
DATA<7:4>
AD<3:0>
Address, 00~08
DATA<7:4>
DATA<3:0>
Next Address
CYCNTR
CYCNTR
READ CONTROL REGISTER CYCLE
WRITE CONTROL REGISTER CYCLE
Graph read/write sequence control register.
10.2. interrupt process
measurements read microprocessor interface high-resolution output ADC, resolution output ADC, positive-negative peak-hold value, output frequency counter.etc. registers, each value means "event". chip, thru IRQO pin, will send interrupt signal microprocessor request process. When microprocessor received interrupt signal negative-end trigger; means that some measuring registers 970x chip detected value. microprocessor will then read interrupt status register INTSTA checking where interrupt comes from. Chart shows corresponding event each INSTA. INTEN Chart controls whether measuring event interrupt will occur. INSTA Event INSTA<3> INSTA<2> INSTA<1> Low-resolution INTEN<1> Corresponding IRQO enable INSTA<0> High-resolution INTEN<0> Corresponding IRQO enable
Frequency counter peak-hold value output INTEN<3> Corresponding IRQO enable
Chart
INTEN Function
INTEN<2> Corresponding IRQO enable
Interrupt status registers.
When microprocessor reads register again, interrupt will reset waiting measurement generate interrupt again. interrupt status register INSTA<3:0> read-only register. interrupt enable register INTEN<3:0> read/write register. read/write sequences both registers same control register, shown Graph
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FS970x Series Data Sheet
flow-Chart interrupt process follows:
When there's value shown enable register, then IRQO equal keep When microprocessor receive this negative-end trigger, then read interrupt status register. After reading status register, IRQO will pulled back to1. Check IRQO pulled back not, means that didn't catch negative end; then, should read interrupt status more time. When reading instruction period interrupt register; negative-end interrupt might lost. Therefore, adding Step will improve this problem.
addition, whether value interrupt status register been updated independent from interrupt enable register. That say, interrupt enable register only affects IRQO output.
10.3. Measurement Registers
Address Register Function Length register
Times reading
KTB<23:0> KSG<23:0> POSPK<15:0> NEGPK<15:0> SUM2<15:0> SUM1<23:0>
Output time-based counter Output signal counter
up-most positive peak-hold register up-most negative peak-hold register
Output low-resolution Output high-resolution
Chart measurement value registers chip.
measurement registers their corresponding address FS970x listed Chart There addresses total. length each register varies. They output ports, only read microprocessor. reading clocks measurement register shown Graph When IRQC<x> negative-end, will clear corresponding INSTA<x>. number readings each value correct. Otherwise, read/write cycle counter CYCNTR will
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FS970x Series Data Sheet
cleared when "Hi". number readings each address varies with length each register, shown last column Chart When reading SUM1or SUM2, first reading period (when CYCNTR=1), pulse width must greater than sampling period ADC. other reading periods need only greater than example, when sampling frequency 83.3 kHz, then, first reading period SUM1 SUM2 must greater than Regarding frequency counter, what worth mentioning when reading value time-based counter, will clear interrupt INSTA<3>. corresponding interrupt INSTA<3> cleared. INSTA<2> will cleared whether reading registers up-most positive peak-hold value up-most negative peak-hold value.
AD<3:0>
Address, 0A~0F
DATA<N:N-3> DATA<N-4:N-7> DATA<3:0>
Only when reading signal counter,
CYCNTR
IRQC<x>
READ MEASURED REGISTER CYCLE
Graph Reading sequence diagram measuring registers.
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FS970x Series Data Sheet
Basic Measurement Application
11.1. DCmV
11.1.1.
BPFTR CHIP CHIP
DCmV 909K
ADIMUX
27nF 220pF EXCEPT CHIP SGND ADIMUX
COMMON
AGND
Graph Function network diagram
Address Register Value
SETADC
MISC1 MISC2
Chart register setup.
Signal flows SMV, through ADIMUX pre-filter, into ADC.
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11.1.2.
FS970x Series Data Sheet
CHIP
AGND
CHIP
ACDIV
ACBUF ACEN
CMPHMUX
ADIMUX BPFTR
DCmV
27nF CHIP SGND ADIMUX
COMMON
AGND
Graph Function network diagram
Address Register Value
SETADC
MISC1 MISC2
Chart register setup.
Signal flows from AMV, through 10-times amplified gain network ACBUF, goes through pre-filter before flowing into ADC.
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11.2. voltage
FS970x Series Data Sheet
ACBUF ACEN
AGND
ACDIV RFUSE+PTC TENM TENM<0>
ADIMUX BPFTR
CMPHMUX XOHM 100K XOHM 19~22 ADIMUX XOHM CHIP SGND ADIMUX 27nF
COMMON CHIP AGND CHIP
Graph Function network diagram voltage. Address Register 5V~1000V SETADC
MISC1 MISC2
Chart voltage register setup.
Whereas, value RGD<7:4> determined function, shown Chart Address Register RGD<7:0> 0.5V~5V 500V 1000V
Chart Voltage range setup
voltage signal will decay lower than 0.5V suitable multiple decay network. will through pre-filter, then into ADC. Only signal 0.5V, decayed 10-times, will amplify 10-times before flow into ADC.
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11.3. Voltage (ACV)
FS970x Series Data Sheet
AGND
10uF AGND
ACHO
ACLO
RCTN
CCOMPENSATION CPN<1> ACDIV AGND
RCTO
RCTP
ACDIVB
CPN<0> CDECOUPLE RFUSE+PTC BPFTR CMPMUX XOHM 100K XOHM 19~22 ADIMUX XOHM CHIP ADIMUX 27nF SGND SGND TENM ACEN TENM<0> ACBUF AGND
RCTOP RCTEN
CMP1
FREQ
CMPEN1
COMMON CHIP AGND CHIP
Graph
Function network diagram voltage. SETADC
Address Register 0.5V 5V~100V
MISC1 MISC2
Chart voltage register setup.
Whereas, value RGD<7:4> determined function, show Chart voltage signal 5V~1000V will decay lower than 0.5V suitable multiple decay network. will through buffer with gain value then into AC/DC converter true mean square converter. then goes through pre-filter, into ADC. Under 0.5V, setting ACDIV=1 will allow 10-times decay signal 10-times amplified buffer, reversing back within dynamic range 0.5V before feeding into AC/DC converter true mean square converter.
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11.4. Current (DCA)
FS970x Series Data Sheet
AGND
ACDIV
ACDIVB
ACBUF ACEN
mA+uA CMPMUX BPFTR
0.99
ADIMUX
27nF 0.01 COMMON SGND ADIMUX CHIP
AGND CHIP CHIP
Graph Function network diagram current.
Address Register 5000uA, 500mA, 500uA, 5mA,
SETADC
MISC1 MISC2
Chart current register setup.
shown Graph assuming transferring resistor approx. 100, transferring voltage will 0.5V under 5.0000 will then flow into through ACBUF buffer (ACDIV=AFT<5>=0). Under 50.000 when using transferring resistor 100, transferring voltage will high. using transferring voltage will 50mV, gain ACBUF will (ACDIV=AFT<5>=1). Amplify signal 10-times before feeding into ADC.
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11.5. Current (ACA)
FS970x Series Data Sheet
AGND
10uF AGND
ACHO
ACLO
RCTN
RCTO
RCTP
ACDIV ACDIVB
RCTOP ACBUF mA+uA AGND ACEN CMP1 FREQ RCTEN
BPFTR 0.99 27nF 0.01 COMMON SGND SGND ADIMUX CHIP ADIMUX CMPMUX
CMPEN1
AGND CHIP CHIP
Graph Function network diagram current.
Address Register 5000uA, 500mA, 500uA, 5mA,
SETADC
MISC1 MISC2
Chart current register setup.
shown Graph, measuring path current, output buffer, same current. After going through buffer, signal will flow through AC/DC converter true mean square converter convert signal into signal before flow into ADC.
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11.6. Resistor
COMMON
FS970x Series Data Sheet
SGND
DCmV+OHM+CAP +DT+HFE+PKH
AGND 909K EXCEPT XOHM<0> 100K 220pF XOHM 19~22 XOHM<2> OHM+CAP +HFE+CALR AGND TENM DCV+OHM +CAP+HFE+PKH TENM<0> XOHM<1> OSRC OSREN OSRC
FUSE VOLT+OHM+ DT+CAP
27nF
CPN<0> CPN<1> AGND
CHIP
CHIP
Graph
Function network diagram resistor. SETADC
Address Register Value
MISC1 MISC2
Chart Resistor register setup.
setup RGD<7:4>, SRF<7:0>, ADG<7:0>, MISC1<7:0> varies with different functions. below details. Address Register RGD<7:0> SRF<7:0> ADG<7:0> MISC1<7:0> 500K
Chart Resistor range setup.
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11.7. Capacitor
COMMON
FS970x Series Data Sheet
DCmV+OHM+CAP +DT+HFE+PKH
AGND 909K CMPH
CMPEN1 CMP1 CAPTG
CMPL
OSREN 100K FUSE VOLT+OHM+ DT+CAP DCV+OHM +CAP+HFE+PKH 18~22 XOHM XOHM<1> OSRC XOHM<2> OSRC
CHIP
CHIP
Graph Function network diagram capacitor.
Address Register Value
SETADC
MISC1 MISC2
Chart Capacitor register setup.
Address
Register RGD<7:0> AFT<7:0> MISC1<7:0>
500nF
50uF
500uF
Chart Capacitor range setup.
Measuring capacitor value FS9704B charge discharge resistor reference added XOHM make oscillation, then calculate oscillated cycle capacitor value.
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FS970x Series Data Sheet
3/4VDD 1/4VDD
Capacitor Measurement
calculate cycle, send square wave that from CAPTG frequency counter. When operating frequency measurement, necessary timer reference signal FTB. measuring frequency, gained through following formula. this formula, signal counter value time-base counter.
(Ksg Ktb)
revise calculated cycle.
(Ksg Ktb)
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11.8. Diode
FS970x Series Data Sheet
CHIP CHIP
DCmV+OHM+CAP DT+HFE+PKH
HUNK
DIODE
SGND
COMMON
AGND
Graph
Function network diode measurement. SETADC
Address Register Setup value
MISC1 MISC2
Chart Diode register setup.
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FS970x Series Data Sheet
Package Outline
LQFP64: plastic profile quad flat package; leads; body x1.4
index
(A3)
detail
scale
DIMENSIONS origlinal dimensions)
UNIT max. 1.60 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09
0.75 0.45
10.1
10.1
12.15 12.15 11.85 11.85
0.12 0.075
1.45 1.05
1.45 1.05
Note: 1.Plastic metal protrusions 0.25 maximum side included.
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FS970x Series Data Sheet
Attachment OP-AMP Specifications
(VDD TA=+25, unless otherwise indicated) Instrumentation Amplifier Gain Vref=0.5V, TA=25
PARAMETER TEST CONTITIONS MIN. TYP. MAX. UNITS
Input Offset Voltage without Rs<100 Input Offset Voltage with Input Offset Drift without Input Offset Drift with Input Referred Noise Input Bias Current Current Consumption Rs<100 -20<TA<+50 -20<TA<+50 Rs=100, 0.1Hz~1Hz
µVpp
These parameters guaranteed design tested only sampling while mass production. While voltage source with large output impedance measured instrument-ation amplifier having input bias current, additional input offset voltage will introduced. However, this offset voltage could cancelled mirrored offset cancellation technique.
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FS970x Series Data Sheet FS970x Series Data Sheet (V3.8) Dig

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