FS501 Manual FS501 Manual [P3.7] Embedded OperationalAmplifi

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FS501 Manual
FS501 Manual [P3.7]
Embedded OperationalAmplifier High Resolution Analog-to-Digital Converter
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FS501 Manual
INTRODUCTION FS501 CHIP CHARACTERISTICS BLOCK DIAGRAM FS501. ELECTRICAL CHARACTERISTICS
PACKAGE TERMINAL ASSIGNMENTS.6 PACKAGE TERMINAL ASSIGNMENT LQ44 TERMINAL DESCRIPTION MICROPROCESSOR INTERFACES CONTROL REGISTERS INTERRUPT PROCESS MEASURE REGISTERS VOLTAGE REGULATOR.14 BIAS CURRENT SOURCE GENERATOR POWER SAVING MODE SWITCHABLE POWER OUTPUT POWER DETECTOR. CLOCK GENERATOR CLOCK GENERATOR FUNCTION NETWORK.18 MEASURE MODE MULTIPLEXER PRE-FILTER OPERATION AMPLIFIER AMP) VOLTAGE SOURCE ANALOG DIGITAL CONVERTER (ADC).22 OPERATION DELTA-SIGMA MODULATOR GAIN STAGE SETTING DIGITAL FILTER READING CALCULATING DIGITAL-TO-ANALOG CONVERTER 8.4.1 Output SUM1 CONVERSION DIGITAL CODES EQUIVALENT VOLTAGE OTHER CONTROL SETTING APPLICATION INFORMATION APPLICATION CIRCUIT ELECTRONICS SCALE (USING INTERNAL APPLICATION CIRCUIT ELECTRONICS SCALE (USING EXTERNAL DIMENSION.29
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Introduction FS501 Chip
FS501 high resolution analog-to-digital converter (ADC) chip. core this chip 18-bit resolution ADC. Besides ADC, FS501 consists switching circuits, operational amplifier amp), digital filter, crystal oscillation circuits, digital control logic, microprocessor interface. Under working voltage, this chip consumes 1.2mA power. FS501 contains amps several programmable direct inputs. input signals reference voltages fully differential. This mechanism measure fully differential small signals. application includes electronic scale infrared thermometer. FS501 contains digital filters. 18-b/5Hz high resolution output, other 12-b/325Hz resolution output. Chip Package High Resolution Resolution Voltage Detector/ Bits/Hz Bits/Hz (Thermistor) Resistance Measuring 18/5
Table
FS501F
LQ44
12/325 FS501 Chip
Characteristics
Embed High resolution Five 18-bit high resolution outputs second 12-bit outputs second Embed amps Embed voltage regulator, input: outputs: Chip current less than 1.2mA With power saving mode 50/60 noise distortion Embed crystal oscillation circuits
Standard 4-bit parallel port interface, directly connected microprocessor ports With four programmable direct input channels
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Block Diagram FS501
TENM HUNK ADRF RCTP RCTN RCTO SGND AGND XTALI XTALO VDDA GNDR VCCR VCCS VDDS VSSD
Electrical Characteristics
(VDD TA=+25 unless otherwise indicated) PARAMETER Analog-to-Digital Converter Zero Input Reading Zero Reading Drift Linearity (Max. deviation from best straight line fit) VIN=0V, 500mV Scale Counts
500mV Scale
Counts Counts Counts
Input Common-Mode Rejection VCM= VIN=0V, 500mV Scale Ratio Input Common-Mode Voltage Range VIN=0V, 500mV Scale, Counts
Noise (p-p Value Exceeding VIN=0V, 500mV Scale Time) Rollover Error (Difference -VIN=+VIN=500.00mV reading equal positive negative inputs near Full Scale)
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Regulator Modulator Functional Network Oscillator
TEST CONDITIONS MIN. VIN=0V, <TA<+70
FS501 Manual
Battery Detector
VBAT
Digital Filter
Digital Interface Control Registors
RST_ IRQO
TYP.
MAX.
UNITS
VER.
PARAMETER Input Leakage Current Scale Factor Temperature Coefficient Current Consumption
Input Offset Voltage without Rs<100 Input Offset Voltage with Input Offset Drift without Input Offset Drift with Input Referred Noise Input Bias Current Current Consumption Regulator Analog Ground Source Capability Analog Ground Sink Capability VBAT Battery Detection Voltage Operating Current Sleep Current Parasitic Capacitance Digital Output High Digital Output Digital Input High Digital Input Temperature Range Operating Temperature Range Storage Temperature Range IOUT=-1mA IOUT=1mA VIN=0, 500mV Scale VO=-0.1V VO=0.1V Rs<100
<TA<+50
Rs=100 0.1Hz~1Hz
µVpp
These parameters guaranteed design tested only sampling while mass production. While voltage source with large output impedance measured instrumentation amplifier having input bias current, additional input offset voltage will introduced. However, this offset voltage could cancelled mirrored offset cancellation technique.
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<TA<+50
Instrumentation Amplifier Gain Vref=0.5V, TA=25
TEST CONDITIONS VIN=0V VIN=500.00mV, <TA<+70 MIN.
FS501 Manual
TYP. MAX. UNITS ppm/
FS501 Manual
Package Terminal Assignments
Package Terminal Assignment LQ44
AD<0> AD<1> AD<2> AD<3> IRQO XTALO
RST_ TENM HUNK SGND AGND VDDA
XTALI VSSD VBAT VCCS
FS501F/LQ44
VCCR VDDS GNDR RCTO
RCTN
ADRF
REFH
RCTP
CSFB
VSSA
http://www.fsc.com.tw
(0,0)
opening 90um Chip size 3.578mm 3.146mm
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Package
Dice size
3.578*3.146 Name XTALO IRQO AD<3> AD<2> AD<1> AD<0> RST_ TENM HUNK SGND AGND VDDA ADRF VSSA REFH CSFB RCTP RCTN X[mm] 2.675 2.340 2.120 1.900 1.679 1.459 1.255 1.051 0.847 0.643 0.496 0.349 0.209 0.209 0.209 0.209 0.209 0.209 0.209 0.209 0.209 0.209 0.209 0.449 0.597 0.750 1.213 1.366 1.521 1.674 Y[mm] 2.937 2.937 2.937 2.937 2.937 2.937 2.937 2.937 2.937 2.937 2.937 2.937 2.468 2.313 2.006 1.544 1.390 1.236 1.082 0.935 0.788 0.480 0.325 0.209 0.209 0.209 0.209 0.209 0.209 0.209 Name RCTO GNDR VDDS VDDS VCCR VCCS VBAT VSSD XTAL1 X[mm] 1.828 2.290 2.444 2.753 2.906 3.282 3.368 3.368 3.368 3.368 3.368 3.368 3.368 3.368 3.368 3.046 2.899 Y[mm] 0.209 0.209 0.209 0.209 0.209 0.209 0.961 1.110 1.272 1.503 1.674 1.845 2.016 2.761 2.952 2.937 2.937
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LQFP44 10*10
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FS501 Manual
Terminal Description
Attribute Name SGND AGND VDDA Signal Ground Power Supply Ground Analog Signal (+2.5 Function
Input Analog Signal
Reference Resistance Bottom Input (Thermistor) Resistance Measuring Input Reference Voltage Power Supply (0V) Analog Signal Reference Voltage Input Embedded Analog Power Source Current Source Feedback ACBUF Terminals Inputs RCTOP Output RCTOP Programmable Input Channel Programmable Input Channel Programmable Input Channel Programmable Input Channel Analog Ground Output Embedded Voltage Regulator (+2.5 Output Internal Switches (+5V) Input Voltage Regulator Output from Voltage Regulator
ADRF VSSA REFH
9-10 11-12
27-28 29-30
CSFB ACB, RCTP, RCTN RCTO GNDR
VDDS VCCR
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Power Supply Analog Signal
21-22
25-26 28-31
39-40
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VCCS VBAT OSCO 44-1 VSSD (0V) Digital Signal XTALI, XTALO Crystal Oscillator Inputs IRQO AD<3:0> 14-15 RST_ TENM, HUNK FTA, 16-17 Notations:
FS501 Manual
Output Internal Switches Power Supply (4~5V) Digital Signal Input Power Detector Crystal Oscillation Output. used microprocessor directly.
Interrupt Output Signal Measure Events Data Input/Output Microprocessor Interface Read Terminal Microprocessor (Active Oriented) Write Terminal Microprocessor (Active Oriented) Address Latch Enable Microprocessor. When high, AD<3:0> address bus. Chip Select Microprocessor Interface (Active Oriented) (+4V) Digital Signal Reset. reset internal registers zero. Terminal Filter Reference Resistance Terminals (Thermistor) Resistance Measuring Terminals Filter
stands Digital. stands Analog stands Power. stands Output. stands Input. example: means "Digital Input/Output"
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Microprocessor Interfaces
FS501 directly connected microprocessor pins CS_, WR_, RD_, ALE, AD<3>, AD<2>, AD<1>, AD<0>, RQO. access read/write control registers, handle interrupts, access measure registers.
Control Registers
Control registers control status internal components, such status multiplexer, digital filters, etc. them 8-bit registers, them input/output ports that read written microprocessor. When reset activated (RST_= control registers rest microprocessor control chip setting control registers, read values control registers check status chip.
Address Name
Table shows control signals addresses control registers. There addresses, 00~09. functions briefly described Table Registers MODE<3:0> RGD<5> SIN<7:0> SRF<5:0> Function Selection Thermistor Voltage Measure Selection Thermistor Measure Switches Input selection control signals filter. Refer Section Table Table Table
SCP<7:4> AFT<6:4> ADG<5:0> ADG<7:6>
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Path selection CMPH Enable controls amps Input gain setting setting
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Table Address Control Registers Interrupt Registers.
Reference voltage selection control signals Table Table filter Table Fig. Section Section
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SETADC<7:6> SETADC<5:4> SETADC<3:0>
MISC1<6,4:3> MISC2<7> MISC2<2>
MISC2<4>, MISC2<0> MISC2<1>
INTRG<4> INTRG<0>
read/write timing sequences control registers shown Fig. length data 8-bit wide, therefore, needs read write consecutively twice (MSB bits first then bits). Otherwise, activation next will reset CYCNTR (cycle counter) will start from bits next instruction.
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ENVDS ENVCS, programmable power supply setting. CYS<1:0>, offset voltage elimination mode setting Setting clock generator ACBUF switching mode Setting Power Detector Interrupt status register Enable control IRQO
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Section Section
TPS2<1:0> TPS1<1:0>, TPS2<1:0> TPS1<1:0> Section high speed high resolution setting digital filter. Table Section
set, CMPH signal will bypass ACBUF amplifier directly Fig. output through Section
ENGNDR_, enable control output internal power supply Section ground analog parts. Section Section
Table Brief Description Function FS501 Registers
Fig. Read/Write Timing Diagram Control Registers
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Interrupt Process
INSTA Event
FS501 Manual
data converted read interface microprocessor, that event occurred, this chip activates interrupt signal through IRQO microprocessor request accessing. When microprocessor receives negative edge-triggered interrupt signal, measure register FS501 measured data. interrupt measured event triggered signal INTEN shown Table
INSTA<1>
INSTA<0>
High speed resolution High resolution speed conversion conversion INTEN<1> Corresponding IRQO enable INTEN<0> Corresponding IRQO enable
INTEN Function
Table Interrupt Status Register
When microprocessor reading data from measure register, corresponding interrupt cleared wait next measured data. Interrupt status register, INSTA<0>, read-only register. Whereas interrupt enable register, INTEN<0>, read/write register. read/write timing sequences these registers same that control registers shown Fig. interrupt procedures follows: When data appear enabled measure register, IRQO cleared kept microprocessor activated negative edge IRQO then reads contents interrupt status register. After read interrupt status register, IRQO
Check IRQO. negative edge signal captured, microprocessor read interrupt status register again. When reading interrupt register, negative edge interrupt signal lost. Step improve this problem. value interrupt status register whether refreshed independent interrupt enable register. interrupt enable register only affects IRQO output.
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Measure Registers
Name
Address
measure register corresponding address FS501 shown Table output reading microprocessor. read timing sequence measure register shown Fig. negative edge IRQC will clear INSTA<0>. read count each read should correct. Otherwise, high will clear CYCNTR (read/write cycle counter) read count measure register shown last column Table When read measure register, should longer than sampling cycle first read cycle. other read cycles, least 2us. example, sampling rate 83.3kHz; then first read cycle reading measure register should greater than 12us.
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Content Output resolution high speed Output speed high resolution
Table Measure Register
FS501 Manual
Register Length Read Times
SUM1<15:0>
SUM1<23:0>
Fig. Read Timing Sequence Measure Register
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Voltage Regulator
VBAT
VCCR
S81250
REFH
block diagram FS501 voltage regulator shown Fig. circuit, need cost voltage regulator, S81250, regulate battery voltage (more than 6.8V) 6.4V VDD. power supply used for: analog circuit power supply, reference voltage voltage regulator. Fig. voltages REFH used reference voltages generate VCCR, GNDR, FS501. then VCCR GNDR will regulated 3.2V respectively. Users select power supply source FS501 themselves, either generated internally supplied externally. power sources analog circuits FS501 supported through terminals VDDA, AGND, VSSA. Therefore, directly connect voltage regulator outputs VCCR, GNDR, terminals VCC, AGND, VSSA respectively. user find stable power source externally, power sources applied terminals VCC, AGND, VSSA directly instead internal power sources VCCR GNDR. Most power consumption analog circuit static current. FS501 current analog part designed less than 1mA, current digital part less than 0.5mA
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309K Battery 800K ENGNDR_
FS501 Manual
GNDR
AGND
FS501 Regulator
Fig. Block Diagram FS501 Voltage Regulator
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Bias Current Source Generator
bias current source generator shown Fig. generates bias current analog circuits FS501. embedded works, CSFB will pulled AGND feedback; there 1.2V resistor 412K, bias current obtained. value 412K-resistor reduced, working current chip will increased, some specs improved.
Power Saving Mode
FS501 except VCCR generator, user control registers turn part circuits reduce power consumption. control signals related power saving shown Table turn devices (circuits) keep VCCR active, shown Table total current FS501 chip will less than 10uA Register Control Name Power-Saving Setting Power Consumption Circuit Switching Power Output OSCO Output Crystal Oscillator GNDR Voltage Regulator
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CSFB AGND ENGNDR_
FS501 Manual
Current Bias
FS501 Current Bias
Fig. FS501 Bias Current Source Generator
AFT<6> AFT<4> ADG<7> SETADC<7:6> MISC1<4> MISC1<3> MISC2<1>
RCTEN ACEN ENAD ENVDS, ENVCS ENOSCO_ ENXTL_ ENGNDR_
Table Setting Power Saving Mode
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Switchable Power Output
VDD/VCC VDDS/ VCCS
Terminals VDDS VCCS switchable power outputs respectively, circuit diagram shown Fig. VDD/VCC PMOS switch, VDDS/VCCS output. PMOS switch controlled ENVDS/ENVCS control signal. Signals will turn turn PMOS switch respectively.
Power Detector
Power detector shown Fig. dividing voltage VBAT into input power detector. output voltage, LBO, power detector detect whether dividing voltage VBAT less than AGND. less than AGND, high user replace battery. Before reading LBO, have ENLBS (high), pull ENLBS after approximately 0.1ms; then read LBO. multiplexer, voltage selected ADC, Equation voltage found. Equation
power saving mode, ENGDR_ (MISC<1>) high turn GNDR save power consumption.
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ENVDS/ ENVCS
FS501 Manual
Fig. Switchable Power Output
ENLBS
Fig. Power Detector
VBAT VLBS
Clock Generator
Clock Generator
block diagram clock generator shown Fig. connect 4MHz crystal oscillator clock generator generate 4MHz clock frequency. frequency divider used divide clock signal generate signal uses this signal data conversion. controlled ENXTAL_ FSDIV; truth table shown Table ENXTAL_ FSDIV 166.67 83.33
When ENOSCO_=0, output fixed 2.000 square wave. When ENOSCO_=1, output save power consumption.
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XTALI FSDIV XTALO
FS501 Manual
ENXTL_
DIVIDER
ENOSCO_ OSCO
OSCO
1/FS
Fig. Clock Generator
Table Truth Table Generation
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Function Network
RCTN
RCTO
RCTP
SGND ADRF
SGND ACDIV ADRF ACDIV BPACBF
SINH<3:0> SGND ADRF ACBO CMPH INHMUX SRFH<1:0> ADRF VRHMUX FTIN
ACBUF
RCTOP RCTE
ACEN
ACBO
function network shown Fig. There multiplexers, amps, comparators. Control registers multiplexers, INHMUX, INLMUX, VRHMUX, VRLMUX, SCMPHMUX, select working channels. amps, ACBUF RCTOP, used amplifier input voltage buffer. OSRC embedded voltage source resistance measuring. comparator compare input signal with AGND, output read through register.
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BPFTR SINL<2:0> SGND INLMUX SRFL<2:0> AGND SCMPH<3:0> ADRF CMPH CMPHMUX hunk<0> (VDD) HUNK hunk<1> SOSR1:0 AGND CMP1 CMPEN1 VRLMUX hunk<2>
FS501 Manual
CMP1
OSRO OSRC OSRC
Vrefh
tenm<0> tenm<1>
OSRMUX
TENM
tenm<1>
Fig. Function Network FS501
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Measure Mode
FS501 voltage measuring resistance measuring modes, modes controlled register MODE3:0. When MODE=0, voltage measuring mode. measured voltage either directly from INHMUX ADC, through ACBUF amplifier then ADC.
When MODE=1, resistance measuring mode. circuit shown Fig. Suppose that reference resistance Rref, measured resistance Rth. measuring equation follows. Equation
Where Dout output, thereafter resistance measured. control setting resistance measuring circuit shown Table Range Mode HUNK TENM MODE3:0 1001 1001 HUNK hunk2:0 tenm1:0
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Fig. Resistance Measuring Circuit
FS501 Manual
Rref
VINH VINL Dout VVRH VVRL
Table Setup Table Resistance Measuring Circuit
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Multiplexer Pre-filter
Multiplexers INHMUX, INLMUX, VRHMUX, VRLMUX select inputs FTIN, INL, VRH, ADC. Where FTIN outputs. These signals will through pre-filter then connected fully differential inputs, INL, ADC. They also bypass filter control BPFTR FTR, connected directly. control registers control selections. control registers selections shown Tables
Multiplexer CMPH (CMPHMUX) select signals ACBUF. control registers selections shown Table
Name SCMPH 0000 ADRF 0011 0101 SGND 1100 AGND 1101 1110 1111
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Name SINH 0000 SGND 0011 ADRF 0111 ACBO 1000 CMPH 1001 1011
FS501 Manual
1100
Table Setting Multiplexer
Name SINL
SGND
Table Setting Multiplexer
Name SRFH ADRF
Table Setting Multiplexer
Name SRFL AGND
Table Setting Multiplexer
Table Setting CMPH Multiplexer
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Operation Amplifier Amp)
ACBUF, control switch ACDIV external resistors form gain loop. Operation ACBUF controlled register ACEN. When ACEN=0, turned output high impedance. gain ACBUF control register ACDIV. When ACDIV=0, gain When ACDIV=1, gain determined external resistance.
RCTOP enabled control register RCTEN. When RCTEN=0, turned save power.
Voltage Source
supplied voltages voltage source shown Table they directly into attenuating network. output voltage source controlled SOSR1:0. value SOSR1:0 directly control register. When output voltage source VDD, switch resistor loop will affect voltage chip driving terminator. Therefore, load affects effective load voltage. Because high gain negative feedback, outputs other than will affected switch resistor. effect load circuit neglected, maximum supplied current around ±1.2mA. INPUT MODE3:0 1001 1001 1001 1001 SOSR1:0 OUTPUT OSRO high impedance Vrfh
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ACBUF RCTOP
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Table Control Values Voltage Source
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Analog Digital Converter (ADC)
Operation Delta-Sigma Modulator
This high resolution designed technology delta-sigma modulator. continuous analog signals sampled very high sampling rate that much higher than bandwidth input signal. delta-sigma modulator converts input signal series 1-bit codes. These 1-bit codes then digital filter filter high frequency quantization noise find high resolution digital outputs. used high resolution digital multimeters. This kind quantizes analog part, therefore, very good linearity. Because fully differential configuration, common mode rejection ratio (CMRR) very high reduce common mode signals effectively.
ANALO INTEGRATO
symbolic diagram delta-sigma shown Fig. consists analog subtractor, integrator, comparator, 1-bit digital-to-analog converter (DAC), low-pass digital filter. analog signals continuously sampled subtracted expected voltage. difference signals into integrator, then signal compared with reference voltage find digital output. This digital output converted 1-bit become analog signal (+Vref -Vref) then negatively back into integrator. infinitive gain integrator, change input signal much slower than sampling speed, average voltage obtained delta-sigma modulator will very close input signal. some resolution they treated same, therefore, 1-bit output data from comparator equivalent Vref analog signal values. digital filter then decimates 1-bit data very high resolution digital code.
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COMPARATOR
Vref, -Vref, -Vref, Vref, Vref, Vref,.
FS501 Manual
DIGITAL PASS DECIMATION FILTER
Dout
Fig. Symbolic Diagram Delta-Sigma Analog-to-Digital Converter
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Gain Stage Setting
There four different gain paths input FS501 ADC, they controlled control register ADG<3:0>; block diagram shown Fig. different gain paths control input reference voltage, they controlled control register ADG<5:4>. gains shown here accurate. accurate gains found careful calibration. proper selection gain paths, this applied optimum dynamic range measuring applications. Table shows values ADG<5:0> three frequently used applications. First Scale Second Scale 11_0111 Third Scale
Table FS501 Typical Gain Setting
transfer function each scale follows,
gains reference voltages input voltages shown Table approximate values. accurate gains reference voltages input voltages found careful calibration.
Digital Filter
Fig. 1-bit output comparator should digital pass filter decimation find high resolution multiple-bit digital output. transfer function FS501 digital filter
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Equation
Input Voltage Gain GSIGi
SIGi REFi
ADG<0> ADG<1>
FS501 Manual
0.25
ADG<2>
signal input
ADG<4>
VREF
0.25
ADG<5>
reference input
ADG<3>
Fig. Diagram FS501Gain Stage Setting
ADG<5:0> Reference Voltage Gain GREFi
01_0011
11_1000
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FS501 Manual
Where digital filter. Suppose sampling rate 166KHz, digital filter 16600. find frequency response diagram digital filter shown Fig. first zero Equation
-100
-150
-200
Fig. Frequency Response Diagram FS501 Digital Filter zero points fall multiples 10Hz. digital filter will filter signals near zero points. From Fig. find that noises 50Hz 60Hz suppressed very well. sampling rate 83KHz filter 16600, first zero-frequency 5Hz. There programmable digital filters FS970x, they COMB1 COMB2; outputs SUM1 SUM2 respectively. COMB1 higher than that COMB2; therefore COMB1 used high resolution measuring, COMB2 used resolution high speed measuring. TAP's COMB1 COMB2 programmable, TPS1 TPS2 respectively; they shown Table first zero-frequency computed taking 83.3 sampling frequency applies Equation TPS1=TPS2=11, resolutions high speed speed 18-bit 12-bit respectively. resolutions other conditions according actual measuring. COMB1 TPS1
16384
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TPSX<1:0>
First Zero Frequency
First Zero Frequency
Equation
COMB2 TPS2
VER.
FS501 Manual
8192 4096 2048 1300 2600
Table Setting Comb Digital Filter First Zero Frequency [FS=83.3 kHz]
Reading Calculating Digital-to-Analog Converter
manufacture process drift, there offset voltage FS501 such that offset value existed output. order eliminate offset value, FS501 provides three operation modes, which <1:0> control register SETADC. SUM1 output calculation different different operation modes, they described following subsection. 8.4.1 Output SUM1 CYS<1:0>=00, inputs short circuited, find negative offset voltage from SUM1. CYS<1:0>=11, described Equation find equivalent voltage input signal from SUM1. CYS<1:0>=01, SUM1 output value ideal ADC. transfer function Equation This mode suitable high resolution measurement. When CYS<1:0>01, output rate SUM1 first zero frequency, described Equation When CYS<1:0> =01, output rate equals
COMB1
Conversion Digital Codes Equivalent Voltage
output FS501 SUM1<23:0>, which 24-bit complement number. SUM1<23> sign bit; represents positive number, represents negative number. decimal point lies between SUM1<22> SUM1<21>. equivalent floating point number
SUM1 00.10 1000 0000 0000 0000 0000
Equation
0.125 0.625
equivalent floating point number
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FS501 Manual
SUM1 11.01 1111 1111 1111 1111 1111 -(00.10 0000 0000 0000 0000 0001) -0.5000002384
Equation
From Equation gain equals reference voltage Vref =1.00000V, value SUM1, 0010_1000_0000_0000_0000_0000, used calculate measured voltage
Vref
1.00000 0.625 0.62500
measured voltage calculated:
Vref
1.00000 -0.5000002384 -0.50000
However, manufacture process drift exactly equal there will around offset. Similarly reference voltage source resistors affect reference voltage make exact 1.00000V. Therefore, have calibrate ADC.
Other Control Setting
ENAD(ADG<7>) enable control signal ADC. enable ADC; turn save power. CPVR(ADG<6>) enhancement mode resistance measuring. improve linearity when measuring resistance.
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Application Information
Application Circuit Electronics Scale (Using Internal
AGND AGND VDDS VDDS
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Micro-Processor
4.00MHz 500K 10nF 27nF 27nF Thermistor 250K SGND SGND AGND VDDA RCTO VCCS HUNK TENM VSSD VBAT RST_ ADRF VSSA REFH
FS501 Manual
AGND
10uF
10uF
10uF
10uF
FS501F/LQ44
CSFB
AD<0>
AD<1> RCTP
AD<2> RCTN
AD<3>
IRQO
XTALO
XTALI
AGND
VCCS
S-81250
VOUT
VCCR VDDS GNDR
AGND
VDDS AGND
2.25K VDDS 2.25K
590K 825K
27/30
TD0112-2406
VER.
FS501 Manual
Application Circuit Electronics Scale (Using External
Micro-Processor
4.00MHz AGND
10uF
10uF
10uF
10uF
500K 10nF 27nF 27nF Thermistor 250K AGND AGND VDDS VDDS
RST_
TENM HUNK
SGND AGND VDDA RCTO
ADRF
VSSA
REFH
FS501F/LQ44
CSFB
AD<0>
AD<1> RCTP
AD<2> RCTN
AD<3>
IRQO
XTALO
XTALI VSSD VBAT VCCS
VDDS AGND VCCS S-81250
VOUT
AGND
VCCR VDDS GNDR
AGND
Fortune Semiconductor +886-2-2809-4742 http://www.fsc.com.tw FAX: +886-2-2809-4874
OP07/177
590K 825K
SGND 2.25K VDDS 2.25K
28/30
TD0112-2406
VER.
Dimension
Fortune Semiconductor +886-2-2809-4742 http://www.fsc.com.tw FAX: +886-2-2809-4874
29/30
FS501 Manual
TD0112-2406
VER.
FS501 Manual
Fortune Semiconductor +886-2-2809-4742 http://www.fsc.com.tw FAX: +886-2-2809-4874
30/30
TD0112-2406
VER.

FS501 Manual FS501 Manual [P3.7] Embedded OperationalAmplifi

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