CellBusBus Switch TXC-05802 DATA SHEET FEATURES UTOPIA 16-Bit (Ao
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CellBusBus Switch TXC-05802 DATA SHEET FEATURES
UTOPIA 16-Bit (Aor PHY) Layer cell interfaces Inlet-side address translation routing header insertion, using external SRAM Programmable OAM-cell RM-cell routing CellBus access request, grant reception transmission CellBus cell reception address recognition Outlet cell queuing: various modes Ability insert field real time Ability insert FECN indication, under programmable conditions Ability send receive cells control purposes over same CellBus Cell insertion extraction microprocessor port Master arbiter frame pulse generator included each CUBIT-Pro, with enabling Internal transceivers CellBus connection Interface port translation table SRAM Microprocessor control port, selectable Intel Motorola interface +3.3 power supplies 208-pin plastic quad flat package
CUBIT-Prois single-chip solution implementing cost effective Aaccess systems. based CellBusBus Architecture (CellBus). Such systems constructed from number CUBIT-Pro devices, interconnected 37-line common bus, CellBus bus. When operating clock rate, CellBus system handle Gbit/s Acell bandwidth. CUBIT-Pro supports unicast multicast transfers, necessary functions implementing switch: cell address translation, cell routing, outlet cell queuing.
APPLICATIONS
xDSL Access Multiplexer Remote Access Equipment Cable Modem Access Multiplexer ALAN Amultiplexer/concentrator Small-stand-alone Aswitch Add-Drop Ring Switch Edge switching equipment
Translation Address Cell Inlet Data Other Data Other
Data
Control
CUBIT-Pro
Cell Outlet
CellBus Switch
CellBus Port (32-bit data) Other CellBus bus-related signals
TXC-05802
Clock, controls, test, etc.
Address
Data
Controls clock input
Document Number: TXC-05802-MB September 1998
U.S. Patent 5,568,060 Microprocessor Port U.S. and/or foreign patents issued pending Copyright 1998 TranSwitch Corporation CUBIT-Pro SARA-Lite trademarks TranSwitch Corporation TranSwitch, TXC, CellBus, CUBIT, SALI-25C SARA registered trademarks TranSwitch Corporation
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
CUBIT-Pro TXC-05802 TABLE CONTENTS
SECTION PAGE List Figures Block Diagram Operation 6-40 Introduction CellBus Architecture CellBus Operation CellBus Cell Routing CellBus Status Signals Monitoring CUBIT-Pro Cell Inlet Outlet Ports 8-Bit UTOPIA Mode Aand Layer Emulation ALI-25 Mode Back-to-Back Mode Byte Ordering UTOPIA, ALI-25 Back-to-Back Modes 16-Bit Cell Interface Mode Aand Layer Emulation Word Ordering 16-Bit Cell Interface Mode Traffic Management Functions Dynamic Generic Flow Control (GFC) Field Insertion Forward Explicit Congestion Notification (FECN) Congestion Indication from CellBus Cell Inlet Paralleling Cell Inlet/Outlet Ports Redundancy Inlet-Side Translation Introduction Translation Connections Translation Control Translation Organization Translation Procedure Translation Record Formats Multicast Number Memory CellBus Interface Operation with Internal Transceivers Clock Source Arbiter Selection Outlet-Side Queue Management Single Queue Operation Split-Queue Operation Microprocessor Interface General Description Intel Mode Motorola Mode Interrupts Control Queue Send Receive Loopback Cell Send, Receive Relay Memory Reset States Diagram Descriptions Absolute Maximum Ratings Environmental Limitations Thermal Characteristics Power Requirements Input, Output Parameters Timing Characteristics Memory
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Memory Descriptions Package Information Ordering Information Related Products Standards Documentation Sources List Data Sheet Changes Documentation Update Registration Form
Please note that TranSwitch provides documentation products. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure CUBIT-Pro TXC-05802 Block Diagram CellBus Structure CellBus Frame Format CellBus 16/32-User Modes Frame Formats CellBus Routing Header Formats ALayer Emulation 8-Bit UTOPIA Mode Signal Connections Operating Mode Selection Layer Emulation 8-Bit UTOPIA Mode Signal Connections Operating Mode Selection ALI-25 Mode Signal Connections Operating Mode Selection Back-to-Back Mode Signal Connections Operating Mode Selection Byte Ordering Cell Inlet Outlet UTOPIA, ALI-25 Back-to-Back Modes ALayer Emulation 16-Bit Mode Signal Connections Operating Mode Selection Layer Emulation 16-Bit Mode Signal Connections Operating Mode Selection Word Ordering Cell Inlet Outlet 16-Bit Mode Insertion Outlet Queue (GFCENA Example Congestion Indication Single-Queue Mode (QM=0) Example Congestion Indication Split-Queue Mode (QM=1) Translation Connections Translation Organization Page Organization (Bit OAMRMEN=1) Translation Record Formats Translation Record Formats RM-VCC Cell Routing (Bit OAMRMEN=1) RM-VPC Cell Routing (Bit OAMRMEN=1) OAM/RM-Cells Translation Record Formats Multicast Number Memory External Circuit Requirements Transceivers Microprocessor Port Interface Connections CUBIT-Pro Status Register Address CUBIT-Pro Status Register Address
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Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Transmit Receive Control Cell Formats Loading Loopback Registers CUBIT-Pro TXC-05802 Diagram Translation Timing Read from Translation Timing Write Timing UTOPIA (ALayer Emulation) Cell Inlet Interface Timing UTOPIA (PHY Layer Emulation) Cell Inlet Interface Timing UTOPIA (ALayer Emulation) Cell Outlet Interface Timing UTOPIA (PHY Layer Emulation) Cell Outlet Interface Timing 16-Bit (ALayer Emulation) Cell Inlet Interface Timing 16-Bit (PHY Layer Emulation) Cell Inlet Interface Timing 16-Bit (ALayer Emulation) Cell Outlet Interface Timing 16-Bit (PHY Layer Emulation) Cell Outlet Interface Timing ALI-25 Cell Receive Interface Timing ALI-25 Cell Transmit Interface Timing Back-to-Back Cell Receive Interface Timing Back-to-Back Cell Transmit Interface Field Insertion Timing CellBus Timing CellBus Frame Position, 16-User 32-User Applications Intel Microprocessor Read Cycle Timing Intel Microprocessor Write Cycle Timing Motorola Microprocessor Read Cycle Timing Motorola Microprocessor Write Cycle Timing Microprocessor Interrupt Timing CUBIT-Pro TXC-05802 208-Pin Plastic Quad Flat Package CUBIT-Pro TXC-05802 Related Product Applications AAccess Switching
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CUBIT-Pro TXC-05802 BLOCK DIAGRAM
PHYEN Reset External Translation Port Test Address TRA(17-0) Data TRD(7-0) Translation Control TROE Inlet Queue TRWE Data Cell Queue cells Control Queue cell Loopback Queue cell CONGOUT
CID(7-0)/ RData(7-0) CICLAV/ RdVal CICLK/ RBClk CIENB/ RLoad CIF1/ RFlush CIF2/ RFlshD CIF3 CIF4/ EInt CISOC/ RdPrty
CBDISABLE VREF
CellBus Port
Cell Inlet Port
CBD(31-0) CBRC CBWC CBACK CBCONG
Outlet Queue Loopback Queue cell Synchronization FIFO Data Cell Queue cells Control Queue cells Cell Address Screen
CellBus Interface Logic
COD(7-0)/ TData(7-0) COCLAV/ TdVal COCLK/ TBClk COENB/ TLoad COSOC/ TDPrty GFC(3-0)
cells
Cell Outlet Port
Microprocessor Interface
Arbiter Frame Pulse Generator
MOTO
FRCABRCNG
Address Data INT/ RDY/ PCLK LCLOCK A(7-0) D(7-0) DTACK RD/WR
ENARB Other Controls
Figure CUBIT-Pro TXC-05802 Block Diagram block diagram CUBIT-Pro device shown Figure Further information device operation interfaces external circuits provided below following Operation section. cell inlet side CUBIT-Pro circuitry associated with accepting cells from line passing them CellBus with appropriate header. Cell Inlet Port block pin-selectable compliant with either AForum UTOPIA (Universal Test Operations Physical Interface ATM) interface, TranSwitch 16-Bit interface, TranSwitch ALI-25 device interface. Incoming cells carry CellBus Routing Header translated outgoing VPI/VCI address, translation function having been performed externally, this address translation routing header insertion done CUBIT-Pro Translation Control block. Translation routing header tables support this function contained external static 256k bits). They support and/or VPI/VCI address translation. incoming cells then pass through FIFO queue Inlet Queue block CellBus Port CellBus Interface Logic block. When there cell this 4-cell data cell queue, CUBIT-Pro makes access request, waits grant from Arbiter Frame Pulse Generator block CUBIT-Pro device attached that been enabled perform these functions. When access grant received, CUBIT-Pro sends cell bus, standard CellBus format. cell then received connected CUBIT-Pro CUBIT-Pros. addition these incoming data cells, CUBIT-Pro also send Control cells from local microprocessor Microprocessor Interface block. Special cells Loopback type received from also returned bus, re-directed back CUBIT- which launched original Loopback cell. Both Control cells Loopback cells have 1-cell inlet queues. -5TXC-05802-MB September 1998
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cell outlet side, cells proper unicast address, broadcast address selected multicast address, received from CellBus Interface Logic block, recognized Cell Address Screen block routed into FIFO structure Outlet Queue block. unicast address unique device, device straps. Each CUBIT- programmed accept cells associated with multicast sessions. From zero full multicast sessions accepted independently each CUBIT-Pro bus. Data cells from into 123-cell outlet data cell queue structure. Control cells Loopback cells arriving from routed 4-cell outlet control queue, 1-cell outlet loopback queue, respectively. outlet data cell FIFO structure treated single 123-cell queue, subdivided into four individual queues traffic different service types. four-queue split typically into highspeed control data cells, cells, cells, cells, decreasing order outlet service priority. This allows delay minimization critical service types, more efficient traffic management. cell outlet, provisions made insertion outgoing Generic Flow Control (GFC) field Explicit Forward Congestion Indication (EFCI) bit.
OPERATION
INTRODUCTION CellBus ARCHITECTURE CellBus Operation CUBIT-Pro versatile CMOS VLSI device implementing Aswitching functions. Various Acell switching multiplexing structures formed interconnection number CUBIT- devices over 37-line parallel with data bits, CellBus bus. Since interconnect structure bus, communications between devices possible. Each cell placed onto CellBus CUBIT-Pro device routed either single CUBIT-Pro (unicast addressing), multiple CUBIT-Pro devices (multicast broadcast addressing). Depending upon needs application, CUBIT- devices interconnected CellBus bus. With maximum frequency more than MHz, bandwidth CellBus exceeds Gbit/s. Enabled CUBIT-Pro's Arbiter Frame Pulse Generator
Data (32) Clock Frame Acknowledge Congestion Indicator
CUBIT-Pro
CUBIT-Pro
CUBIT-Pro
Figure CellBus Structure CellBus bus, shown Figure shared bus, implemented either single circuit card, backplane configuration among multiple circuit cards. Since multiple CUBIT-Pros share same bus, access contention must resolved. This access contention resolved central arbitration function. CUBIT-Pros will request access, central Arbiter will grant access back, response. circuitry this Arbiter included inside CUBIT-Pro device. CUBIT-Pro system selected perform arbitration function setting ENARB low. -6TXC-05802-MB September 1998
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Cycle Number Request Cell Body cycles) Grant
CellBus Routing Header
Tandem Routing Header (Optional)
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte BIP-8
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Unused
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Granted Terminal Number
Figure CellBus Frame Format CellBus framed format clock cycles long bits wide, which illustrated Figure first cycle each frame Request cycle (Cycle during which those CUBIT-Pros which have cell send each make access request asserting assigned bits bus. CBF, CBACK CBCONG signals asserted during Request cycle. device address assigned each CUBIT-Pro device straps (UA(4-0) pins 2-6) uniquely specifies which bits assert during Request cycle time. example, UA(4-0) HHHHH selects bits asserting assigned bits, other, both, access requests three different priorities made (controlled bits memory address 0AH). central Arbiter accepts these access requests, executes arbitration algorithm (highest priority served first, round-robin within each priority), issues access grant during final cycle frame, Grant cycle (Cycle 15). Each grant issued arbiter CUBIT-Pro send cell bus. Whichever CUBIT-Pro issued grant during Grant cycle will transmit cell during Cell Body clock cycles next frame, will also drive 8-bit cell parity check during Grant cycle that frame. Each cell sent unicast, multicast, broadcast type. CUBIT-Pros will accept single-address cells routed address defined their address straps, broadcast cells, selected multicast cells. Thus, cells sent from CUBIT-Pro CUBIT-Pro multiple CUBIT-Pros. CUBIT-Pro operated either 16-user 32-user mode, selectable pin, shown Figure 16-user mode CellBus frame identical Figure However, 32-user mode frame duplicated, that even frame provided. distinction between frames given location frame pulse. cycles both frames same, except meaning Request cycle. Request cycle even frame coincides with frame pulse, whereas frame pulse present. Furthermore, even frame CUBIT-Pros 0-15 (lower users) request access frame CUBIT-Pros 16-31 (upper users) request access bus. full bandwidth available shared among users either 32-user mode. -7TXC-05802-MB September 1998
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16-User Mode Framing Pulse Request Users 1-16 Framing Pulse
32-User Mode Request Users 1-16 Even
Cell body Grant Request
Cell body Grant Request Users 17-32
Users 1-16
Cell body
Cell body
Grant Request Users 1-16
Grant Request Users 1-16
Figure CellBus 16/32-User Modes Frame Formats detect CellBus errors, BIP-8 (Bit Interleave Parity byte) calculated over 54-byte data field that extends from first Tandem Routing Header byte through final payload data byte, Byte BIP-8 generated transmitting CUBIT-Pro using following algorithm. first byte Tandem Routing Header exclusive-or gated with all-ones byte, creating starting seed value. This seed value then exclusive-or gated with second byte Tandem Routing Header. result then exclusive-or gated with next byte cell. This process repeated with every successive byte cell, through Byte payload, final result transmitted BIP-8 byte cycle receiving CUBIT-Pro performs same process compares generated BIP-8 with received BIP-8. errors detected receiving CUBIT-Pro pulls CBACK low, acknowledging receipt cell. CellBus Routing Header CRC-4 field included BIP-8 calculation. cell with BIP-8 CRC-4 error discarded. only signals required operate which sourced CUBIT-Pro device transfer clocks: write clock (CBWC) read clock (CBRC). These clock signals same frequency, slightly phase-offset allow reliable operation. framing pulse used define frame cycle sent CUBIT-Pros, arbitration function also performed same CUBIT-Pro. Each CUBIT-Pro contains circuitry both Arbiter Frame Pulse Generator. Only CUBIT-Pro will have this circuitry enabled, setting control ENARB. CellBus Cell Routing CellBus architecture allows several types cell routing from inlet port outlet ports CUBIT-Pros CellBus bus: Point-to-Point Routing: Unicast Single Address cell routing cell coming into inlet port transferred single outlet port. CUBIT-Pro address cell itself, effectively implementing both inlet outlet ports. Point-to-Multipoint (Broadcast): cell coming into inlet port routed outlet ports CUBIT-Pros CellBus bus. Point-to-Multipoint (Multicast): multicast routing cell arriving inlet port sent subset outlet ports that belong specific multicast session means selection receiving CUBIT-Pros.
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each routing methods cells sent different output queues according whether cell used data cell control/loopback cell. Furthermore, data cells selected four different data outlet queues: Control Data queue, Constant Rate (CBR) queue, Variable Rate (VBR) queue, Available Rate (ABR) queue. CUBIT-Pro programmed receive cells into separate queues (split-queue mode) (single-queue mode). encoding rules two-byte CellBus Routing Header Bits 31-16 Cycle summarized Figure
Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header Tandem Routing Header Multicast Address_Control Multicast Address_Data Broadcast Address_Control Broadcast Address_Data Single Address_Loopback Single Address_Control Single Address_Data
Figure CellBus Routing Header Formats CellBus Routing Header Format CellBus Routing Header contains following fields, shown Figure Multi-PHY selector field bits). interpreted CUBIT-Pro currently (passed through intact). This field ignored. Queue selection field split-queue mode bits). outlet Control Data queue, Constant Rate (CBR) queue, Variable Rate (VBR) queue, Available Rate (ABR) queue. This coding only valid data cells which contain Q1,Q0 fields header. multicast broadcast cell routing, cells routed queues, respectively, when using split-queue mode. CUBIT-Pro single address field bits, addresses). LSB. example, A(4-0)=00000 address value CUBIT whose five device identity straps UA(4-0) tied high (HHHHH). Multicast number field bits, multicast sessions). LSB.
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CRC-4 field. This 4-bit field (H3-H0) provides Routing Header error protection across CellBus both directions. calculated over 12-bit word (X11-X0) bits 31-20 Routing Header using following logic: where represents logical exclusive-or. cells arriving from CellBus bus, CUBIT-Pro automatically calculates corresponding CRC-4 sets status CRCF (bit register 08H) same that bits H3-H0 received Routing Header. This status enabled cause interrupt signal microprocessor setting enable INTEN7 (bit register 09H). cells supplied cell inlet interface from external source transmission CellBus bus, CRC-4 either supplied input signal external logic required CUBIT device) generated internally inserted into Routing Header CUBIT-Pro. Setting control CRC4EN (bit register 0EH) activates internal CRC-4 insertion incoming cells (i.e., only data cells, also control cells loopback cells). When control CRC4I (bit register 0EH) internally generated CRC-4 inverted testing purposes. This effect externally-supplied CRC-4. operation CUBIT TXC-05801 mode with externally-supplied CRC-4, CRC4EN should which default power-up/reset. Tandem Routing Header Format two-byte Tandem Routing Header format Bits 15-0 Cycle same CellBus Routing Header format, used cascaded CellBus bus, conform different specification used another system. Tandem Routing Header passed unchanged through CellBus bus. CellBus Status Signals Monitoring CUBIT-Pro provides capability monitor activity CellBus bus. essential signals that determine whether active absence cell traffic) clock signals frame pulse. CellBus clocks (read write) generated externally CUBIT-Pro. either these clocks fails, entire will cease operation. CUBIT-Pro provides capability detect absence clock signal more than equivalent processor clock (PCLK) cycles. failure detection performed independently CellBus Read Clock (CBRC) CellBus Write Clock (CBWC). bits (register bits CBLORC CBLOWC) CUBIT-Pro memory used indicate clock loss event. Once event detected, these bits register will remain until microprocessor reads register, which point register will cleared. These events used generate microprocessor interrupt provided that appropriate bits interrupt enable register (address 06H, bits INTENA1 INTENA0) second monitoring function concerns detection loss frame. detection mechanism looks consecutive missing CellBus frame pulses 32-user mode (U32 Low), four consecutive missing CellBus frame pulses 16-user mode. CellBus Read Clock must present detect Loss Frame Pulse. CellBus Read Clock present CellBus Write Clock not, then both CBLOWC CBLOF will set. CBLOF generate interrupt microprocessor assuming that appropriate interrupt enable (register 06H, INTENA2).
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CUBIT-Pro CELL INLET OUTLET PORTS Cell Inlet Outlet ports constitute main interfaces cell traffic between CUBIT-Pro other devices either upper Physical (PHY) Layers. Several interfaces supported device: UTOPIA 8-bit mode, TranSwitch 16-Bit mode, TranSwitch ALI-25 device interface mode, Back-toBack (CUBIT-Pro-to-CUBIT-Pro interface). CUBIT-Pro provide address translation selected input TRAN (pin 154). translation selected, external hardware must provide CellBus Routing Header, Tandem Routing Header (optional), Acell. translation mode selected, hardware required only provide Acell CUBIT-Pro will perform translation based information programmed into attached translation SRAM. modes cell size selectable external pins LMODE2, LMODE1 LMODE0 (pins 156, 157, 158, respectively), described below. This feature permits CUBIT-Pro accommodate requirements different designs. Additionally, UTOPIA 16-Bit modes selected behave either master (Alayer device) slave (PHY layer device). selection between Aand layer device UTOPIA 16-Bit modes made PHYEN (pin 48), where enables layer device operation. CUBIT-Pro allows selection clock cell Inlet/Outlet operation from three different sources: CellBus clocks (CBRC, CBWC, 77), processor clock (PCLK, 32), externally supplied clock (LCLOCK, 45). clock selected will used UTOPIA 16-Bit Alayer device modes, ALI-25 (cell inlet clock) mode, Back-to-Back (cell inlet clock) mode, which CUBITPro sources interface clock. other modes clock input CUBIT-Pro. selection clock source cell interfaces performed control bits register 0BH: CLKS1, CLKS0. coding clock selection follows: CLKS1, CLKS0 0,0: Cell interface clock CellBus clock divided 2LINEDIV CLKS1, CLKS0 0,1: Cell interface clock LCLOCK clock divided 2LINEDIV CLKS1, CLKS0 1,0: Cell interface clock PCLK clock divided 2LINEDIV CLKS1, CLKS0 1,1: Reserved, 8-Bit UTOPIA Mode Aand Layer Emulation Typical signal connections CUBIT-Pro when operating UTOPIA mode illustrated Figures ALayer Layer cell level handshake modes, respectively. operating mode options UTOPIA mode controlled input pins TRAN, PHYEN, LMODE2, LMODE1 LMODE0, indicated tables Figures TRAN selects internal translation mode, asserted. UTOPIA mode, PHYEN determines whether CUBIT-Pro emulates device. LMODE2, LMODE1 LMODE0 determine cell inlet/outlet cell size. When internal translation used, cell exactly that defined UTOPIA, with 53-byte inlet cells. applications which internal translation function used, timing logical flow cell still identical that UTOPIA, except that 57-byte 55-byte inlet cells used, instead additional bytes Routing Header bytes which would inserted CUBIT-Pro translation function were used, instead added external translation function. connections different inlet outlet byte counts cell various modes shown table Figure ALayer emulation. Similarly, Figure shows connections byte counts Layer emulation. ABRENA must held high left floating internal pull-up) proper UTOPIA mode operation.
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Figure ALayer Emulation 8-Bit UTOPIA Mode Signal Connections Operating Mode Selection
UTOPIA Layer Device
Inlet
CID(7-0) CISOC CIF1 CIF2 CIF3 CIF4 CICLAV CIENB CICLK GFC3 GFC2 GFC1 GFC0 COD(7-0) COSOC COCLAV COENB COCLK
RxData RxSOC
CUBIT-Pro CellBus
CBD(31-0) CBRC CBWC CBACK CBCONG
RxClav RxEnb RxClk
Input
TxData TxSOC TxClav TxEnb TxClk
Outlet Microprocessor
PHYEN High
TRAN High
LMODE2 High
LMODE1
LMODE0 High
Operating Mode: Inlet UTOPIA, bytes: cell plus CellBus Routing Header plus bytes Tandem Routing Header UTOPIA, bytes: cell plus CellBus Routing Header plus bytes Tandem Routing Header UTOPIA, bytes: cell plus CellBus Routing Header UTOPIA, bytes: cell plus CellBus Routing Header UTOPIA, 53-byte cell UTOPIA, 53-byte cell
Operating Mode: Outlet UTOPIA, 53-byte cell
High
High
High
High
UTOPIA, bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell
High
High
High
High
High
UTOPIA, bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell UTOPIA, bytes: cell plus Tandem Routing Header Reserved Reserved Reserved Reserved
High High
High High
High High
High
High High High High
High
High High High
High High High
Reserved Reserved Reserved Reserved
Note: High VDD5 +5V; Ground; Don't Care
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Figure Layer Emulation 8-Bit UTOPIA Mode Signal Connections Operating Mode Selection
UTOPIA ALayer Device ATxData TxSOC CID(7-0) CISOC CIF1 CIF2 CIF3 CIF4 CICLAV CIENB CICLK GFC3 GFC2 GFC1 GFC0 COD(7-0) COSOC COCLAV COENB COCLK
Inlet CUBIT-Pro CellBus
CBD(31-0) CBRC CBWC CBACK CBCONG
TxClav TxEnb TxClk
Input
RxData RxSOC RxClav RxEnb RxClk
Outlet Microprocessor
PHYEN
TRAN High
LMODE2 High
LMODE1
LMODE0 High
Operating Mode: Inlet UTOPIA, bytes: cell plus CellBus Routing Header plus bytes Tandem Routing Header UTOPIA, bytes: cell plus CellBus Routing Header plus bytes Tandem Routing Header UTOPIA, bytes: cell plus CellBus Routing Header UTOPIA, bytes: cell plus CellBus Routing Header UTOPIA, 53-byte cell UTOPIA, 53-byte cell
Operating Mode: Outlet UTOPIA, 53-byte cell
High
High
High
UTOPIA, bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell
High
High
High
UTOPIA, bytes: cell plus Tandem Routing Header UTOPIA, 53-byte cell UTOPIA, bytes: cell plus Tandem Routing Header Reserved Reserved Reserved Reserved
High High
High High
High
High
High High High
High High High
Reserved Reserved Reserved Reserved
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ALI-25 Mode CUBIT-Pro supports ALI-25 interface devices, connects directly ALI-25C with glue logic, shown Figure ALI-25 mode there always translation, because ALI-25C device cannot produce CellBus Routing Header Tandem Routing Header. exception conditions ALI-25C supported through CUBIT-Pro pins CIF1, CIF2 CIF4. output CIF1 connects directly RFlush input ALI-25C. error condition ALI-25C, RDVal unexpectedly de-asserted CICLAV input, CUBIT-Pro will assert CIF1 flush ALI-25C declare start-of-cell (SOC) error. ALI-25C uses RFlshD output acknowledge CUBIT-Pro's CIF2 input that flush completed. second exception condition accommodated flagging error ALI-25C. error found, ALI-25C asserts EInt output pin, which drives CIF4 input CUBIT-Pro causes increment Error Counter. ABRENA must held high left floating internal pull-up).
Inlet ALI-25C
CID(7-0) CISOC CIF1 CIF2 CIF3 CIF4 CICLAV CIENB CICLK GFC3 GFC2 GFC1 GFC0 COD(7-0) COSOC COCLAV COENB COCLK RData RDPrty RFlush RFlshD Elnt RDVal RLoad RBClk
CUBIT-Pro CellBus
CBD(31-0) CBRC CBWC CBACK CBCONG
Input
TData TDPrty TdVal TLoad TBClk
Outlet Microprocessor
PHYEN
TRAN
LMODE2 High
LMODE1
LMODE0 High
Operating Mode: Inlet ALI-25: 53-byte cell
Operating Mode: Outlet ALI-25: 53-byte cell
Figure ALI-25 Mode Signal Connections Operating Mode Selection
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Back-to-Back Mode Back-to-Back mode used support interconnection CellBus buses, shown Figure TRAN low, each CUBIT-Pros translation memory connected, cell address translation function active, inlet cells bytes long. cells from outlet either bytes long. bytes selected, cell will carry Tandem Routing Header from CellBus bus. TRAN high, translation function used. transfers into cell inlet will bytes long. initial bytes presented CUBIT-Pro CellBus Routing Header. cell outlet present cells either bytes, whether internal translation performed cell inlet side. bytes selected, cell will carry Tandem Routing Header from CellBus bus. cell outlet will carry extra bytes which Tandem Routing Header from CellBus bus. These bytes presented inlet port connected CUBIT-Pro, which uses them CellBus Routing Header when puts cell bus. order avoid re-transmission multicast broadcast cells from CellBus another, back again, CUBIT-Pro which operating Back-to-Back mode will reject incoming broadcast multicast cells which originated from inlet side. timing this mode similar that UTOPIA ALayer emulation mode, except that directionality COCLAV, COENB COCLK signals reversed, shown connections diagrams Figures ABRENA must held high left floating internal pull-up).
Inlet CUBIT-Pro CellBus
CBD(31-0) CBRC CBWC CBACK CBCONG COCLK COENB COCLAV COSOC COD(7-0) CICLK CIENB CICLAV CISOC CID(7-0) CID(7-0) CISOC CICLAV CIENB CICLK
Outlet
COD(7-0) COSOC COCLAV COENB COCLK
CUBIT-Pro CellBus
CBD(31-0) CBRC CBWC CBACK CBCONG
Outlet Microprocessor
Inlet Microprocessor
PHYEN
TRAN High
LMODE2 High
LMODE1
LMODE0
Operating Mode: Inlet Back-to-Back: bytes, cell plus bytes CellBus Routing Header Back-to-Back: 53-byte cell Back-to-Back: 53-byte cell
Operating Mode: Outlet Back-to-Back: bytes, cell plus bytes Tandem Routing Header Back-to-Back: 53-byte cell Back-to-Back: bytes, cell plus bytes Tandem Routing Header Back-to-Back: 53-byte cell
High
High
High
Back-to-Back: bytes, cell plus bytes CellBus Routing Header
Figure Back-to-Back Mode Signal Connections Operating Mode Selection TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Byte Ordering UTOPIA, ALI-25 Back-to-Back Modes Byte ordering three cell inlet outlet alternatives described above illustrated Figure
First Byte Transferred
TandemRH TandemRH CellBusBusRH CellBusBusRH GFC, VPI, VCI, Byte Byte Byte CellBusBusRH CellBusBusRH GFC, VPI, VCI, Byte Byte Byte TandemRH TandemRH GFC, VPI, VCI, Byte Byte Byte GFC, VPI, VCI, Byte Byte Byte bytes, header
bytes, data
Byte Byte Last Byte Transferred Byte
Byte Byte Byte
Byte Byte Byte
Byte Byte Byte
Bytes Inlet
Bytes Inlet
Bytes Outlet
Bytes Inlet, Outlet Cell
Note: Routing Header
Figure Byte Ordering Cell Inlet Outlet UTOPIA, ALI-25 Back-to-Back Modes
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16-Bit Cell Interface Mode Aand Layer Emulation 16-Bit cell interface mode selected emulate ALayer UTOPIA device, alternatively emulate Layer UTOPIA device, shown Figures respectively. 16-Bit mode enabled setting device strap ABRENA low, with settings TRAN, LMODE2, LMODE1 LMODE0 selected according table Figure ALayer emulation, according table Figure Layer emulation. Layer emulation enabled with PHYEN. timing 16-Bit mode identical that UTOPIA mode, data width expanded word bits out. translation used this case. extra inlet bits connected pins used data translation RAM, (7-0), extra outlet pins pins translation address output, (7-0).
Inlet
TRD(7-0) CID(7-0) CISOC CIF1(ACK) CIF2 CIF3(NOACK) CIF4 CICLAV CIENB CICLK GFC3 GFC2 GFC1 GFC0 TRA(7-0) COD(7-0) COSOC COCLAV COENB COCLK
CUBIT-Pro CellBus
CBD(31-0) CBRC CBWC CBACK CBCONG
Outlet Microprocessor
PHYEN High
TRAN
LMODE2
LMODE1 High
LMODE0
Operating Mode: Inlet 16-Bit: words, cell plus word Tandem Routing Header, plus word CellBus Routing Header 16-Bit: words, cell plus word Tandem Routing Header, plus word CellBus Routing Header 16-Bit: words, cell, plus word CellBus Routing Header 16-Bit: words, cell, plus word CellBus Routing Header Reserved
Operating Mode: Outlet 16-Bit: words, cell plus word Tandem Routing Header
High
High
High
16-Bit: 27-word cell
High
High
16-Bit: words, cell plus word Tandem Routing Header 16-Bit: 27-word cell
High
High
High
Reserved
Figure ALayer Emulation 16-Bit Mode Signal Connections Operating Mode Selection
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Figure Layer Emulation 16-Bit Mode Signal Connections Operating Mode Selection
Inlet
TRD(7-0) CID(7-0) CISOC CIF1(ACK) CIF2 CIF3(NOACK) CIF4 CICLAV CIENB CICLK GFC3 GFC2 GFC1 GFC0 TRA(7-0) COD(7-0) COSOC COCLAV COENB COCLK
CUBIT-Pro CellBus
CBD(31-0) CBRC CBWC CBACK CBCONG
Outlet Microprocessor
PHYEN
TRAN
LMODE2
LMODE1 High
LMODE0
Operating Mode: Inlet 16-Bit: words, cell plus word Tandem Routing Header, plus word CellBus Routing Header 16-Bit: words, cell plus word Tandem Routing Header, plus word CellBus Routing Header 16-Bit: words, cell, plus word CellBus Routing Header 16-Bit: words, cell, plus word CellBus Routing Header Reserved
Operating Mode: Outlet 16-Bit: words, cell plus word Tandem Routing Header
High
High
16-Bit: 27-word cell
High
16-Bit: words, cell plus word Tandem Routing Header 16-Bit: 27-word cell
High
Reserved
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Word Ordering 16-Bit Cell Interface Mode word ordering 16-Bit mode shown Figure
29-Word Inlet
First Word Transferred
TandemRH TandemRH
28-Word Inlet
CellBusBusRH CellBusBusRH GFC, Byte Byte VPI, VCI, Undefined Byte Byte
28-Word Outlet
TandemRH GFC, Byte Byte TandemRH VPI, VCI, Undefined Byte Byte
CellBusBusRH CellBusBusRH GFC, Byte Byte VPI, VCI, Undefined Byte Byte
27-Word Outlet
GFC, Byte Byte VPI, VCI, Undefined Byte Byte
Byte Byte
Byte Byte Byte
Byte Byte Byte
Byte Byte Byte
Byte Byte Byte
Byte Byte Byte
Byte Byte Byte
Byte Byte Byte
Last Word Transferred
Byte
High Byte
Byte
High Byte
Byte
High Byte
Byte
High Byte
Byte
Figure Word Ordering Cell Inlet Outlet 16-Bit Mode
TRAFFIC MANAGEMENT FUNCTIONS Dynamic Generic Flow Control (GFC) Field Insertion CUBIT-Pro insert value first nibble Acell header real time. value nibble supplied CUBIT-Pro input pins GFC(3-0). insertion value enabled control GFCENA.
CUBIT-Pro Cell Outlet Port
Value
Output Cell Data
Cell from Outlet Queue
Calculation
GFCENA
Figure Insertion Outlet Queue (GFCENA control GFCENA (Control Register Address 0CH, one, then state four Generic Flow Control input pins GFC(3-0) will accepted during leading rising edge clock first byte Acell header inserted outgoing following cell (see timing diagram Figure details). Therefore value inserted into next outgoing cell. TXC-05802-MB September 1998
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Forward Explicit Congestion Notification (FECN) CUBIT-Pro notify impending congested state setting middle Payload Type (PT) field Acell header. This Explicit Forward Congestion Indication (EFCI) will asserted cell both conditions occur same time: register (IFECN (bit register 0CH) Limit reached, QM=1 Limit Limit reached. activation EFCI single-queue split-queue modes illustrated Figures respectively.
VBRLIMIT Single Queue Cell Outlet Port Cell Cell Cell Cell Cell Cell
Sync FIFO
Note: IFECN control EFCI congestion indication middle sequence (X0X X1X). value determined when cell leaves queue.
Figure Example Congestion Indication Single-Queue Mode Figure shows starting condition single-queue mode soon after congestion conditions have both become present, with three cells queue when VBRLIMIT Cells reached Sync FIFO before congestion occurred, they marked with congestion indication have value X0X. first cell queue (cell marked with congestion indication X1X) moves into Sync FIFO when outlet link free Cell sent cell outlet port. Cells then shift left, putting Cell VBRLIMIT boundary, congestion persists Cell also marked with X1X. When this cell moves into Sync FIFO, Cell shifts left only cell left queue, assuming more cells have joined queue. Since queue length less than VBRLIMIT condition longer exists cell carries congestion marking X0X).
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Figure shows starting condition split-queue mode some time after congestion conditions have both become present, with three cells cell queue when CBRLIMIT cells cell queue when VBRLIMIT (i.e., both queues congestion level).
Control Data Cell Queue (Priority
CBRLIMIT Cell Queue (Priority Cell Cell Cell Cell Queue (Priority Cell Cell Cell Queue (Priority
Sync FIFO Cell Outlet Port Cell Cell Cell
VBRLIMIT
Note: IFECN control EFCI congestion indication middle sequence (X0X X1X). value determined when cell leaves queue.
Figure Example Congestion Indication Split-Queue Mode (QM=1) before, cells left queues before congestion occurred marked congestion indication X0X). When outlet link becomes free cells Sync FIFO shift left, cells flow Sync FIFO from four data cell queues priority order. Since queue contains cells when VBRLIMIT congestion continues exist while cells cell queue moved into Sync FIFO, cells marked with congestion indications X1X). Now, assuming more cells joining queues, cell queue empty cell queue still VBRLIMIT value with cells, cell also marked with congestion indication. when moves Sync FIFO only cell left cell queue, conditions longer both exist, this cell marked with congestion indication X0X).
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Congestion Indication from CellBus Cell Inlet event congestion being experienced output port receiving CUBIT-Pro, three bits relayed back sending CUBIT-Pro allow congestion control. output signals provided sending CUBIT-Pro are: CONGOUT: This output signal dual function which selected with (bit register 0EH). EBP=0 (default power-up/reset) CONGOUT straight GTL-to-CMOS translation CellBus signal CBCONG. EBP=1, then CONGOUT indication that receiving CUBIT-Pro experiencing congestion impending congestion. These situations correspond case where outlet queue receiving CUBIT-Pro full congestion limit (almost full) that queue been reached, respectively. case almost full cell will lost CLP=0 cycle full queue will accept cells. this case, NACK will also received. pulse available CONGOUT output (pin 155) CUBIT- sending cell after receiving CUBIT-Pro experiences congestion (for UTOPIA, 16-Bit, Back-to-Back modes). ACK: Positive acknowledge which indicates that cell accepted destination CUBIT-Pro. pulse provided CIF1 output (pin 118) CUBIT-Pro sending cell cell successfully accepted (for UTOPIA, 16-Bit, Back-to-Back modes). NACK: Negative acknowledge which indicates cell forwarded outlet queue receiving CUBIT-Pro. pulse provided CIF3 output (pin 115) CUBIT-Pro sending cell cell forwarded, dropped (for UTOPIA, 16-Bit, Back-to-Back modes). Note: (address 0EH, must enable NACK functions CIF1 CIF3 UTOPIA back-to-back modes. NACK functions CIF1 CIF3 always enabled 16-Bit mode. Paralleling Cell Inlet/Outlet Ports Redundancy control ONLINE (control register address 0CH, zero, then CUBIT-Pro cell outlet interface output pins will taken high impedance (Hi-Z) state cell inlet data input pins will disabled. Thus CUBIT-Pros paralleled redundancy, each connected separate CellBus bus. Cells will only accepted from, sent line CUBIT-Pro which ONLINE
INLET-SIDE TRANSLATION Introduction translation function inlet side operates using information stored external static RAM, provide following functions: Virtual Path Identifier (VPI) translation VPI/VCI translation (where Virtual Circuit Identifier), CellBus Routing Header insertion, Tandem Routing Header insertion, flow cell routing, flow cell routing.
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translation operations start performing translation table lookup based number incoming cell. Within routing table record that control information that VPI, indicating whether cells routed based number alone VCI. VPI-only routing selected, translated number, accompanied CellBus Tandem Routing Headers, retrieved from translation record that VPI. this case, number incoming cell changed. translation selected, separate routing flow cells RM-VPC cells that programmed, allowing selective handling these OAM-cells RM-cells CellBus system. instead programmed translation, then two-step procedure used accomplish translation. record, accessed first, indicates size position memory translation table. Using this information, address cell, translation record accessed. This translation record contains numbers assigned cell, along with CellBus Tandem Routing Headers. When VPI/VCI translation selected, separate routing flow cells RMVCC cells that programmed, allowing selective handling these OAM-cells RM-cells manner similar that flow cells RM-VPC cells. both cases, cells with translated headers CellBus Tandem Routing Headers forwarded sequential order. Translation does delay cells passing through inlet side CellBus bus. Translation Connections CUBIT-Pro address 256k bytes translation SRAM (TRAM). connections TRAM shown Figure TRAM access time requirement dependent upon cell inlet clock speed (i.e., ALayer mode: CellBus clock, PCLK, LCLOCK; Layer mode: CICLK), Figures access time nanoseconds less will support maximum CellBus speed. Translation SRAM
ADDR DATA
Chip Select Generation Logic
TRWE TROE
CUBIT-Pro
Figure Translation Connections chip select should implemented according number SRAM devices used design. single 256k SRAM used, memory permanently selected, low-power application required then memory selected only when CUBIT-Pro needs access SRAM (use TROE TRWE, shown Figure 17). Translation Control When CUBIT-Pro device configured perform translation (input TRAN low), replaces received values numbers with values, adds Routing Headers cells forwarded CellBus bus. VPI/VCI number Routing Header information that inserted comes from translation record entries TRAM. TRAM organized into block records block records, contents which established system control.
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Translation Organization translation partitioning shown Figure lower portion TRAM contains translation records VPIs. When mode enabled (control UNI=1), number entries 256. When mode enabled (UNI=0), 4096 entries present. Depending whether Tandem Routing Header enabled Record has: four bytes Tandem Routing Header (TRH) used (control TRHENA=0), bytes used (TRHENA=1). size memory space this mode ranges from 1024 bytes (UNI mode, TRH, 256) 24576 bytes (NNI TRH, 4096). memory space above section translation record storage space, divided into number pages. Each page contains translation records 128, 256, 512, 1024 VCIs. Depending whether Tandem Routing Header enabled Record has: bytes Tandem Routing Header (TRH) used (control TRHENA=0), eight bytes used (TRHENA=1). number records page (VRP) depends settings VRPS[1,0] control bits register follows: VRPS[1,0]=0,0: VRPS[1,0]=0,1: VRPS[1,0]=1,0: 1024 VRPS[1,0]=1,1: total size TRAM which CUBIT-Pro support 262,144 bytes (256k). Hence, number translation table pages which supported function memory size, states control bits TRHENA. example, maximum number memory pages, maximum memory size, follows: VRPS[1,0]=0,0: UNI=1, TRHENA (262144-(256*6))/(256*8) Pages, UNI=1, TRHENA (262144-(256*4))/(256*6) Pages. VRPS[1,0]=0,1: UNI=1, TRHENA (262144-(256*6))/(512*8) Pages, UNI=1, TRHENA (262144-(256*4))/(512*6) Pages. VRPS[1,0]=1,0: 1024 UNI=1, TRHENA (262144-(256*6))/(1024*8) Pages, UNI=1, TRHENA (262144-(256*4))/(1024*6) Pages. VRPS[1,0]=1,1: UNI=1, TRHENA (262144-(256*6))/(128*8) Pages, UNI=1, TRHENA Min[(262144-(256*4))/(128*6), 256] [340,256] Pages. VRPS[1,0]=1,1, 128. maximum number addressable pages 256, even though, theoretically, pages could SRAM 256k bytes.
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6143 8191 1023 Record
VRPS[1,0] VRPS[1,0]
3071 4095 Record Record Record Record Record Page
VRPS[1,0]
1535 2047 Record Record Record 1023
VRPS[1,0]
Record Record Page Page Page
Translation Table
VRPS[1,0]
1023, 1535, 16383 24575 Record Record Record Record Record Page
Translation Table
Figure Translation Organization Page Organization This page optionally used OAM-cells routing, RM-cells routing, data cells routing. OAM/RM reserved VCs, OAMRMEN (bit register 0EH) must OAM/RM routing enabled (OAMRMEN=1) then organization Page shown Figure
Last Record (127, 255, 511, 1023)
Page
Record Record Record Record Record Record Record Record Record Record Record Record Record Record
OAM-F5 Cells (PT= 111) Record RM-VCC Cells (PT= 110) Record OAM-F5 Cells (PT= 101) Record OAM-F5 Cells (PT= 100) Record RM-VPC Cells Record
OAM-F4 Cells Records
Reserved Special Cells
Figure Page Organization (Bit OAMRMEN=1) device required operate CUBIT TXC-05801 applications, then OAMRMEN must which power-up/reset default.
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Translation Procedure Translation performed two-step procedure, starting with examining incoming number. full 8-bit (UNI=1) 12-bit (UNI=0) number used. incoming number used address translation record. translation done only, leaving number intact, then number routing header contained translation record. translation done, then record contains pointer location more "pages" translation records. Each "page" translation records either 128, 256, 512, 1024 consecutive numbers (depending settings bits VRPS[1,0] register 0EH). sixteen such pages assigned VPI. only restriction that pages each must assigned consecutive address space from zero upwards. Within this assigned space, number incoming cell used address particular translation record containing numbers routing header. OAM/RM cells routed either from record record that marked this special cells routing, detailed section below entitled "OAM-Cells RM-Cells Record Format". translation operation CUBIT-Pro uses several data structures. These data structures three different types: Record Record OAM/RM Record Each these records contains more control bits first byte record (byte which determines whether routing OAM/RM cell. control bits described next. Translation Records Control Bits Four control bits, labelled used byte translation records, described below: Active Bit: translation record, then that active. Cells received with this will translated forwarded bus, unless one. A=0, then cells received this will considered misrouted, unless I=1. Translation Enable (P): this translation record, then VPI-only translation made. zero, combined translation made. OAM/RM Cell Routing Enable (E): record, then VCIs numbered through that will routed according OAM/RM records contained record numbers through page zero. Additionally, record, then cells that with having will routed according translation record contained record number page zero. Regular data cells (not conforming above rules) routed according and/or record. record, then cells that having 100, 101, 110, 111(Payload Type Indicator, Acell header) will routed according translation record contained record numbers page zero, respectively. Ignore (I): ignore (I=1) active (i.e., translation record) then incoming cells bearing this number discarded, counted misrouted cells. control NOTIGN (bit register 0EH) then connections with will treated I=0.
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OAM/RM Routing Mode Bits (C1,C0): These bits used determine which VPI/VCI OAM/RM cells routed. possible combinations are: C1,C0 0,0: cell header translated according values OAM/RM record (this value OAMRMEN=0 should selected applications supporting CUBIT TXC-05801 functionality) C1,C0 0,1: flow this virtual path connection (VPC) cells/RM-VPC cells routed according OAM/RM record. Instead, these cells routed according record corresponding incoming flow this virtual circuit connection (VCC) cells/RM-VCC cells routed according OAM/RM record. Instead, these cells routed according record corresponding incoming VP/VC combination. C1,C0 1,0: attach CellBus Routing Header (CBRH) Tandem Routing Header (TRH) only, preserve incoming VP/VC combination C1,C0 1,1: reserved Note: order Tandem Routing Header, TRHENA must selected regardless table values. CellBus Routing Header CellBus Routing Header 16-bit structure, which formatted described earlier CellBus Cell Routing subsection. Additional detail provided Appendix "CellBus Technical Manual CUBIT-Pro Applications", TranSwitch document number TXC-05802-TM1. Tandem Routing Header Tandem Routing Header used CellBus Routing Header, when passed through CUBIT-Pro back-to-back mode, must follow same construction rules CellBus Routing Header. Tandem Routing Header used some proprietary purposes, format will follow different specification.
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Translation Record Formats Translation Record Formats translation records four bytes long TRHENA=0, bytes long TRHENA=1, shown Figure Each either idle busy. busy, then each VPI-only translation, combined VPI/VCI translation. control bits Routing Headers described preceding sections.
Idle VPI, TRHENA=1 Idle VPI, TRHENA=0
unused, then (Active bit, relative address zero zero, indicating idle. cell arrives with this number, discarded counted misrouted cell.
Translation, TRHENA=1 Translation, TRHENA=0
CellBus Routing Header CellBus Routing Header VPI, VPI, Tandem Routing Header Tandem Routing Header CellBus Routing Header CellBus Routing Header VPI, VPI,
busy have number translation only, then set=1, set=1. this case, inserted cell contained relative address zero VPI), relative address VPI). CellBus Tandem Routing Headers also contained next four bytes. busy combined VPI/VCI number translation, reference generated translation record. active (A=1), translation (P=0). relative address zero contain Page Size, which number assigned pages, each 128, 256, 512, 1024 records, allocated this (range from where 0H=16). Relative address contains Page Offset, which indicates where among pages first utilized page starts.
Translation, TRHENA=1 Translation, TRHENA=0
Page Offset Page Size
Page Offset Page Size
Figure Translation Record Formats
calculation start address record when there Tandem Routing Header (control TRHENA=0) performed follows: VP_Start_Addr TRHENA=1 then: VP_Start_Addr
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Translation Record Formats translation records bytes long TRHENA=0, eight bytes long TRHENA=1, shown Figure Each either idle busy.
IDLE VCI, TRHENA=1 IDLE VCI, TRHENA=0
inactive (A=0) Ignore (I=0), then cells arriving bearing that number discarded counted misrouted. I=1, they discarded counted misrouted.
Translation, TRHENA=1 Translation, TRHENA=0
CellBus Routing Header CellBus Routing Header VCI, VCI, VPI, VPI,
Tandem Routing Header Tandem Routing Header CellBus Routing Header CellBus Routing Header VCI, VCI, VPI, VPI,
active (A=1), then numbers inserted cell, CellBus Routing Header used, read from translation record positions indicated.
Figure Translation Record Formats
calculation start address record uses information from table addressed incoming cell, well information incoming cell. information required from record Page Offset (VPO). case with Tandem Header Translation (control TRHENA=0 register 0AH) mode (control UNI=1 register 0AH) start address record corresponding incoming VP/VC, assuming given number records page (VRP, determined control bits VRPS1 VRPS0 register 0EH) calculated decimal format) follows: VC_Start_Address 1024 with TRHENA=1 UNI=1: VC_Start_Address 1536 with TRHENA=0 UNI=0: VC_Start_Address =16384 with TRHENA=1 UNI=0: VC_Start_Address 24576
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OAM-Cells RM-Cells Record Format OAM/RM reserved cells routing performed VP/VC combination with appropriate programming E-bit translation record, setting OAMRMEN (bit register 0EH) compatibility with CUBIT TXC-05801 applications, OAMRMEN should (default). Both flows supported CUBIT-Pro. Depending which flow routed, algorithms used CUBIT-Pro (assuming OAMRMEN=1). algorithm F5-flow depicted Figure field Acell header coming VP/VC that VP/VC translation (with E-bit translation record) will checked possible values routed Page according flow shown Figure flow cell coming will sent Page within numbers 0-31 (OAMRMEN=1) according algorithm shown Figure
Incoming Cell
VPI/VCI Translation? Record: E-Bit
Route According Translation
Route According Record
ACell Header: 100? Route According Page
ACell Header: 101? Route According Page
ACell Header: 110? Route According Page
ACell Header: 111? Route According Page
ACell Header: 0xx? Route According Record
Figure RM-VCC Cell Routing (Bit OAMRMEN=1)
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Incoming Cell
Translation? E-Bit
Route According VP/VC Translation
Route According Record
0.31? 7.31? Route According 7.31 Page
110? Route According Page
Route According Page
Figure RM-VPC Cell Routing (Bit OAMRMEN=1) corresponding formats translation records shown Figure
IDLE VCI, TRHENA=1 IDLE VCI, TRHENA=0
inactive (A=0) Ignore (I=0), then cells arriving bearing that number discarded counted misrouted. I=1, they discarded counted misrouted.
Translation cells, TRHENA=1 Translation cells, TRHENA=0
CellBus Routing Header CellBus Routing Header VCI, VCI, VPI, VPI,
Tandem Routing Header Tandem Routing Header CellBus Routing Header CellBus Routing Header VCI, VCI, VPI, VPI,
bits determine type translation OAM/RM cells received. coding explained "Translation Records Control Bits" section.
active (A=1), then numbers inserted cell, CellBus Routing Header used, read from translation record positions indicated.
Note: OAM/RM Translation Records optional. They located page zero.
Figure OAM/RM-Cells Translation Record Formats TXC-05802-MB September 1998
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MULTICAST NUMBER MEMORY multicast address control cell multicast address data cell sent number CUBIT-Pros, single CUBIT-Pro receive cells with number different addresses. This controlled setup Multicast Number Memory (addresses E0H-FFH CUBIT-Pro memory map), which block bytes. Each bits block maps multicast address, shown Figure When CUBIT-Pro enabled receive corresponding multicast address cell. Each CUBIT-Pro receive possible multicast addresses.
this location enables multicast address Field FFH) this location enables multicast address Field F8H)
Addresses (32)
Byte
this location enables multicast address Field 00H)
this location enables multicast address Field 07H) Note: Field refers CellBus Routing Header Multicast Address cells (see Figure
Figure Multicast Number Memory
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CellBus INTERFACE Thirty-seven lines comprise CellBus interface, shown Figure There thirty-two Data lines, with Frame, Acknowledge, Congestion Indicator lines, sourced CUBIT- device, Clock lines sourced external drivers. Operation with Internal Transceivers Gunning Transceiver Logic (GTL) transceivers CellBus Data, Frame, Acknowledge, Congestion Indicator lines contained internally CUBIT-Pro, along with clock line receivers. Each drivers maximum current sink capability capable driving card backplane directly. Each lines pulled-up each ends (+/- resistor (metal film carbon composition) +1.2 low-impedance supply. Each each line should have filtering capacitor connected from +1.2 supply ground, shown Figure
+1.2V 0.01µF +1.2V 0.01µF
CUBIT-Pro
CUBIT-Pro
CUBIT-Pro
Figure External Circuit Requirements Transceivers CUBIT-Pro pinout, pins involved with interface aligned along side package between pins 112. This side package must aligned toward board connector, toward bus, with little board trace length possible between pins connector bus, maximize operating speed. Clock Source GTL-level clock signals must driven CellBus from external source. These write clock, CBWC, read clock, CBRC. phase relationship keeping write clock between nanoseconds behind read clock needed ensure proper synchronous operation. When clock driver driven from center backplane (i.e., greater than half backplane length from card) minimum phase distance more must maintained. When driver ends, more conservative minimum required. CellBus implementation, backplane each card, care must taken ensure that these lines routed together. capacitive inductive loadings lines should nearly equal possible, maintain performance. drive point, delay line should used maintain stable delay, read write clock drivers must units same integrated circuit package. these precautions will ensure most stable clocks permit highest possible operating speed. Arbiter Selection copy CellBus Arbiter circuitry included inside each CUBIT-Pro device. Enabling arbiter particular CUBIT-Pro done connecting ENARB that device ground (VSS). Normally, arbiter turned remaining arbiters that turned off. responsibility overall system control decide which CUBIT-Pro will have arbiter enabled, enable Failure arbiter detected using NOGRT indications. multiple CUBIT-Pros indicating NOGRT failures, arbiter failure indicated. again responsibility system control enable another arbiter. Upon switching from arbiter another, receiving devices will automatically re-align frame position within CellBus frame.
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OUTLET-SIDE QUEUE MANAGEMENT CUBIT-Pro contains 123-cell queuing FIFO data outlet side. This FIFO operated single 123-cell FIFO, split into four independent FIFOs. Single Queue Operation control Address 0CH, zero, then outlet single 123-cell FIFO. This mode appropriate when single type traffic switched system. this case cell congestion, purposes causing FECN enabled control IFECN Address 0CH, established register VBRLIMIT Address 12H. Split-Queue Operation outlet FIFO split into separate queues. These are, order service priority, Control Data (highest priority), CBR, VBR, ABR. Control Data cell queue fixed length cells, queue cells. congestion threshold queue size queue contents register CBRLEN Address 10H, congestion point CBRLIMIT Address 11H. remaining FIFO cells assigned queue. length queue (123-2-32-CBRLEN 89-CBRLEN), congestion limit VBRLIMIT Address 12H. Note differences between control data queue section split outlet queue, control cell receive buffer control cell transmit buffer (all referred control queue): control data queue section split outlet queue accepts cells from CellBus that have single address data routing header with field (see Figure control cell receive buffer (address 60H-93H) accepts cells from CellBus that have single address control routing header (see Figure control cell transmit buffer loaded microprocessor with cell sent CellBus bus. have CellBus Routing Header formats shown Figure Multicast Broadcast cells split-queue mode sent queues, respectively.
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MICROPROCESSOR INTERFACE General Description CUBIT-Pro Microprocessor Port will support interface characteristic either Intel Motorola microprocessors, shown Figure
Intel Interface
PCLK MOTO
CUBIT-Pro
CUBIT-Pro PCLK RD/WR DTACK MOTO
Motorola Interface
Figure Microprocessor Port Interface Connections connections address A(7-0), data D(7-0), select (SEL) processor clock (PCLK) same both cases. Differences listed below. Intel Mode Enabled when device strap MOTO connected (ground). Connections shown Figure differences support Intel mode are: execute write command, execute read command, Interrupt active high, Ready active high. When low, requests microprocessor wait time. Motorola Mode Enabled when device strap MOTO connected VDD5 (+5V). Connections shown Figure differences support Motorola mode are: used must pulled volts, RD/WR high execute read command execute write command, Interrupt active low, Data Transfer Acknowledge DTACK active low. When inactive, pulled high external pullup resistor, requests microprocessor wait time.
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Interrupts CUBIT-Pro allows generation interrupts based thirteen different events. events latched status registers located addresses 08H, shown Figures events will generate interrupt provided corresponding interrupt enable bit, located registers addresses 09H, one. events occurs, corresponding status will one. status bits register cleared when read, except bits which events still persist. Some enabled interrupts cleared absence CellBus clocks. Such interrupts will persist until clocks re-applied. possible, however, mask interrupt regardless absence presence CellBus clocks. events reported explained below: Status register address 05H: (MSB) CTNAK CTACK RESERVED BIP-8 CBLOF (LSB) CBLORC CBLOWC
Figure CUBIT-Pro Status Register Address CTNAK Microprocessor Control Cell Negative Acknowledge: cell transmitted from Microprocessor Control queue CellBus received destination CUBIT-Pro, this CTACK Microprocessor Control Cell Positive Acknowledge: cell transmitted from Microprocessor Control queue CellBus successfully received destination CUBIT-Pro, this BIP-8 Error: BIP-8 field (Grant cycle) CellBus cell body cell received from CellBus does match calculated BIP-8, this (see Figure CBLOF CellBus Loss Frame Pulse Error: event that CellBus frame pulse present more than consecutive 16cycle frames, CellBus Write Clock present, this CBLORC CellBus Loss Read Clock Error: CellBus Read Clock present, this will CBLOWC CellBus Loss Write Clock Error: CellBus Write Clock present, this will Status register address 08H: (MSB) CRCF CRQOVF CRQCAV INSOC CTSENT NOGRT RESERVED (LSB) OCOVF
Figure CUBIT-Pro Status Register Address TXC-05802-MB September 1998
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CRCF CRC-4 Error: CRC-4 field H(3-0) CellBus Routing Header cell received from CellBus does match calculated CRC-4, this (see Figure CRQOVF Control Receive Queue Overflow: overflow will occur, this will when more than four cells accumulate control receive queue. CRQCAV Control Receive Queue Cell Available: When control cell been received from CellBus placed receive buffer (addresses 60H-93H) this will This cleared after microprocessor writes CRQSENT. INSOC Inlet Start Cell: ALayer Emulation UTOPIA 8-bit (PHYEN High) ALayer Emulation 16-Bit (PHYEN High) modes Back-to-Back mode, CISOC present same clock cycle that CICLAV asserted, CISOC asserted before current cell, INSOC Layer Emulation UTOPIA 8-bit (PHYEN Low) Layer Emulation 16-Bit (PHYEN Low) modes, CISOC present same clock cycle that CIENB asserted (after CICLAV been asserted signaling transfer first byte cell), CISOC asserted before current cell, INSOC ONLINE disable cell acceptance cell inlet, arrival cell will cause INSOC order prevent generation false interrupts, interrupt-enable INSOC (INTEN4) should also when ONLINE layer emulation mode. ALI-25 mode, RDVal deasserted prematurely INSOC error will occur. CTSENT Control Cell Sent: When microprocessor requests that control cell sent CellBus bus, this will after cell been sent. NOGRT Grant: CUBIT-Pro device requested CellBus grant received after number frames indicated TIME register (address 0FH), this will OCOVF Outlet Cell Overflow: single-queue mode overflow will occur, this will when more than cells accumulate outlet queue. split-queue mode this overflow will occur following events occurs: More than cells accumulate queue More than CBRLEN (address 10H) cells accumulate queue More than minus CBRLEN) cells accumulate queue More than cells accumulate control queue.
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Control Queue Send Receive formats send (transmit) receive control cells shown Figure Reference Figure will helpful understanding cells handled inlet outlet control queues. cell sent from microprocessor CellBus using control cell transmit buffer (Inlet Control Queue Figure This ability allows microprocessor send type data, control loopback cell CUBIT-Pro CellBus bus. microprocessor first writes 56-byte transmit cell with format shown Figure control cell transmit buffer (Addresses A0H-D7H CUBIT-Pro memory map). Then written control CTRDY (Address 0AH, cell will sent CellBus after pending data cells, CTSENT (Address 08H, will then CTRDY will reset Another such cell send sequence started after CTSENT been received. four-cell FIFO buffer (Outlet Control Queue Figure provided reception control cells from CellBus bus, since control cells arrive from several sources have wait microprocessor accept them from CUBIT- Pro. FIFO output 52-byte memory segment CRQ(51-0) Addresses 93H-60H. When this segment acquires received control cell CUBIT-Pro sets interrupt CRQCAV (Address 08H, This enabled cause interrupt microprocessor setting interrupt enable INTEN5 Address 09H, When interrupt polling process causes microprocessor read interrupt event status register Address will detect CRQCAV indication that control cell available reading. must then read CRQ(51-0) control CRQSENT upon completion (Address 0AH, This notifies CUBIT-Pro reset CRQCAV place next control cell CRQ(51-0), either immediately from adjacent FIFO cell, occupied, whenever next cell arrives FIFO from CellBus bus. CUBIT-Pro resets CRQSENT CUBIT-Pro handshake mechanism whereby interrupt generated indicating whether cell received not. bits available, CTACK CTNAK (bits register 05H) which cell sent from microprocessor interface accepted destination, respectively. These interrupts enabled setting bits register (INTENA6 INTENA7). Control cell transmission reception still performed regardless state control ONLINE (Address 0CH,
Byte
CellBusBusRH CellBusBusRH TandemRH TandemRH GFC, VPI, VCI, Byte Byte Byte GFC=0, VPI, VCI, Byte Byte Byte
Byte Byte Byte
Byte Byte Byte
Transmit Control Cell
Receive Control Cell
Figure Transmit Receive Control Cell Formats TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
LOOPBACK CELL SEND, RECEIVE RELAY loopback function provided diagnostic purposes. used on-line (ONLINE off-line (ONLINE loopback path cell from CUBIT-Pro CUBIT-Pro back CUBIT-Pro loading LBADDR registers Addresses CUBIT-Pro with single address control CellBus Routing Header CUBIT-Pro shown Figure microprocessor then writes cell with single address loopback Routing Header CUBIT-Pro into control transmit buffer (Addresses A0H-D7H) CUBIT-Pro causes cell sent. When CUBIT-Pro receives cell will contents LBADDR form Routing Header cell send back CUBIT- CUBIT-Pro will receive cell place control receive buffer where examined microprocessor. above description assumes that loopback cell originates control transmit buffer CUBIT-Pro could also received from inlet port. seven Routing Header formats shown Figure could actually loaded LBADDR register CUBIT-Pro instead single address control CellBus Routing Header CUBIT-Pro with corresponding change final destination loopback cell.
address CUBIT-Pro
CellBus Routing Header (single address control shown, Figure
LBADDRL (address 13H) Memory CUBIT-Pro LBADDRU (address 14H)
Note: indicates don't care state
Figure Loading Loopback Registers aspects system operation responsibility control system implemented CUBIT-Pro devices. Care must taken ensure that more than CUBIT-Pro trying loopback into same CUBIT-Pro, mis-routing will ensue.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
MEMORY RESET STATES general conditions resetting memory states are: input clock signals present, DEVHIZ TSTMODE input pins high. There alternative reset conditions that reset memory registers through values shown following table: power-up, hardware reset applied RESET input pin. Address (Hex) Reset Value (Hex) XX(1) XX(2) A0-D7 XX(3) XX(3) Others 00(4)
Notes: Reset value depends content location TRAM. Reset value depends state pins ABRENA, U32, ENARB UA(4-0). Undefined value after power-up. Pre-existing value affected hardware reset. Except reserved addresses, which contain undefined values after power-up hardware reset.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802 DIAGRAM
LMODE2CONGOUT TRANABRENATRA16 VDD5 TRA17 TRD0 TRD1 TRD2 TRD3 VDD3 TRD4 TRD5 TRD6 TRD7 TRWEVDD5 TROEVSS CID0/RData0 CID1/RData1 CID2/RData2 CID3/RData3 VDD3 CID4/RData4 CID5/RData5 CID6/RData6 CID7/RData7 CISOC/RDPrty VDD5 CICLK/RBClk CIENB-/RLoad CICLAV/RDVal CIF1/RFlush CIF2/RFlshD VDD3 CIF3 CIF4/EInt CBD31VSS CBD30CBD29VSS CBD28VREF VDDBOOT
Note: space limitations, active (inverted) active-on-falling-edge signals indicated their symbol (e.g., LMODE1- equivalent LMODE1).
U32UA4UA3UA2UA1UA0VSS FRCABRCNG VDD5 VDD5 VDD5 VDD3 PCLK VDD3 SELWRRD- RD/WRVDD5 INT/IRQRDY/DTACKMOTO RESETVDD5 TESTINLCLOCK TSTOUT PHYENVSS CBACKCBCONGVSS
Figure CUBIT-Pro TXC-05802 Diagram
LMODE1LMODE0VSS TRA15 TRA14 TRA13 TRA12 VDD5 TRA11 TRA10 TRA9 TRA8 VDD5 TRA7 TRA6 TRA5 TRA4 TRA3 TRA2 TRA1 TRA0 VDD3 COD7/TData7 COD6/TData6 VDD5 COD5/TData5 COD4/TData4 VDD5 COD3/TData3 COD2/TData2 COD1/TData1 COD0/TData0 VDD3 COCLAV/TdValCOSOC/TDPrty VDD5 COCLK/TBClk COENB-/TLoad GFC3 GFC2 VDD5 GFC1 GFC0 SCAN2 SCAN1 TSTMODEDEVHIZENARB-
CUBIT-Pro
TXC-05802 Diagram (Top View)
CBD27VSS CBD26CBD25VSS CBD24CBD23VSS CBD22CBD21VSS CBD20NC CBD19VSS CBD18VDD3 CBD17VSS CBD16CBD15VSS CBD14CBD13VSS CBRCCBWCVSS CBD12CBD11VSS CBD10NC CBD9VSS CBD8VDD3 CBD7VSS CBD6CBD5VSS CBD4CBD3VSS CBD2CBD1VSS CBD0CBFCBDISABLE-
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802 DESCRIPTIONS
POWER SUPPLY, GROUND CONNECT PINS Symbol VDD5 123, 137, 151, 164, 169, 182, 185, 194, 116, 130, 144, 179, 102, 108, 111, 113, 119, 125, 135, 139, 149, 159, 174, 188, 197, I/O/P* Type Name/Function VDD5: volt supply voltage,
VDD3
VDD3: +3.3 volt supply voltage, VSS: Ground, volt reference.
VDDBOOT
VDDBOOT: supply voltage, 10%, which must present CellBus disable function work. Connect: pins connected, even another pin, must left floating. Connection pins impair performance cause damage device. Some pins assigned functions future upgrades device. Compatibility CUBIT-Pro TXC-05802 device existing CUBIT TXC-05801 applications rely upon these pins having been left floating.
Note:
I=Input; O=Output; OD=Open Drain Output; P=Power
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CUBIT-Pro TXC-05802
CELL INLET Symbol** CICLAV/ RDVal I/O/P Type* Name/Function
TTL/ Cell Inlet Cell Available: direction CICLAV signal depends mode selected: ALayer emulation: active high input signal from Layer device indicate that complete cell transfer. This applies UTOPIA 16-Bit modes. Layer emulation: active high output signal indicate that CUBIT-Pro space receive cell from ALayer device. This applies UTOPIA 16-Bit modes. Back-to-Back mode: CICLAV active high input signal. ALI-25 mode: RDVal signal (input). TTL/ Cell Inlet Clock: Transfer clock. Rising edge CICLK used data transfer. ALayer emulation: clock output. This applies UTOPIA 16-Bit modes. Layer emulation: clock input. This applies UTOPIA 16-Bit modes. Back-to-Back mode: clock output. ALI-25 mode: RBClk signal (output). Maximum clock speed with 40/60 duty cycle. Cell Inlet Data: Byte-parallel input data. RData(7-0) input ALI-25 mode.
CICLK/ RBClk
CID(7-4) CID(3-0)/ RData(7-0) CIENB/ RLoad
126-129, 131-134
TTL/ Cell Inlet Enable: direction CIENB signal depends mode selected: ALayer emulation: active output signal indicating that input data CISOC will sampled next cycle. This applies UTOPIA, 16-Bit, Back-to-Back modes. Layer emulation: active input signal indicating that input data CISOC will sampled next clock cycle. This applies UTOPIA 16-Bit modes ALI-25 mode: RLoad signal (output). Cell Inlet Flag Active high positive cell receipt acknowledge (ACK) UTOPIA, 16-Bit, Back-to-Back modes. RFlush ALI-25 mode. Cell Inlet Flag used UTOPIA, 16-Bit Back-to-Back modes. RFlshd ALI-25 mode.
CIF1/ RFlush CIF2/RFlsh CIF3
Cell Inlet Flag Active high cell rejection indication (NACK) UTOPIA, 16-Bit Back-to-Back modes. Disregard ALI25 mode. Cell Inlet Flag EInt ALI-25 mode. Cell Inlet Start Cell: Start-of-Cell indication UTOPIA 16-Bit modes. RDPrty parity ALI-25 mode. (Note: Parity output ALI-25 device ignored CUBIT-Pro).
CIF4/EInt CISOC/ RDPrty
Input, Output Parameters section Type definitions. Signals which active when upon their falling edges shown negated (overlined).
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CUBIT-Pro TXC-05802
CELL OUTLET Symbol COCLAV/ TdVal I/O/P Type Name/Function
TTL/ Cell Outlet Cell Available: direction COCLAV signal depends mode selected: ALayer emulation: active high input from layer device indicate that accept transfer complete cell. This applies UTOPIA 16-Bit modes Layer emulation: active high output that CUBIT-Pro asserts indicate that transfer complete cell Alayer device. This applies UTOPIA 16-Bit modes. Back-to-Back mode: COCLAV active high output signal. ALI-25 mode: TdVal signal (output). TTL/ Cell Outlet Clock: Transfer clock. Rising edge COCLK used data transfer. ALayer emulation: This output clock. This applies UTOPIA 16-Bit modes. Layer emulation: This input clock. This applies UTOPIA, Back-to-Back, 16-Bit modes. ALI-25 mode: TBClk signal (input). Maximum clock speed with 40/60 duty cycle. Cell Outlet Data: Byte-parallel output data. TData(7-0) output ALI-25 mode.
COCLK/ TBClk
COD(7-6) COD(5-4) COD(3-2) COD(1-0)/ TData(7-0) COENB/ TLoad
180, 181, 183, 184, 186, 187, 189,
TTL/ Cell Outlet Enable: active enable signal which occurs during clock cycles when COD(7-0) data and/or COSOC active. ALayer emulation: active output signal. This applies UTOPIA 16-Bit modes. Layer emulation: active input signal. This applies UTOPIA 16-Bit modes. Back-to-Back mode: COENB active input signal. ALI-25 mode: TLoad signal (input). Cell Outlet Start Cell: Start-of-Cell UTOPIA 16-Bit modes. TDPrty parity output ALI-25 mode. TTLp TTLp Generic Flow Control: Inlet nibble inserted cell outlet. Force Congestion: Active high signal force congestion indication cells received.
COSOC/ TDPrty GFC(3-2) GFC(1-0) FRCABRCNG
198, 199, 201,
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CUBIT-Pro TXC-05802
Symbol LCLOCK
I/O/P
Type TTLp
Name/Function Line Clock: Rising edge used data transfer. This clock input used cell Inlet/Outlet timing assuming that CLKS1,CLKS0=1,0 register 0BH.
CellBus PORT Symbol CBACK CBCONG CBD(31-24) CBD(23-16) CBD(15-8) CBD(7-0) CBRC CBWC CONGOUT 112, 110, 109, 107, 103, 101, 100, I/O/P Type CellBus Frame: 16-clock cycle structure. CellBus Read Clock: Accepts data from bus. Falling edge used data transfer. CellBus Write Clock: Puts data bus. Falling edge used data transfer. CellBus Congestion: EBP=1, indicates congestion impending congestion detected after CUBIT-Pro sends cell CellBus bus. This indication provided UTOPIA, 16-Bit Back-to-Back Modes. EBP=0 this signal GTL-to-CMOS translation CellBus signal CBCONG. CellBus Disable: Active signal tristate entire CellBus regardless state VDD3 VDD5 power supplies. (This signal part CellBus bus.) Name/Function CellBus Acknowledge: Active acknowledge. CellBus Congestion Indicator: Active congestion indicator. CellBus Data: Active 32-bit parallel data input/output bus.
CBDISABLE
CMOS
VREF
Reference VREF: Reference voltage receivers. Voltage VREF approximately Vtt, where backplane termination voltage (nominally +1.2V). input connection this part CellBus bus.
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CUBIT-Pro TXC-05802
MICROPROCESSOR PORT Symbol A(7-6) A(5-4) A(3-0) D(7-6) D(5-2) D(1-0) INT/IRQ MOTO PCLK RD/WR RDY/DTACK 16-19 24-27, I/O/P Type Name/Function Address Bus: 8-bit address lines from microprocessor, used address CUBIT-Pro register memory. LSB. High logic
TTL/ Data Bus: Bidirectional 8-bit data lines used transferTTL ring data from microprocessor. LSB. High logic Interrupt: Active high Intel, active Motorola. Motorola Mode: Select Motorola operation high, Intel low. Processor Clock: Rising edge used data transfer. Read/Write: Data transfer command CUBIT-Pro memory. Read (low) Intel. Read (high) Write (low) Motorola.
Ready Data Transfer Acknowledge: Active high Ready Intel, active Data Transfer Acknowledge Motorola. This output open-drain buffer which requires external pull-up resistor. Select: Active signal enable data transfer. Write: Active write command transferring data CUBIT-Pro memory Intel mode. This input must held high Motorola mode.
TRANSLATION ACCESS PORT Symbol TRA(17-16) TRA(15-12) TRA(11-8) TRA(7-4) TRA(3-0) (7-4) (3-0) TROE TRWE 150, 152, 160-163, 165-168, 170-173, 175-178 140-143, 145-148 I/O/P Type Name/Function
Translation Address Bus: 18-bit address output 256k byte Translation RAM. TRA(7-0) cell data outlet ABRENA enabled. TRA0 LSB. High logic TTL/ Translation Data Bus: Bidirectional 8-bit data bus. TRD(7-0) cell data inlet ABRENA enabled. TRD0 LSB. High logic Translation Output Enable: Active output enable. Translation Write Enable: Active write enable.
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CUBIT-Pro TXC-05802
CONTROL STRAPS Symbol* ABRENA I/O/P Type TTLp Name/Function 16-Bit Mode Enable: Active signal select 16-Bit operating mode. additional data bits carried TRD(7-0) acting cell data inlet TRA(7-0) acting cell data outlet. Device High Impedance: Active signal outputs high-impedance (Hi-Z) state. Enable Arbiter: Active signal enable internal copy Arbiter Frame Pulse Generator. Operating Mode: Three active signals selection CUBIT-Pro cell Inlet/Outlet operating mode. Please Figures 6-9, details. Translation Enable: active signal enable header translation CUBIT-Pro. Unit Address: Five active device identity straps, used identify each CUBIT-Pro device system containing devices. Unit Control strap setting maximum number CUBIT-Pros that connected CellBus bus. CUBIT-Pros, high floating) Layer Enable: enables Layer emulation UTOPIA 16-Bit modes
DEVHIZ ENARB LMODE2 LMODE1 LMODE0 TRAN UA(4-0)
156, 157,
TTLp TTLp TTLp
TTLp TTLp
TTLp
PHYEN
TTLp
Note: control straps active inputs. They pulled internally will inactive left unconnected. They must enable associated function.
RESET TEST PINS Symbol RESET TSTMODE SCAN1 SCAN2 TSTOUT TESTIN I/O/P Type -Name/Function Reset: Active device reset (minimum duration nanoseconds). Test Mode: Active signal enable device test manufacturer. DD5. Scan Internal test function. VSS. Scan Internal test function. VSS. Internal Test Pin: Leave floating. Internal Test Mode Input: VDD5.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802 ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage, Supply voltage, +3.3V input voltage Storage temperature range Component Temperature Time Ambient operating temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit Classification Symbol VDD5 VDD3 ±2000 -0.3 -0.3 -0.3 +7.0 +6.0 VDD5 +0.3 +150 +270
Unit
Conditions Note Note Note Note Note ft/min linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing MIL-STD-883D Method 3015.7
Level
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied.
THERMAL CHARACTERISTICS
Parameter Thermal resistance junction ambient 29.5 Unit
Test Conditions ft/min linear airflow
POWER REQUIREMENTS
Parameter VDD5 IDD5 PDD5 VDD3 IDD3 PDD3 VDDBOOT IDDBOOT PDDBOOT PTOTAL 4.75 3.14 4.75 5.00 3.30 5.00 0.01 0.05 5.25 3.46 1000 5.25 0.10 0.525 1250 Unit Note Note Notes Notes Notes Notes Notes Test Conditions
Notes: Typical values based measurements made with nominal voltages, ambient, UTOPIA CellBus clocks. values dependent upon operation.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802 INPUT, OUTPUT PARAMETERS
INPUT PARAMETERS CMOS Parameter Input leakage current Input capacitance INPUT PARAMETERS Parameter Input leakage current Input capacitance Unit Test Conditions 4.75 5.25 4.75 5.25 VDD5 VDD5 Unit Test Conditions 4.75 5.25 4.75 5.25
INPUT PARAMETERS TTLp (TTL WITH INTERNAL PULL-UP) Parameter Input current Input leakage current Input capacitance OUTPUT PARAMETERS Parameter Tri-state leakage current -4.0 Unit Test Conditions -4.0 -115 -214 Unit Test Conditions 4.75 5.25 4.75 5.25 VIN=VSS VIN=VDD5
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CUBIT-Pro TXC-05802
OUTPUT PARAMETERS (OPEN-DRAIN) Parameter Unit Test Conditions VDD=4.75; IOL=
Note: Open Drain requires external pull-up resistor VDD5. this resistor provided output behaves tri-state.
OUTPUT PARAMETERS Parameter Tri-state leakage current OUTPUT PARAMETERS Parameter Tri-state leakage current INPUT/OUTPUT PARAMETERS Parameter Input leakage current Input capacitance Tri-state leakage current 0.86 0.66 Unit Test Conditions 4.75 5.25 4.75 5.25 5.25 -8.0 Unit Test Conditions -8.0 -6.0 Unit Test Conditions -6.0
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CUBIT-Pro TXC-05802
INPUT/OUTPUT PARAMETERS TTL/TTL Parameter Input leakage current Input capacitance INPUT/OUTPUT PARAMETERS TTL/TTL Parameter Input leakage current Input capacitance INPUT/OUTPUT PARAMETERS TTL/TTL Parameter Input leakage current Input capacitance -8.0 Unit 4.75; -8.0 4.75; Test Conditions 4.75 5.25 4.75 5.25 5.25 -6.0 Unit 4.75; -6.0 4.75; Test Conditions 4.75 5.25 4.75 5.25 5.25 -4.0 Unit 4.75; -4.0 4.75; Test Conditions 4.75 5.25 4.75 5.25 5.25
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802 TIMING CHARACTERISTICS
Detailed timing diagrams CUBIT-Pro device provided Figures through with values timing intervals given tables below waveform drawings. output times measured with maximum load capacitance unless otherwise indicated. Timing parameters measured voltage levels (VIH+VIL)/2 input signals (VOH+VOL)/2 output signals. DUTY CYCLE INPUT CLOCK SIGNALS duty cycle input clock signals defined ratio duration high pulse clock signal period, express percentage. required duty cycle values defined following table: Input Clock Symbol CICLK PCLK COCLK LCLOCK CBRC CBWC Input Clock Duty Cycle Unit
FREQUENCY INPUT CLOCK SIGNALS required frequency values defined following table: Input Clock Symbol CICLK PCLK COCLK LCLOCK CBRC CBWC Input Clock Frequency Unit
CONTROL TRANSLATION INTERFACE timing translation interface referenced appropriate clock selection cell inlet clock. Therefore, timing shown Figures shows timings with respect four different clocks: CBWC: CLKS[1:0] UTOPIA/16-Bit (ALayer), Back-to-Back, ALI-25 modes LCLOCK: CLKS[1:0] UTOPIA/16-Bit (ALayer), Back-to-Back, ALI-25 modes PCLK: CLKS[1:0] UTOPIA/16-Bit (ALayer), Back-to-Back, ALI-25 modes CICLK: PHYEN only UTOPIA/16-Bit (PHY Layer) TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Figure Translation Timing Read from
CICLK (Input) PCLK (Input) LCLOCK (Input) CBWC (Input)
tD(1d)
tD(1a) tD(2a) tD(1b) tD(2b) tD(1c) tD(2c)
tSU(1a)
tH(1a)
tSU(1b)
tH(1b)
tSU(1c)
tH(1c)
TROE (Output)
tD(2d)
TRA(17-0) (Output)
tSU(1d)
TRD(7-0) (Input)
Data Valid
Data Valid
Data Valid
tH(1d)
Microprocessordirected read cycle from
Translation read cycle
Parameter TROE output delay after CICLK (PHY Mode) TROE output delay after PCLK TROE output delay after LCLOCK TROE output delay after CBWC TRA(17-0) output delay after CICLK TRA(17-0) output delay after PCLK TRA(17-0) output delay after LCLOCK TRA(17-0) output delay after CBWC TRD(7-0) setup time before CICLK TRD(7-0) setup time before PCLK TRD(7-0) setup time before LCLOCK TRD(7-0) setup time before CBWC TRD(7-0) hold time after CICLK TRD(7-0) hold time after PCLK TRD(7-0) hold time after LCLOCK TRD(7-0) hold time after CBWC
Symbol tD(1a) tD(1b) tD(1c) tD(1d) tD(2a) tD(2b) tD(2c) tD(2d) tSU(1a) tSU(1b) tSU(1c) tSU(1d) tH(1a) tH(1b) tH(1c) tH(1d)
Unit
Note: TRWE output high. timing parameter values apply both Microprocessor Translation read cycles.
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CUBIT-Pro TXC-05802
Figure Translation Timing Write
CICLK (Input) PCLK (Input) LCLOCK (Input) CBWC (Input) TRD(7-0) (Output) TRA(17-0) (Output) TROE (Output) TRWE (Output)
Read Cycle Microprocessor-directed Write Cycle tD(2a) tD(1a) tD(3a) tD(1b) tD(3b) tD(1c) tD(3c) tD(1d) tD(2d) tZ(1c)
tZ(1a)
tD(2b)
tZ(1b)
tD(2c)
tZ(1d)
tD(3d)
Parameter TRD(7-0) delay from tri-state after CICLK TRD(7-0) delay from tri-state after PCLK TRD(7-0) delay from tri-state after LCLOCK TRD(7-0) delay from tri-state after CBWC TRD(7-0) delay tri-state after CICLK TRD(7-0) delay tri-state after PCLK TRD(7-0) delay tri-state after LCLOCK TRD(7-0) delay tri-state after CBWC TRA(17-0) delay after CICLK TRA(17-0) delay after PCLK TRA(17-0) delay after LCLOCK TRA(17-0) delay after CBWC TRWE delay after CICLK TRWE delay after PCLK TRWE delay after LCLOCK TRWE delay after CBWC
Symbol tD(1a) tD(1b) tD(1c) tD(1d) tZ(1a) tZ(1b) tZ(1c) tZ(1d) tD(2a) tD(2b) tD(2c) tD(2d) tD(3a) tD(3b) tD(3c) tD(3d)
Unit
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CUBIT-Pro TXC-05802
CELL INTERFACE Note: cell interface timing diagrams, payload bytes cell labelled through P47. This consistent with Figures which describe byte/word ordering four cell interface modes. Cell Inlet, UTOPIA Mode ALayer Emulation Timing (Receive UTOPIA Interface Timing) Figure Timing UTOPIA (ALayer Emulation) Cell Inlet Interface
CICLK (Output) CICLAV (Input) CIENB (Output)
tSU(1)
tH(1)
tD(1)
tD(1)
Case there back-to-back cells (dashed lines above) CID(7-0) (Input)
tSU(2)
tSU(3)
tH(3) tH(2)
CISOC (Input) Case FIFO full (solid lines above) CID(7-0) (Input)
tSU(2)
tSU(3)
tH(3) tH(2)
CISOC (Input)
Parameter CICLAV setup time before CICLK CICLAV hold time after CICLK CIENB delay after CICLK CISOC setup time before CICLK CISOC hold time after CICLK CID(7-0) setup time before CICLK CID(7-0) hold time after CICLK
Symbol tSU(1) tH(1) tD(1) tSU(2) tH(2) tSU(3) tH(3)
10.5 10.0
Unit
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CUBIT-Pro TXC-05802
Layer Emulation Timing (Transmit UTOPIA Interface Timing) Figure Timing UTOPIA (PHY Layer Emulation) Cell Inlet Interface
CICLK (Input) CICLAV (Output) CIENB (Input)
tH(1)
tD(1)
tSU(1)
Case there back-to-back cells (dashed lines above) CID(7-0) (Input) CISOC (Input)
tH(2)
tSU(3)
tSU(2)
tH(3)
Case FIFO full (solid lines above) CID(7-0) (Input) CISOC (Input)
tSU(3)
tSU(2) tH(2)
tH(3)
Parameter CICLAV delay from CICLK CIENB setup time before CICLK CIENB hold time after CICLK CISOC setup time before CICLK CISOC hold time after CICLK CID(7-0) setup time before CICLK CID(7-0) hold time after CICLK
Symbol tD(1) tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3)
Unit
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CUBIT-Pro TXC-05802
Cell Outlet, UTOPIA Mode ALayer Emulation Timing (Transmit UTOPIA Interface Timing) Figure Timing UTOPIA (ALayer Emulation) Cell Outlet Interface
COCLK (Output)
tSU(1) tH(1)
COCLAV (Input) COENB (Output)
tD(1)
Case COCLAV solid line, cell
COD(7-0) (Output)
tD(2)
Case COCLAV dotted line, consecutive cells
COD(7-0) (Output) COSOC (Output)
tD(3)
Parameter COCLAV setup time before COCLK COCLAV hold time after COCLK COENB delay after COCLK COD(7-0) delay after COCLK COSOC delay after COCLK
Symbol tSU(1) tH(1) tD(1) tD(2) tD(3)
Unit
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CUBIT-Pro TXC-05802
Layer Emulation Timing (Receive UTOPIA Interface Timing) Figure Timing UTOPIA (PHY Layer Emulation) Cell Outlet Interface
COCLK (Input) COCLAV (Output)
tD(1)
tH(1)
COENB (Input)
tSU(1)
Case COCLAV solid line, cell
COD(7-0)* (Output)
tD(2)
Case COCLAV dotted line, consecutive cells
COD(7-0)* (Output)
COSOC* (Output)
tD(3)
Note: COD(7-0) COSOC outputs tri-stated COENB input changed high.
Parameter COCLAV delay after COCLK COENB setup time before COCLK COENB hold time after COCLK COD(7-0) delay after COCLK COSOC delay after COCLK
Symbol tD(1) tSU(1) tH(1) tD(2) tD(3)
Unit
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CUBIT-Pro TXC-05802
Cell Inlet, 16-Bit Cell Interface Mode ALayer Emulation Timing (Receive UTOPIA Interface Timing) Figure Timing 16-Bit (ALayer Emulation) Cell Inlet Interface
CICLK (Output) CICLAV (Input) CIENB (Output)
tSU(1)
tH(1)
tD(1)
tD(1)
Case there back-to-back cells (dashed lines above) TRD(7-0) (Input) CID(7-0) (Input) CISOC (Input) Case FIFO full (solid lines above) TRD(7-0) (Input) CID(7-0) (Input) CISOC (Input)
tSU(4)
tH(4)
tSU(3)
tSU(2)
tH(3) tH(2)
tSU(4)
tH(4) tSU(3)
tSU(2)
tH(3) tH(2)
Parameter CICLAV setup time before CICLK CICLAV hold time after CICLK CIENB delay after CICLK CISOC setup time before CICLK CISOC hold time after CICLK CID(7-0) setup time before CICLK CID(7-0) hold time after CICLK TRD(7-0) setup time before CICLK TRD(7-0) hold time after CICLK
Symbol tSU(1) tH(1) tD(1) tSU(2) tH(2) tSU(3) tH(3) tSU(4) tH(4)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Layer Emulation Timing (Transmit UTOPIA Interface Timing) Figure Timing 16-Bit (PHY Layer Emulation) Cell Inlet Interface
CICLK (Input) CICLAV (Output)
tH(1)
tD(1)
tSU(1)
CIENB (Input) Case there back-to-back cells (dashed lines above) TRD(7-0) (Input)
tSU(4)
tH(4) tSU(3)
CID(7-0) (Input) CISOC (Input)
tSU(2)
tH(3)
tH(2)
Case FIFO full (solid lines above) TRD(7-0) (Input) CID(7-0) (Input)
tSU(2)
tSU(4)
tH(4) tSU(3)
tH(3)
CISOC (Input)
tH(2)
Parameter CICLAV delay from CICLK CIENB setup time before CICLK CIENB hold time after CICLK CISOC setup time before CICLK CISOC hold time after CICLK CID(7-0) setup time before CICLK CID(7-0) hold time after CICLK TRD(7-0) setup time before CICLK TRD(7-0) hold time after CICLK
Symbol tD(1) tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tSU(4) tH(4)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Cell Outlet, 16-Bit Cell Interface Mode ALayer Emulation Timing (Transmit UTOPIA Interface Timing) Figure Timing 16-Bit (ALayer Emulation) Cell Outlet Interface
COCLK (Output)
tSU(1) tH(1)
COCLAV (Input) COENB (Output)
tD(1)
Case COCLAV solid line, cell
tD(4)
TRA(7-0) (Output) COD(7-0) (Output)
tD(3)
Case COCLAV dotted line, consecutive cells
tD(4)
TRA(7-0) (Output) COD(7-0) (Output) COSOC (Output)
tD(2)
tD(3)
Parameter COCLAV setup time before COCLK COCLAV hold time after COCLK COENB delay after COCLK COSOC delay after COCLK COD(7-0) delay after COCLK TRA(7-0) delay after COCLK
Symbol tSU(1) tH(1) tD(1) tD(2) tD(3) tD(4)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Layer Emulation Timing (Receive UTOPIA Interface Timing) Figure Timing 16-Bit (PHY Layer Emulation) Cell Outlet Interface
COCLK (Input) COCLAV (Output)
tD(1)
tH(1)
COENB (Input)
Case COCLAV solid line, cell
TRA(7-0)* (Output) COD(7-0)* (Output)
tD(4)
tSU(1)
tD(3)
Case COCLAV dotted line, consecutive cells
tD(4)
TRA(7-0)* (Output) COD(7-0)* (Output) COSOC* (Output)
tD(2)
tD(3)
Note: TRA(7-0), COD(7-0) COSOC outputs tri-stated COENB input changed high.
Parameter COCLAV delay after COCLK COENB setup time before COCLK COENB hold time after COCLK COSOC delay after COCLK COD(7-0) delay after COCLK TRA(7-0) delay after COCLK
Symbol tD(1) tSU(1) tH(1) tD(2) tD(3) tD(4)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Cell Inlet, ALI-25 Mode Figure Timing ALI-25 Cell Receive Interface
CICLK/RBClk
(Output) tSU(1) tH(1) tH(1)
CICLAV/RDVal
(Input) tD(1) tD(1) tD(1)
CIENB/RLoad
(Output) tSU(2)
CID(7-0)/RData(7-0)
(Input)
tH(2) tD(2)
CIF1/RFlush
(Output) tSU(3)
CIF2/RFlshD
(Input) tSU(4) tH(3) tH(4)
CIF4/EInt
(Input) FIFO Flush Sequence
Parameter CICLAV setup time before CICLK CICLAV hold time after CICLK CIENB delay after CICLK CID(7-0) setup time before CICLK CID(7-0) hold time after CICLK CIF1 delay after CICLK CIF2 setup time before CICLK CIF2 hold time after CICLK CIF4 setup time before CICLK CIF4 hold time after CICLK
Symbol tSU(1) tH(1) tD(1) tSU(2) tH(2) tD(2) tSU(3) tH(3) tSU(4) tH(4)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Cell Outlet, ALI-25 Mode Figure Timing ALI-25 Cell Transmit Interface
COCLK/TBClk
(Input) tD(1)
COCLAV/TDVal
(Output) tD(1) tSU(1) tH(1)
COENB/TLoad
(Input) tD(2)
COD(7-0)/TData(7-0) (Output)
tD(3)
COSOC/TDPrty (Output)
Parameter COCLAV delay after COCLK COENB setup time before COCLK COENB hold time after COCLK COD(7-0) delay after COCLK COSOC delay after COCLK
Symbol tD(1) tSU(1) tH(1) tD(2) tD(3)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Cell Inlet, Back-to-Back Mode
Figure Timing Back-to-Back Cell Receive Interface
CICLK (Output) CICLAV (Input) CIENB (Output) CID(7-0) (Input) CISOC (Input)
tSU(2)
tSU(1) tD(1)
tH(1)
tSU(3)
tH(3)
tH(2)
Parameter CICLAV setup time before CICLK CICLAV hold time after CICLK CIENB delay after CICLK CID(7-0) setup time before CICLK CID(7-0) hold time after CICLK CISOC setup time before CICLK CISOC hold time after CICLK
Symbol tSU(1) tH(1) tD(1) tSU(2) tH(2) tSU(3) tH(3)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Cell Outlet, Back-to-Back Mode Figure Timing Back-to-Back Cell Transmit Interface
COCLK (Input)
tD(1)
COCLAV (Output)
tSU(1)
tD(1)
COENB (Input)
tD(2)
tH(1)
COD(7-0) (Output) COSOC (Output)
tD(3)
Parameter COCLAV delay after COCLK COENB setup time before COCLK COENB hold time after COCLK COD(7-0) delay after COCLK COSOC delay after COCLK
Symbol tD(1) tSU(1) tH(1) tD(2) tD(3)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Field Insertion Figure Field Insertion Timing
COCLK (Input Output)*
COD(7-0) (Output)
tSU(1)
GFC(3-0) (Input)
tH(1)
Note: Output signal UTOPIA 16-Bit ALayer emulation modes. Input signal UTOPIA 16-Bit Layer emulation modes, Back-to-Back mode ALI-25 mode.
Parameter GFC(3-0) setup time before COCLK GFC(3-0) hold time after COCLK
Symbol tSU(1) tH(1)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
CellBus Port Figure CellBus Timing
CBRC (Input) Data inputs from
CBD(31-0) CBACK CBCONG tSU(1)
tH(1)
CBWC (Input) Data outputs
CBD(31-0) CBACK CBCONG tD(1)
Parameter CellBus inputs setup time before CBRC CellBus inputs hold time after CBRC CellBus outputs delay after CBWC
Note:
Symbol tSU(1) tH(1) tD(1)
Unit
note
CUBIT-Pro CellBus write clock CellBus data time delay complex highly dependent loading. minimum value delay tD(1) time after CBWC going which data output value does change. This shown table guaranteed design inside CUBIT-Pro. maximum value (over voltage, temperature process ranges) tD(1) 15.8 low-to-high, 14.1 high-to-low minimum load consisting resistor +1.2 volts capacitor ground. These output delay numbers have components, internal delay output delay. With real system load, value driver output delay CUBIT-Pro VLSI chip will depend external circuitry: chip package effects, printed circuit boards both ends, connectors, backplane traces. in-circuit value delay then must derived adding delays arising from these external effects internal delay. TranSwitch strongly recommends that CellBus applications analyzed analog circuit simulation, using such tools HSpice®. TranSwitch provide HSpice model CUBIT-Pro transceiver. When doing such modeling, CUBITPro data delay time divided into parts: internal delay time from CBWC input (internal) driver input, driver delay. minimum maximum values CUBIT-Pro internal delay driver) respectively. general, these simulations model timing from CUBIT-Pro, through various levels system interconnect, another CUBIT-Pro. Models generally include effects device package, printed circuit board connectors, backplane. This level simulation very effectively model system performance. actual value delay from CUBIT-Pro CBWC input point modeled simulation simulation delay CUBIT-Pro internal delay. Applications with backplanes inches wide having clock speeds more than have proven work well with good basic design. most part, this means keeping significant copper wiring traces short: those from backplane connector CUBIT-Pro, those from CellBus ends pull-up resistors. Grounding similarly important performance, with working assumption being that backplane plug-in cards full planes power ground, maintain very ground supply inductance. clocks this case bussed across backplane cards driven point Texas Instruments SN74GTL1655, equivalent. clock line pull-ups ohms each end. delay from CBWC CBRC maintained, analog delay line clock source point, value between Please contact TranSwitch Applications Engineering Department additional information support. HSpice registered trademark Meta-Software, Inc.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Figure CellBus Frame Position, 16-User 32-User Applications
CBRC (Input) CBWC (Input) CBF*
(U32 VDD5, 16-user)
CBF*
(U32 VSS, 32-user)
*Note: Output from CUBIT-Pro that selected perform arbitration function. Input other CUBIT-Pros CellBus bus.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Microprocessor Interface Intel Mode: Read Cycle Figure Intel Microprocessor Read Cycle Timing
A(7-0) (Input)
D(7-0) (Output)
tD(1) tSU(1)
(Input)
tSU(2) tH(1)
(Input)
tH(2) tD(2)
(Output) (Note
tPW(1)
Parameter A(7-0) setup time D(7-0) valid delay after D(7-0) float time tri-state after setup time hold time after hold time after delay after pulse width
Symbol tSU(1) tD(1) tSU(2) tH(1) tH(2) tD(2) tPW(1)
Unit
Note
Note CUBIT-Pro will hold microprocessor period periods CellBus bus, LCLOCK PCLK clock selected settings control bits CLKS1 CLKS0 (bits register 0BH). This occurs only during accesses external Translation RAM. Note open drain output signal that requires pull-up resistor VDD5 proper operation.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Intel Mode: Write Cycle Figure Intel Microprocessor Write Cycle Timing
A(7-0) (Input)
tSU(2) tH(1)
D(7-0) (Input)
tSU(1)
(Input)
tSU(3)
(Input)
tD(1) tH(2)
(Output) (Note
tPW(1)
Parameter A(7-0) setup time D(7-0) hold time after hold after D(7-0) valid setup time setup time delay after pulse width
Symbol tSU(2) tH(1) tH(2) tSU(1) tSU(3) tD(1) tPW(1)
Unit
Note
Note CUBIT-Pro will hold microprocessor period periods CellBus bus, LCLOCK PCLK clock selected settings control bits CLKS1 CLKS0 (bits register 0BH). This occurs only during accesses external Translation RAM. Note open drain output signal that requires pull-up resistor VDD5 proper operation.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Motorola Mode: Read Cycle Figure Motorola Microprocessor Read Cycle Timing
A(7-0) (Input)
D(7-0) (Output)
tSU(1) tH(1)
(Input)
tSU(2)
RD/WR (Input)
tD(1) tH(2)
DTACK (Output)
tD(2)
Parameter A(7-0) valid setup time D(7-0) hold time after D(7-0) output delay after DTACK hold time after DTACK RD/WR setup time DTACK delay time from DTACK float time after
Symbol tSU(1) tH(1) tD(1) tH(2) tSU(2) tD(2)
Unit
2*PCLK Note
Note CUBIT-Pro will hold microprocessor period periods CellBus bus, LCLOCK PCLK clock selected settings control bits CLKS1 CLKS0 (bits register 0BH). This occurs only during accesses external Translation RAM.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Motorola Mode: Write Cycle Figure Motorola Microprocessor Write Cycle Timing
A(7-0) (Input)
tSU(2)
D(7-0) (Input)
tSU(1) tH(1)
tH(2)
(Input)
tSU(3)
RD/WR (Input)
DTACK (Output)
tD(1)
Parameter A(7-0) valid setup time D(7-0) valid setup time D(7-0) hold time after hold time after DTACK RD/WR setup time delay after DTACK float time after
Symbol tSU(2) tSU(1) tH(1) tH(2) tSU(3) tD(1)
Note
Unit
Note
Notes: cycles clock PCLK. CUBIT-Pro will hold microprocessor period periods CellBus bus, LCLOCK PCLK clock selected settings control bits CLKS1 CLKS0 (bits register 0BH). This occurs only during accesses external Translation RAM.
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Microprocessor Interrupt Generation Figure Microprocessor Interrupt Timing
PCLK (Input)
tD(1)
Intel Interface: (Output) Motorola Interface: (Output)
Parameter INT/IRQ delay after PCLK
Symbol tD(1)
Unit
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802 MEMORY
Address Mode* (Hex) Reserved** TRAL(7-0) TRAU(7-0) TRADATA(7-0) VRPS1 VRPS0 NOTIGN CRCF INTEN7 ONLINE CRQOVF CRQCAV INTEN6 TRHIZ INTEN5 CLKS1
Mask Mask Mask Mask CTNAK CTACK Reserved** Reserved** Reserved** INSOC INTEN4 TRHENA CLKS0
Reserved**
Reserved** BIP-8 CBLOF CBLORC CBLOWC RESET CTSENT INTEN3 NOGRT INTEN2
Reserved** Reserved**
INTENA7 INTENA6
INTENA3 INTENA2 INTENA1 INTENA0 OCOVF INTEN0 CRQSENT IFECN MRCIN CRC4EN CBRLEN(6-0) CBRLIMIT(6-0) VBRLIMIT(6-0)
OAMRMEN
Reserved**
CTRDY LINEDIV GFCENA
Reserved**
Reserved** Reserved** CRC4I
Reserved**
TIME(7-0)
LBADDRL(7-0) LBADDRU(3-0)
Read-Only; Write-Only; Read Clear (individual bits remain their causative condition persists); Read/Write. Note: Reserved addresses should accessed microprocessor. Reserved positions within used addresses contain random values; writable addresses, these bits should
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Address Mode* (Hex) 25-5F 61-92 94-9F A1-D6 D8-DF E1-FE
16BMODE 32USER
DISCCTR(7-0) MRCCTR(7-0) HECERCTR(7-0) INCELLL(7-0) (Lower Byte) INCELLM(7-0) (Middle Byte) INCELLU(7-0) (Upper Byte) MASTER Reserved** MRCHEAD0(7-0) MRCHEAD1(7-0) MRCHEAD2(7-0) MRCHEAD3(7-0) Reserved** Reserved** CRQ0(7-0) CRQ1(7-0) (61H) through CRQ50(7-0) (92H) CRQ51(7-0) Reserved** CTQ0(7-0) CTQ1(7-0) (A1H) through CTQ54(7-0) (D6H) CTQ55(7-0) Reserved** MCASTN00(7-0) MCASTN01(7-0) (E1H) through MCASTN1E(7-0) (FEH) MCASTN1F(7-0) TRAMSB(1-0) CUBIT-ID(4-0)
Read-Only; Read/Write; Register. Note: Reserved addresses should accessed microprocessor. Reserved positions within used addresses contain random values; writable addresses, these bits should
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802 MEMORY DESCRIPTIONS
DEVICE DESCRIPTOR RESET BITS Address 00-02 -RESET Symbol DEVID Description Device identification code bits). Version number. Mask revision level. Reserved bits. Reserved bits. When this clears counters DISCCTR, MRCCTR, HECERCTR INCELL addresses through 1DH. This clears automatically.
addresses memory description tables hexadecimal. Reserved addresses listed.
STATUS INTERRUPT-ENABLE BITS Address Symbol CTNAK CTACK -BIP-8 Description microprocessor control cell sent CUBIT-Pro accepted destination microprocessor control cell sent CUBIT-Pro accepted destination Reserved bits. when BIP-8 error detected receiver. will generate microprocessor interrupt (INTENA3) interrupt enable location address 06H. CellBus frame pulse present consecutive frame pulse times (U32 low) four consecutive frame pulse times (U32 high). CellBus read clock present more than equivalent PCLK cycles. CellBus write clock present more than equivalent PCLK cycles. Interrupt enabled CTNAK, Interrupt enabled CTACK, Reserved bits. Interrupt enabled BIP-8, Interrupt enabled CBLOF, Interrupt enabled CBLORC, Interrupt enabled CBLOWC,
CBLOF
CBLORC CBLOWC INTENA7 INTENA6 -INTENA3 INTENA2 INTENA1 INTENA0
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Address
Symbol CRCF CRQOVF CRQCAV INSOC CTSENT NOGRT
Description indicate check error cell from CellBus bus. indicate loss incoming control cell, overflow internal 4-cell control cell receive queue. indicate that control cell present control cell receive queue, CRQ. indicate cell inlet Start-of-Cell error occurrence. indicate that control cell been sent CellBus from control cell transmit buffer. indicate that access grant been received inlet side, after access request, within time established register TIME. Reserved bit. indicate cell discarded overflow outlet FIFO. Interrupt enabled CRCF, Interrupt enabled CRQOVF, Interrupt enabled CRQCAV, Interrupt enabled INSOC, Interrupt enabled CTSENT, Interrupt enabled NOGRT, Reserved bit. Interrupt enabled OCOVF, ABRENA high. indicates that CUBIT-Pro operated 16-Bit mode. high. indicates that CUBIT-Pro operated 32-user mode. ENARB high. indicates that CUBIT- master arbiter CellBus bus. Contains address pins UA(4-0). These states detected power-up UA(4-0) inputs change state. example, CUBIT-ID UA(4-0) pins high.
-OCOVF INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 -INTEN0 16BMODE 32USER MASTER CUBIT-ID (4-0)
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
DEVICE MODE CONTROL BITS Address Symbol Description access priority this CUBIT-Pro device. Possible values are: high-priority, P1=1, P0=1; medium-priority, P1=1, P0=0; low-priority, P1=0, P0=1; request, P1=0, P0=0. operation, filled width bits. operation, filled width bits. Enable insertion Tandem Routing Header during address translation. Reserved bits. microprocessor indicate that control cell ready sent. Cleared CUBIT-Pro when cell been sent.
TRHENA -CTRDY
CRQSENT microprocessor indicate that control cell been read from CUBIT-Pro's control cell receive buffer. Cleared automatically CUBIT-Pro. -CLKS1 Reserved bits. Clock source selection cell inlet/outlet clock. This works conjunction with CLKS0. coding followed
CLKS1, CLKS0 0,0: Cell interface clock CellBus clock divided 2LINEDIV CLKS1, CLKS0 0,1: Cell interface clock LCLOCK clock divided 2LINEDIV CLKS1, CLKS0 1,0: Cell interface clock PCLK clock divided 2LINEDIV CLKS1, CLKS0 1,1: Reserved,
CLKS0 LINEDIV ONLINE
Clock source selection cell inlet/outlet clock. This works conjunction with CLKS1. Cell inlet clock frequency control. Frequency will equal frequency selected clock source, divided 2-to-the-power-LINEDIV. Operational status. CUBIT-Pro on-line functions operating. CUBIT-Pro off-line. off-line condition, cells accepted from cell inlet, interface outputs tri-stated, only control loopback cells accepted from CellBus bus. Translation interface tri-state bit. When ONLINE translation interface Hi-Z mode. Reserved bits. Outlet cell queue structure. single 123-cell queue QM=0. Split queue (Control Data, CBR, VBR, ABR) Enable insertion state pins GFC(3-0) into field outgoing cells State GFC(3-0) sampled rising edge COCLK that precedes first byte Acell header (see Figure 47). Enable insertion FECN EFCI (middle field) will FIFO length equals exceeds congestion limits, IFECN
TRHIZ GFCENA
IFECN
TXC-05802-MB September 1998
CUBIT-Pro TXC-05802
Address
Symbol -MRCIN VRPS1 Reserved bits.
Description
indicate that misrouted cell been received. Cleared write operation. Records Page Selection conjunction with VRPS0, this selects number records page (VRP) either 256, 512, 1024 128. VRPS1,VRPS0= 0,0: VRPS1,VRPS0= 0,1: VRPS1,VRPS0= 1,0: 1024 VRPS1,VRPS0= 1,1: Records Page Selection conjunction with VRPS1, this selects number records page (VRP) either 256, 512, 1024 128. Ignore translation record I-bit. When connections marked Ibit=1 translation records will treated I-bit=0. CRC
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