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Volt Intel® Wireless Flash Memory
with Volt
28F320W30, 28F640W30, 28F128W30
Product Features
High Performance Read-While-Write/Erase Burst Frequency Initial Access Speed Page-Mode Read Speed Burst-Mode Read Speed Burst Page Mode Blocks across Partition Boundaries Burst Suspend Feature Enhanced Factory Programming: Word Program Time Programmable WAIT Signal Polarity Quality Reliability Operating Temperature: 100K Minimum Erase Cycles 0.13 ETOXVII Process Flash Security 128-bit Protection Register: Unique Device Identifier Bits; User Protection Register Bits Absolute Write Protection with Ground Program Erase Lockout during Power Transitions Individual Instantaneous Block Locking/ Unlocking with Lock-Down
Flash Architecture Multiple 4-Mbit Partitions Dual Operation: Parameter Block Size 4-Kword Main block size 32-Kword Bottom Parameter Devices Flash Software (typ.) Program/Erase Suspend Latency Time Intel® Flash Data Integrator (FDI) Common Flash Interface (CFI) Compatible Flash Power 1.70 1.90 VCCQ 2.20 3.30 Standby Current (typ.) Read Current word burst, typ.) Density Packaging 32-, 64-, 128-Mbit Densities Package Active Ball Matrix, 0.75 Ball-Pitch Packages 16-bit Data
Volt Intel®Wireless Flash Memory with Volt combines state-of-the-art Intel® Flash technology provide most versatile memory solution high performance, power, board constraint memory applications. Volt Intel Wireless Flash Memory with Volt offers multi-partition, dual-operation flash architecture that enables device read from partition while programming erasing another partition. This ReadWhile-Write Read-While-Erase capability makes possible achieve higher data throughput rates compared single partition devices allows processors interleave code execution because program erase operations occur background processes. Volt Intel Wireless Flash Memory with Volt incorporates Enhanced Factory Programming (EFP) mode improve factory programming performance. This feature helps eliminate manufacturing bottlenecks associated with programming high density flash devices. Compare program time word standard factory program time word save significant factory programming time improved factory efficiency. Additionally, Volt Intel Wireless Flash Memory with Volt includes block lock-down, programmable WAIT signal polarity supported array software tools. these features make this product perfect solution demanding memory application.
Notice: This document contains information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
290702-004 April 2002
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Volt Intel® Wireless Flash Memory with Volt contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 2002. *Other names brands claimed property others.
28F320W30, 28F640W30, 28F128W30
Contents
Introduction
Document Purpose Nomenclature.7 Conventions Product Overview.8 Package Diagram Signal Descriptions Memory Partitioning Operations 3.1.1 Read 3.1.2 Burst Suspend 3.1.3 Standby.16 3.1.4 Reset.16 3.1.5 Write.17 Device Commands.17 Command Sequencing Read Array.21 Read Device ID.21 Read Query (CFI) Read Status Register.22 Clear Status Register.24 Word Program.24 Factory Programming Enhanced Factory Program (EFP).27 5.3.1 Requirements Considerations.27 5.3.2 Setup.28 5.3.3 Program 5.3.4 Verify.28 5.3.5 Exit Program/Erase Suspend Resume Block Erase.33 Read-While-Write Read-While-Erase Block Lock Operations 7.1.1 Lock 7.1.2 Unlock
Device Description
Device Operations
Read Operations
Program Operations
Program Erase Operations
Security Modes
28F320W30, 28F640W30, 28F128W30
7.1.3 Lock-Down 7.1.4 Block Lock Status 7.1.5 Lock During Erase Suspend 7.1.6 Status Register Error Checking 7.1.7 Lock-Down Control Protection Register 7.2.1 Reading Protection Register 7.2.2 Programing Protection Register. 7.2.3 Locking Protection Register Protection
Configuration Register
8.10 Read Mode (CR[15]). First Access Latency Count (CR[13:11]) WAIT Signal Polarity (CR[10]) WAIT Signal Function Data Hold (CR[9]) WAIT Delay (CR[8]) Burst Sequence (CR[7]). Clock Edge (CR[6]). Burst Wrap (CR[3]) Burst Length (CR[2:0]). Active Power. Automatic Power Savings (APS) Standby Power Power-Up/Down Characteristics. 9.4.1 System Reset RST# 9.4.2 VCC, VPP, RST# Transitions Power Supply Decoupling. Absolute Maximum Ratings Operating Conditions Current Characteristics Voltage Characteristics. Read Operations Write Characteristics. Erase Program Times. Reset Specifications Test Conditions Device Capacitance
Power Consumption.
10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6
10.0 Thermal Characteristics
11.0 Characteristics
Appendix Appendix
Write State Machine States. Common Flash Interface
28F320W30, 28F640W30, 28F128W30
Appendix Appendix
Mechanical Specifications Ordering Information
28F320W30, 28F640W30, 28F128W30
Revision History
Date Revision 09/19/00 03/14/01 Version -001 -002 Original Version 28F3208W30 product references removed (product discontinued) 28F640W30 product added Revised Table Signal Descriptions (DQ15-0, ADV#, WAIT, S-UB#, S-LB#, VCCQ) Revised Section 3.1, Operations Revised Table Command Definitions, Notes Revised Section 4.2.2, First Latency Count (LC2-0); revised Figure Data Output with Setting Code added Figure First Access Latency Configuration Revised Section 4.2.3, WAIT Signal Polarity (WT) Added Section 4.2.4, WAIT Signal Function Revised Section 4.2.5, Data Output Configuration (DOC) Added Figure Data Output Configuration with WAIT Signal Delay Revised Table Status Register Description Revised entire Section 5.0, Program Erase Voltages Revised entire Section 5.3, Enhanced Factory Programming (EFP) Revised entire Section 8.0, Flash Security Modes Revised entire Section 9.0, Flash Protection Register; added Table Simultaneous Operations Allowed with Protection Register Revised Section 10.1, Power-Up/Down Characteristics Revised Section 11.3, Characteristics. Changed ICCS,ICCWS, ICCES Specs from 21µA; changed ICCR Spec from (burst length Added Figure WAIT Signal Synchronous Non-Read Array Operation Waveform Added Figure WAIT Signal Asynchronous Page-Mode Read Operation Waveform Added Figure WAIT Signal Asynchronous Single-Word Read Operation Waveform Revised Figure Write Waveform Revised Section 12.4, Reset Operations Clarified Section 13.2, SRAM Write Operation, Note Revised Section 14.0, Ordering Information Minor text edits Deleted SRAM Section Added 128M Specifications Added Burst Suspend Added Read While Write Transition Waveforms Various text edits Revised Device Revised Write Speed Various text edits Description
04/05/02
-003
04/24/02
-004
Volt Intel® Wireless Flash Memory with Volt
Introduction
Document Purpose
This datasheet contains information about Volt Intel® Wireless Flash memory with Volt family. Section provides flash memory overview. Section through Section describe memory functionality. Section 10.0 describes electrical specifications extended temperature product offerings. Packaging specifications order information found Appendix Appendix respectively.
Nomenclature
Many acronyms that describe product features usage defined here:
APSAutomatic Power Savings Block Base Address Common Flash Interface Command User Interface Enhanced Factory Programming Flash Data Integrator NCNo Connect One-Time Programmable Partition Base Address Read-While-Erase RWWRead-While-Write SRDStatus Register Data BGAVery thin, Fine pitch, Ball Grid Array WSMWrite State Machine
Conventions
Many abbreviated terms phrases used throughout this document:
term "1.8 refers full voltage range 1.95 (except where noted)
"VPP refers ±5%.
When referring registers, term means logical clear means
logical
terms signal often used interchangeably refer external signal
connections package. (ball term used BGA).
word bytes, bits.
Volt Intel® Wireless Flash Memory with Volt
Signal names CAPS (see Section 2.3, "Signal Descriptions" page 11.) Voltage applied signal subscripted, example, VPP.
Throughout this document, references made top, bottom, parameter, partition. clarify these references, following conventions have been adopted:
block group bits words) that erase simultaneously with block erase
instruction.
main block contains Kwords. parameter block contains Kwords. Block Base Address (BBA) first address block. partition group blocks that share erase program circuitry common status register. Mbit top-parameter device, partition number 140000h.
Partition Base Address (PBA) first address partition. example, partition located highest physical device address. This partition
main partition parameter partition.
bottom partition located lowest physical device address. This partition
main partition parameter partition.
main partition contains only main blocks. parameter partition contains mixture main blocks parameter blocks. parameter device (TPD) parameter partition memory with
parameter blocks that partition. This formerly referred top-boot device.
bottom parameter device (BPD) parameter partition bottom memory
with parameter blocks bottom that partition. This formerly referred bottom-boot block flash device.
Device Description
This section provides overview Volt Intel Wireless Flash memory features, packaging, signal naming, device architecture.
Product Overview
Volt Intel Wireless Flash memory provides Read-While-Write (RWW) Read-WhiteErase (RWE) capability with high-performance synchronous asynchronous reads packagecompatible densities with 16-bit data bus. Individually-erasable memory blocks optimally sized code data storage. Eight 4-Kword parameter blocks located parameter partition either bottom memory map. rest memory array grouped into 32-Kword main blocks.
Volt Intel® Wireless Flash Memory with Volt
memory architecture Volt Intel Wireless Flash memory consists multiple 4-Mbit partitions, exact number depending device density. dividing memory array into partitions, program erase operations take place simultaneously during read operations. Burst reads traverse partition boundaries, user application code responsible ensuring that they don't extend into partition that actively programming erasing. Although each partition burst-read, write, erase capabilities, simultaneous operation limited write erase partition while other partitions read mode. Augmented erase-suspend functionality further enhances capabilities this device. erase suspended perform program read operation within block, except that which erase-suspended. program operation nested within suspended erase subsequently suspended read another memory location. After device power-up reset, Volt Intel Wireless Flash memory defaults asynchronous read configuration. Writing device's configuration register enables synchronous burst-mode read operation. synchronous mode, input increments internal burst address generator. also synchronizes flash memory with host outputs data every, every other, valid cycle after initial latency. programmable WAIT output signals when data from flash memory device ready. addition improved architecture interface, Volt Intel Wireless Flash memory with Volt incorporates Enhanced Factory Programming (EFP), feature that enables fast programming low-power designs. feature provides fastest currently-available program performance, which increase factory's manufacturing throughput. device supports read operations erase program operations With 1.8-V option, tied together simple, ultra-low-power design. addition voltage flexibility, dedicated input provides complete data protection when VPPLK. 128-bit protection register enhances user's ability implement security techniques data protection schemes. Unique flash device identification fraud-, cloning-, contentprotection schemes possible through combination factory-programmed user-OTP data cells. Zero-latency locking/unlocking memory block provides instant complete protection critical system code data. additional block lock-down capability provides hardware protection where software commands alone cannot change block's protection status. device's Command User Interface (CUI) system processor's link internal flash memory operation. valid command sequence written initiates device Write State Machine (WSM) operation that automatically executes algorithms, timings, verifications necessary manage flash memory program erase. internal status register provides ready/ busy indication results operation (success, fail, on). Three power-saving features- Automatic Power Savings (APS), standby, RST#- significantly reduce power consumption. device automatically enters mode following read cycle completion. Standby mode begins when system deselects flash memory de-asserting CE#. Driving RST# produces power savings similar standby mode. also resets part read-array mode (important system-level reset), clears internal status registers, provides additional level flash write protection.
Volt Intel® Wireless Flash Memory with Volt
Package Diagram
Volt Intel® Wireless Flash memory with available active-ball matrix Chip Scale Package with 0.75 ball pitch that ideal board-constrained applications. Figure shows device ballout.
Figure 56-Active-Ball Matrix
VCCQ VSSQ VCCQ VSSQ VSSQ VCCQ VSSQ VCCQ WAIT WAIT ADV# ADV# RST# RST#
View Ball Side Down Complete Mark Shown
Bottom View Ball Side
NOTES: lower density devices, upper address balls treated (Example: 32-Mbit density, A23-21 will NC). Appendix "Mechanical Specifications" page mechanical specifications package.
Volt Intel® Wireless Flash Memory with Volt
Signal Descriptions
Table describes ball usage.
Table
Symbol A[22:0] D[15:0]
Signal Descriptions
Type Name Function ADDRESS INPUTS: memory addresses. Mbit: A[20:0]; Mbit: A[21:0]; Mbit: A[22:0] DATA INPUTS/OUTPUTS: Inputs data commands during write cycles; outputs data during memory, status register, protection register, configuration code reads. Data pins float when chip outputs deselected. Data internally latched during writes. ADDRESS VALID: ADV# indicates valid address presence address inputs. During synchronous read operations, addresses latched ADV#'s rising edge CLK's rising falling) edge, whichever occurs first. CHIP ENABLE: Asserting activates internal control logic, buffers, decoders, sense amps. De-asserting deselects device, places standby mode, tri-states outputs. CLOCK: synchronizes device system frequency during synchronous reads increments internal address generator. During synchronous read operations, addresses latched ADV#'s rising edge CLK's rising falling) edge, whichever occurs first. OUTPUT ENABLE: When asserted, enables device's output data buffers during read cycle. When deasserted, data outputs placed high-impedance state. RESET: When low, RST# resets internal automation inhibits write operations. This provides data protection during power transitions. de-asserting RST# enables normal operation places device asynchronous read-array mode. WAIT: WAIT signal indicates valid data during synchronous read modes. configured asserted-high asserted-low based Configuration Register. WAIT tri-stated deasserted. WAIT gated OE#. WRITE ENABLE: controls writes array. Addresses data latched rising edge WE#. WRITE PROTECT: Disables/enables lock-down function. When asserted, lock-down mechanism enabled blocks marked lock-down cannot unlocked through software. Section 7.1, "Block Lock Operations" page details block locking. ERASE PROGRAM POWER: valid voltage this allows erasing programming. Memory contents cannot altered when VPPLK. Block erase program invalid voltages should attempted.
ADV#
RST#
WAIT
Pwr/I
in-system program erase operations. accommodate resistor diode drops from system supply, level VPP1 min. must remain above VPP1 perform in-system flash modification. during read operations. VPP2 applied main blocks 1000 cycles maximum parameter blocks 2500 cycles. connected cumulative total exceed hours. Extended this reduce block cycling capability.
VCCQ VSSQ
DEVICE POWER SUPPLY: Writes inhibited VLKO. Device operations invalid voltages should attempted. OUTPUT POWER SUPPLY: Enables outputs driven VCCQ. This input tied directly VCC. GROUND: Pins internal device circuitry must connected system ground. OUTPUT GROUND: Provides ground outputs which driven VCCQ. This signal tied directly VSS. DON'T USE: this pin. This should connected power supplies, signals other pins must floated. CONNECT: internal connection; driven floated.
Volt Intel® Wireless Flash Memory with Volt
Memory Partitioning
Volt Intel Wireless Flash memory divided into 4-Mbit physical partitions, which allows simultaneous operations allows users segment code data areas 4-Mbit boundaries. device's memory array asymmetrically blocked, which enables system code data integration within single flash device. Each block erased independently block erase mode. Simultaneous program erase operations allowed; only partition time actively programming erasing. Table "Bottom Parameter Memory Map" page Table "Top Parameter Memory Map" page 32-Mbit device eight partitions, 64-Mbit device partitions, 128-Mbit device partitions. Each device density contains parameter partition several main partitions. 4-Mbit parameter partition contains eight 4-Kword parameter blocks seven 32Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each. bulk array divided into main blocks that store code data, parameter blocks that allow storage frequently updated small parameters that normally stored EEPROM. using software techniques, word-rewrite functionality EEPROMs emulated.
Volt Intel® Wireless Flash Memory with Volt
Table
Size (KW) Sixteen Partitions
Bottom Parameter Memory
Mbit Mbit Mbit 7F8000-7FFFFF 400000-407FFF 3F8000-3FFFFF 200000-207FFF 1F8000-1FFFFF 100000-107FFF 0F8000-0FFFFF 0C0000-0C7FFF 0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Eight Partitions
3F8000-3FFFFF
200000-207FFF
Four Partitions
1F8000-1FFFFF
1F8000-1FFFFF 100000-107FFF 0F8000-0FFFFF 0C0000-0C7FFF 0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Main Partitions
100000-107FFF
Partition
0F8000-0FFFFF
0C0000-0C7FFF
Partition
0B8000-0BFFFF 080000-087FFF 078000-07FFFF 040000-047FFF 038000-03FFFF 008000-00FFFF 007000-007FFF 000000-000FFF
Partition
Parameter Partition
Partition
Volt Intel® Wireless Flash Memory with Volt
Table
Size (KW) Parameter Partition
Parameter Memory
Mbit 1FF000-1FFFFF Mbit 3FF000-3FFFFF Mbit 7FF000-7FFFFF 7F8000-7F8FFF 7F0000-7F7FFF 7C0000-7C7FFF 7B8000-7BFFFF 780000-787FFF 778000-77FFFF 740000-747FFF 738000-73FFFF 700000-707FFF 6F8000-6FFFFF 600000-607FFF 5F8000-5FFFFF 400000-407FFF 3F8000-3FFFFF 000000-007FFF
Partition
1F8000-1F8FFF 1F0000-1F7FFF
3F8000-3F8FFF 3F0000-3F7FFF
1C0000-1C7FFF
3C0000-3C7FFF
Partition
1B8000-1BFFFF
3B8000-3BFFFF 380000-387FFF 378000-37FFFF 340000-347FFF 338000-33FFFF 300000-307FFF 2F8000-2FFFFF 200000-207FFF 1F8000-1FFFFF 000000-007FFF
18000-187FFF
Partition
178000-17FFFF
140000-147FFF
Partition
138000-13FFFF 100000-107FFF 0F8000-0FFFFF 000000-007FFF
Main Partitions
Four Partitions
Eight Partitions Sixteen Partitions
Device Operations
This section provides overview device operations. Volt Intel® Wireless Flash memory with family includes on-chip manage block erase program algorithms. allows minimal processor overhead with RAM-like interface timings.
Volt Intel® Wireless Flash Memory with Volt
Table
Mode Read Output Disable Standby Reset Write
Operations
Operations
Notes RST# ADV# WAIT Note High-Z High-Z High-Z High-Z D[15:0] DOUT High-Z High-Z High-Z
NOTES: must control pins addresses. RST# must meet maximum specified power-down current. Refer Table "Bus Cycle Definitions" page valid during write operation. WAIT only valid during synchronous array read operations.
3.1.1
Read
Volt Intel Wireless Flash memory several read configurations:
Asynchronous page mode read. Synchronous burst mode read outputs four, eight, sixteen, continuous words, from main
blocks parameter blocks. Several read modes available each partition:
Read-array mode: read accesses return flash array data from addressed locations. Read identifier mode: reads return manufacturer device identifier data, block lock status,
protection register data. Identifier information accessed starting 4-Mbit partition base addresses; flash array accessible read identifier mode.
Read query mode: reads return device data. information accessed starting
4-Mbit partition base addresses; flash array accessible read query mode.
Read status register mode: reads return status register data from addressed partition. That
partition's array data accessible. system processor check status register determine addressed partition's state monitor program erase progress. partitions support synchronous burst mode that internally sequences addresses with respect input select supply data outputs. Identifier codes, query data, status register read operations execute single-synchronous asynchronous read cycles. WAIT asserted during these reads. Access modes listed above independent VPP. appropriate command places device read mode. initial power-up after reset, device defaults asynchronous readarray mode. Asserting enables device read operations. device internally decodes upper address inputs determine which partition accessed. Asserting ADV# opens internal address latches. Asserting activates outputs gates selected data onto bus. asynchronous mode, address latched when ADV# deasserted (when device configured
Volt Intel® Wireless Flash Memory with Volt
ADV#). synchronous mode, address latched either rising edge ADV# rising falling) edge while ADV# remains asserted, whichever occurs first. RST# must deasserted during read operations.
3.1.2
Burst Suspend
Burst Suspend feature allows system temporarily suspend synchronous burst operation system needs flash address data other purposes. Burst accesses suspended during initial latency (before data received) after device output data. When burst access suspended, internal array sensing continues previously latched internal data retained. Burst Suspend occurs when asserted, current address been latched (either ADV# rising edge valid edge), halted, deasserted. halted when VIL. resume burst access, reasserted restarted. Subsequent edges resume burst sequence where left off. Within device, gates WAIT. Therefore, during Burst Suspend WAIT remains asserted does revert high-impedance state when deasserted. This cause contention with another device attempting control system's READY signal during Burst Suspend. System using Burst Suspend feature should connect device's WAIT signal directly system's READY signal. Refer Figure "Burst Suspend" page
3.1.3
Standby
De-asserting deselects device places standby mode, substantially reducing device power consumption. standby mode, outputs placed high-impedance state independent OE#. deselected during program erase algorithm, device shall consume active power until program erase operation completes.
3.1.4
Reset
device enters reset mode when RST# asserted. reset mode, internal circuitry turned outputs placed high-impedance state. After returning from reset, time tPHQV required until outputs valid, delay (tPHWV) required before write sequence initiated. After this wake-up interval, normal operation restored. device defaults read-array mode, status register 80h, configuration register defaults asynchronous page-mode reads. RST# asserted during erase program operation, operation aborts memory contents aborted block address invalid. Figure "Reset Operations Waveforms" page detailed information regarding reset timings. Like automated device, important assert RST# during system reset. When system comes reset, processor expects read from flash memory array. Automated flash memories provide status information when read during program erase operations. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Volt Intel Flash memories allow proper initialization following system reset through RST# input. this application, RST# controlled same reset signal, RESET#.
Volt Intel® Wireless Flash Memory with Volt
3.1.5
Write
write occurs when asserted deasserted. Flash control commands written using standard microprocessor write timings. Proper ADV# input needed proper latching addresses. Refer Section 11.2, Write Characteristics" page details. address data latched rising edge WE#. Write operations asynchronous; ignored (but still kept active/toggling). does occupy addressable memory location within partition. system processor must access correct address range depending kind command executed. Programming erasing occur only partition time. Other partitions must read modes erase suspend mode. Table "Command Codes Descriptions" page shows available commands. Appendix "Write State Machine States" page provides information moving between different operating modes using commands.
Device Commands
device's on-chip manages erase program algorithms. This local (WSM) controls device's in-system read, program, erase operations. cycles from flash memory conform standard microprocessor cycles. RST#, CE#, OE#, WE#, ADV# control signals dictate data flow into device. WAIT informs valid data during burst reads. Table "Bus Operations" page summarizes operations. Device operations selected writing specific commands into device's CUI. Table "Command Codes Descriptions" page lists possible command codes descriptions. Table "Bus Cycle Definitions" page lists command definitions. Because commands partition-specific, important issue write commands within target address range.
Table
Operation
Command Codes Descriptions (Sheet
Code Device Command Read Array Read Status Register Read Identifier Description Places selected partition read-array mode. Places selected partition status register read mode. partition enters this mode after Program Erase command issued Puts selected partition read identifier mode. Device reads from partition addresses output manufacturer/device codes, configuration register data, block lock status, protection register data D[15:0]. Puts addressed partition read query mode. Device reads from partition addresses output information D[7:0]. status register's block lock (SR[1]), (SR[3]), program (SR[4]), erase (SR[5]) status bits, cannot clear them. SR[5:3,1] only cleared device reset through Clear Status Register command.
Read
Read Query Clear Status Register
Volt Intel® Wireless Flash Memory with Volt
Table
Operation
Command Codes Descriptions (Sheet
Code Device Command Description This preferred program command's first cycle prepares program operation. second cycle latches address data, executes program algorithm this location. Status register updates occur when toggled. Read Array command required read array data after programming. Equivalent Program Setup command (40h). This program command activates mode. first write cycle sets command. second cycle Confirm command (D0h), subsequent writes provide program data. other commands ignored after mode begins. first command Setup (30h), latches address data, prepares device mode. This command prepares Block Erase. device erases block addressed Erase Confirm command. next command Erase Confirm, sets status register bits SR[5:4] indicate command sequence error places partition read status register mode. first command Erase Setup (20h), latches address data, erases block indicated erase confirm cycle address. During program erase, partition responds only Read Status Register, Program Suspend, Erase Suspend commands. toggle updates status register data. This command, issued device address, suspends currently executing program erase operation. Status register data indicates operation successfully suspended SR[2] (program suspend) SR[6] (erase suspend) SR[7] set. remains suspended state regardless control signal states (except RST#). This command, issued device address, resumes suspended program erase operation. This command prepares lock configuration. next command Lock Block, Unlock Block, Lock-Down, sets SR[5:4] indicate command sequence error. previous command Lock Setup (60h), locks addressed block. previous command Lock Setup (60h), latches address unlocks addressed block. previously locked-down, operation effect. previous command Lock Setup (60h), latches address locks-down addressed block. This command prepares protection register program operation. second cycle latches address data, starts WSM's protection register program lock algorithm. Toggling updates flash status register data. read array data after programming, issue Read Array command. This command prepares device configuration. Configuration Register next command, sets SR[5:4] indicate command sequence error. previous command Configuration Setup (60h), latches address writes data from A[15:0] into configuration register. Subsequent read operations access array data.
Word Program Setup
Program
Alternate Setup
Setup
Confirm
Erase
Erase Setup
Erase Confirm
Suspend
Program Suspend Erase Suspend Suspend Resume Lock Setup
Block Locking
Lock Block
Unlock Block
Lock-Down Protection Program Setup Configuration Setup Configuration Register
Protection
Configuration
NOTE: unassigned commands. Intel reserves right redefine these codes future functions.
Volt Intel® Wireless Flash Memory with Volt
Table
Operation
Cycle Definitions
Command Cycles First Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr1 Data2,3 40h/10h Write Write Write Write Write Write Write Second Cycle Oper Read Read Read Read Addr1 Read Address PBA+IA PBA+QA Data2,3 Array Data
Read Array/Reset Read Read Identifier Read Query Read Status Register Clear Status Register Block Erase Program Erase Lock Protection Word Program Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program
Lock Protection Program
Write
Write
FFFDh
Configuration
Configuration Register
Write
Write
Configuration
Configuration Register
Write
Write
NOTES: First-cycle command addresses should same operation's target address. Examples: firstcycle address Read Identifier command should same Identification code address (IA); first-cycle address Word Program command should same word address (WA) programmed; first-cycle address Erase/Program Suspend command should same address within block suspended; etc. valid address within device. Identification code address. Block Address. address within specific block. Lock Protection Address obtained from (through Read Query command). Volt Intel Wireless Flash memory family's 0080h. User programmable 4-word protection address. address within specific partition.
Volt Intel® Wireless Flash Memory with Volt
Partition Base Address. very first address particular partition. Query code address. Word address memory location written. Status register data. Data written location Identifier code data. User programmable 4-word protection data. Query code data D[7:0]. Configuration register code data presented device addresses A[15:0]. A[MAX:16] address bits select partition. Table "Configuration Register Definitions" page configuration register bits descriptions. Commands other than those shown above reserved Intel future device implementations should used.
Command Sequencing
When issuing 2-cycle write sequence flash device, read operation allowed occur between write cycles. setup phase 2-cycle write sequence places addressed partition into read-status mode, same partition read before second "confirm" write cycle issued, status register data will returned. Reads from other partitions, however, return actual array data assuming addressed partition already read-array mode. Figure page Figure page illustrate these conditions.
Figure Normal Write Read Cycles
Address Data
Partition
Partition
Partition
Block Erase Setup
Block Erase Conf
Read Array
Figure Interleaving 2-Cycle Write Sequence with Array Read
Address Data
Partition
Partition
Partition
Partition
Read Array
Erase Setup
Array Data
Read
Erase Conf
contrast, write cycle interrupt 2-cycle write sequence. Doing causes command sequence error appear status register. Figure illustrates command sequence error.
Volt Intel® Wireless Flash Memory with Volt
Figure Improper Command Sequencing
Address Data [D/Q]
Partition
Partitio
Partition
Partition
Data
Read Operations
Read Array
Read Array command places resets) partition read-array mode used read data from flash memory array. Upon initial device power-up, after reset (RST# transitions from VIH), partitions default asynchronous read-array mode. read array data from flash device, first write Read Array command (FFh) specify desired word address. Then read from that address. partition already read-array mode, issuing Read Array command required read from that partition. Read Array command written partition that erasing programming, device presents invalid data until program erase operation completes. After program erase finishes that partition, valid array data then read. Erase Suspend Program Suspend command suspends WSM, subsequent Read Array command places addressed partition read-array mode. Read Array command functions independently VPP.
Read Device
read identifier mode outputs manufacturer/device identifier, block lock status, protection register codes, configuration register data. identifier information contained within separate memory space device accessed along 4-Mbit partition address range supplied Read Identifier command (90h) address. Reads from addresses Table retrieve information. Issuing Read Identifier command partition that programming erasing places that partition's outputs read mode while partition continues program erase background.
Volt Intel® Wireless Flash Memory with Volt
Table
Device Identification Codes
Address1 Item Base Manufacturer Partition Offset 0089h 8852h 8853h 8854h Device Partition 8855h 8856h 8857h Block Lock Status(2) Block Block Lock-Down Status(2) Configuration Register Protection Register Lock Status Protection Register Block Partition Partition Partition Register Data Lock Data Register Data Multiple reads required read entire 128-bit Protection Register. Block locked down Block locked Block locked-down 64-Mbit 128-Mbit 128-Mbit Block unlocked 32-Mbit 32-Mbit 64-Mbit Data Description
NOTES: address constructed from base address plus offset. example, read Block Lock Status block number BPD, address (0F8000h) plus offset (02h), i.e. 0F8002h. Then examine data determine block locked. Section 7.1.4, "Block Lock Status" page valid lock status.
Read Query (CFI)
This device contains separate query database that acts "on-chip datasheet." information within this device accessed issuing Read Query command supplying specific address. address constructed from base address partition plus particular offset corresponding desired field. Appendix "Common Flash Interface" page shows accessible fields their address offsets. Issuing Read Query command partition that programming erasing puts that partition read query mode while partition continues program erase background.
Read Status Register
device's status register displays program erase operation status. partition's status read after writing Read Status Register command location within partition's address range. Read-status mode default read mode following Program, Erase, Lock Block command sequence. Subsequent single reads from that partition will return status until another valid command written.
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read-status mode supports single synchronous single asynchronous reads only; doesn't support burst reads. first falling edge latches updates status register data. operation doesn't affect other partitions' modes. Because status register bits wide, only [7:0] contains valid status register data; [15:8] contains zeros. Table "Status Register Definitions" page Table "Status Register Descriptions" page Each 4-Mbit partition contains status register. Bits SR[6:0] unique each partition, SR[7], Device Status (DWS) bit, pertains entire device. SR[7] provides program erase status entire device. contrast, Partition Status (PWS) bit, SR[0], provides program erase status addressed partition only. Status register bits SR[6:1] present information about partition-specific program, erase, suspend, VPP, block-lock states. Table "Status Register Device Partition Write Status Description" page presents descriptions (SR[7]) (SR[0]) combinations. Table
Status Register Definitions
VPPS
Table
Status Register Descriptions
Name State Device Busy Device Ready Erase progress/completed Erase suspended Erase successful Erase error Program successful Program error detect, operation aborted Program progress/completed Program suspended Unlocked Aborted erase/program attempt locked block This partition busy, only SR[7]=0 Another partition busy, only SR[7]=0 Description SR[7] indicates erase program completion device. SR[6:1] invalid while SR[7] Table valid SR[7] SR[0] combinations. After issuing Erase Suspend command, halts sets SR[7] SR[6]. SR[6] remains until device receives Erase Resume command. SR[5] attempted erase failed. Command Sequence Error indicated when SR[7,5:4] set. SR[4] failed program word. indicates level after program erase completes. SR[3] does provide continuous feedback isn't guaranteed when VPP1/2. After receiving Program Suspend command, halts execution sets SR[7] SR[2]. They remain until Resume command received. erase program operation attempted locked block VIL), sets SR[1] aborts operation. Addressed partition erasing programming. mode, SR[0] indicates that data-stream word finished programming verifying depending particular phase. Table valid SR[7] SR[0] combinations.
Device Status Erase Suspend Status Erase Status Program Status VPPS Status
Program Suspend Status Device Protect Status
Partition Write Status
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Table Status Register Device Partition Write Status Description
(SR[7]) (SR[0]) Description addressed partition performing program/erase operation. EFP: device finished programming verifying data, ready data. partition other than currently addressed performing program/erase operation. EFP: device either programming verifying data. program/erase operation progress partition. Erase Program suspend bits (SR[6,2]) indicate whether other partitions suspended. EFP: device exited mode. Won't occur standard program erase modes. EFP: this combination does occur.
Clear Status Register
Clear Status Register command clears status register leaves partition output states unchanged. status register bits clear bits SR[7:6,2,0]. Because bits SR[5,4,3,1] indicate various error conditions, they only cleared Clear Status Register command. allowing system software reset these bits, several operations (such cumulatively programming several addresses erasing multiple blocks sequence) performed before reading status register determine error occurrence. error detected, Status Register must cleared before beginning another command sequence. Device reset (RST# VIL) also clears status register. This command functions independently VPP.
Program Operations
Word Program
When Word Program command issued, executes sequence internally timed events program word desired address verify that bits sufficiently programmed. Programming flash array changes specifically addressed bits bits change memory cell contents. Programming occur only partition time. other partitions must either read mode erase suspend mode. Only partition erase suspend mode time. status register examined program progress reading address within partition that busy programming. However, while most status register bits partition-specific, Device Status bit, SR[7], device-specific; that status register read from other partition, SR[7] indicates program status entire device. This permits system monitor program progress while reading status other partitions. toggle (during polling) updates status register. Several commands issued partition that programming: Read Status Register, Program Suspend, Read Identifier, Read Query. Read Array command also issued, read data indeterminate.
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After programming completes, three status register bits signify various possible error conditions. SR[4] indicates program failure set. SR[3] set, couldn't execute Word Program command because outside acceptable limits. SR[1] set, program aborted because attempted program locked block. After status register data examined, clear with Clear Status Register command before command issued. partition remains status register mode until another command written that partition. command issued after status register indicates program completion. deasserted while device programming, devices will enter standby mode until program operation completes.
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Figure Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Command Operation Write Comments
Write 40h, Word Address Write Data Word Address
Program Data Setup Addr Location program (WA) Data Data Data program (WD) Addr Location program (WA) Read Toggle update Check SR[7] ready busy
Write
Read Read Status Register
Suspend Program Loop Suspend Program
Standby
SR[7]
Repeat subsequent programming operations. Full status register check done after each program after sequence program operations.
Full Program Status Check desired) Program Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status Register Command Operation Standby SR[3]
Comments Check SR[3] error Check SR[4] Data program error Check SR[1] Attempted program locked block Program aborted
Range Error Standby Program Error
SR[4]
Standby
SR[1]
Device Protect Error
SR[3] MUST cleared before will allow further program attempts Only Clear Staus Register command clears SR[4:3,1]. error detected, clear status register before attempting program retry other error recovery.
Program Successful
Factory Programming
standard factory programming mode uses same commands algorithm Word Program mode (40h/10h). When VPP1, program erase currents drawn through VCC. driven logic signal, VPP1 must remain above VPP1Min value perform insystem flash modifications. When connected power supply, device draws program erase current directly from VPP. This eliminates need external switching transistor control voltage. Figure "Examples Power Supply Configurations" page shows examples flash power supply usage various configurations.
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12-V mode enhances programming performance during short time period typically found manufacturing processes; however, intended extended use.12 applied during program erase operations specified Section 10.2, "Operating Conditions" page connected total tPPH hours maximum. Stressing device beyond these limits cause permanent damage.
Enhanced Factory Program (EFP)
substantially improves device programming performance through number enhancements conventional Volt word program algorithm. EFP's more efficient algorithm eliminates traditional overhead delays conventional word program mode both host programming system flash device. Changes conventional word programming flowchart internal routine were developed because today's beat-rate-sensitive manufacturing environments; balance between programming speed cycling performance attained. host programmer writes data device checks Status Register determine when data completed programming. This modification essentially cuts write cycles half. Following each internal program pulse, increments device's address next physical location. Now, programming equipment sequentially stream program data throughout entire block without having setup present each address. combination, these enhancements reduce much host programmer overhead, enabling more data streaming approach device programming. further speeds programming performing internal code verification. With this, PROM programmers rely device verify that been programmed properly. From device side, streamlines internal overhead eliminating delays previously associated switch voltages between programming verify levels each memory-word location. consists four phases: setup, program, verify exit. Refer Figure "Enhanced Factory Program Flowchart" page detailed graphical representation implement EFP.
5.3.1
Requirements Considerations
requirements:
Ambient temperature: within specified operating range within specified VPP2 range Target block unlocked
considerations: Block cycling below erase cycles supported2 programs block time cannot suspended
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Recommended optimum performance. Some degradation performance occur this limit exceeded, internal algorithm will continue work properly. Code data cannot read from another partition during EFP.
5.3.2
Setup
After receiving Setup (30h) Confirm (D0h) command sequence, SR[7] transitions from indicating that busy with algorithm startup. delay before checking SR[7] required allow time perform setups checks (VPP level block lock status). error detected, status register bits SR[4], SR[3], and/or SR[1] operation terminates. Note: After Setup Confirm command sequence, reads from device automatically output status register data. issue Read Status Register command; will interpreted data program WA0.
5.3.3
Program
After setup completion, host programming system must check SR[0] determine "data-stream ready" status (SR[0]=0). Each subsequent write after this program-data write flash array. Each cell within memory word programmed receives pulse; additional pulses, required, occur verify phase. SR[0]=1 indicates that busy applying program pulse. host programmer must poll device's status register "program done" state after each data-stream write. SR[0]=0 indicates that appropriate cell(s) within accessed memory location have received their single program pulse, that device ready next word. Although host check full status errors time, only necessary block basis, after exit. Addresses must remain within target block. Supplying address outside target block immediately terminates program phase; then enters verify phase. address either hold constant increment. device compares incoming address that stored from setup phase (WA0); they match, programs data word next sequential memory location. they differ, jumps address location. program phase concludes when host programming system writes different block address, data supplied must FFFFh. Upon program phase completion, device enters verify phase.
5.3.4
Verify
high percentage flash bits program first pulse. However, those cells that completely program their first attempt, internal verification identifies them applies additional pulses required. verify phase identical flow program phase, except that instead programming incoming data, compares verify-stream data that which previously programmed into block. data compares correctly, host programmer proceeds next word. not, host waits while applies additional pulse(s).
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host programmer must reset initial verify-word address same starting location supplied during program phase. then reissues each data word same order during program phase. Like programming, host write each subsequent data word increment through block addresses. verification phase concludes when interfacing programmer writes different block address; data supplied must FFFFh. Upon completion verify phase, device enters exit phase.
5.3.5
Exit
SR[7]=1 indicates that device returned normal operating conditions. full status check should performed this time ensure entire block programmed successfully. After exit, valid command issued.
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Figure Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE Setup
Start
Program
Read Status Register
Verify
Read Status Register
Exit
Read Status Register
Unlock Block
SR[0]=1=N
Data Stream Ready? SR[0] =0=Y Write Data Address
SR[0]=1=N Verify Stream Ready? SR[0] =0=Y Write Data Address
SR[7]=0=N
Exited? SR[7]=1=Y
Write Address
Full Status Check Procedure
Write Address SR[0]=1=N
setup time
SR[7]=0=Y
Read Status Register
Program Done? SR[0]=0=Y
SR[0]=1=N
Read Status Register
Read Status Register
Operation Complete
Verify Done? SR[0]=0=Y
Setup Done? SR[7]=1=N Check Lock errors (SR[3,1])
Last Data? Write FFFFh Address
Last Data? Write FFFFh Address
Exit
Setup
State Write Write Write Standby Read Standby Setup Done? Unlock Block Setup Comments Unlock block Data Address State Read
Program
Comments Status Register State Read
Verify
Comments Status Register
Data Check SR[0] Standby Stream Ready data Ready? ready data Write (note Read Data Data program Address Status Register
Verify Check SR[0] Standby Stream Ready verify Ready? ready verify Write (note Read Standby (note Standby Verify Done? Last Data? Exit Verify Phase Data Word verify Address Status Register Check SR[0] Verify done Verify done Device automatically increments address. Data FFFFh Address within same Status Register Check SR[7] Exit finished Exited? Exit completed
Data Confirm Address setup time Status Register Check SR[7] ready ready
Check SR[0] Program Standby Program done Done? Program done Standby Last Data? Device automatically increments address.
SR[7] Error Check SR[3,1] Standby Condition SR[3] error Check SR[1] locked block
Write
Exit Data FFFFh Program Address within same Phase
Write
Exit
first Word Address programmed within target block. (Block Base Address) must remain constant throughout program phase data stream; held constant first address location, written sequence through addresses within block. Writing equal that block currently being written terminates program phase, instructs device enter verify phase. proper verification occur verify data stream must presented device same sequence that program phase data stream. Writing equal terminates verify phase, instructs device exit Bits that fully program with single pulse program phase receive additional program-pulse attempts during verify phase. device will report program failure setting SR[4]=1; this check performed during full status check after been exited that block, will indicate error within entire data stream. Read Standby
Repeat subsequent operations. After exit, Full Status Check determine program error occurred. Full Status Check procedure Word Program flowchart.
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Program Erase Operations
Program/Erase Suspend Resume
Program Suspend Erase Suspend commands halt in-progress program erase operation. command issued device address. partition corresponding command's address remains previous state. suspend command allows data accessed from memory locations other than being programmed block being erased. program operation suspended only perform read operation. erase operation suspended perform either program read operation within block, except block that erase suspended. program command nested within suspended erase subsequently suspended read another location. Once program erase process starts, Suspend command requests that suspend program erase sequence predetermined points algorithm. partition that actually suspended continues output status register data after Suspend command written. operation suspended when status bits SR[7] SR[6] and/or SR[2] set. read data from blocks within partition (other than erase-suspended block), write Read Array command. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Identifier (ID), Read Query, Program Resume valid commands during Program Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, LockDown Block valid commands during erase suspend. read data from block partition that programming erasing, operation does need suspended. other partition already read array, Query mode, issuing valid address returns corresponding data. other partition read mode, read commands must issued partition before data read. During suspend, places device standby state, which reduces active current. must remain program level must remain unchanged while suspend mode. resume command instructs continue programming erasing clears status register bits SR[2] SR[6]) SR[7]. Resume command written partition. When read partition that programming erasing, device outputs data corresponding partition's last mode. status register error bits set, status register cleared before issuing next instruction. RST# must remain VIH. Figure "Program Suspend Resume Flowchart" page Figure "Erase Suspend Resume Flowchart" page suspended partition placed read array, read status register, read identifier (ID), read query mode during suspend, device remains that mode outputs data corresponding that mode after program erase operation resumed. After resuming suspended operation, issue read command appropriate read operation. read status after resuming suspended operation, issue Read Status Register command (70h) return suspended partition status mode. minimum tWHWH time should elapse between Erase command subsequent Erase Suspend command ensure that device achieves sufficient cumulative erase time. Occasional Erase-to-Suspend interrupts cause problems, Erase-to-Suspend commands issued frequently produce unexpected results.
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Figure Program Suspend Resume Flowchart
PROGRAM SUSPEND RESUME PROCEDURE
Start Command Operation Write Comments
Write Address Write Same Partition Read Status Register
Data Program Addr address within programming Suspend partition Read Status Data Addr address same partition Read Toggle update Addr address same partition Check SR[7] ready busy Check SR[2] Program suspended Program completed Read Array Data Addr device address (except word being programmed) Read array data from block other than being programmed Program Data Resume Addr device address
Write
Read
SR[7]
Standby
SR[2]
Program Completed
Standby
Write
Write Susp Partition Read Read Array Data
Write
Done Reading
suspended partition placed Read Array mode: Write Write Pgm'd Partition Read Array Data Read Status Return partition status mode: Data Addr address within same partition
Write Address Program Resumed Write Same Partition
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Figure Erase Suspend Resume Flowchart
ERASE SUSPEND RESUME PROCEDURE
Start Command Operation Write Comments
Write Address Write Same Partition
Erase Data Suspend Addr address Read Status Data Addr address same partition Read Toggle update Addr address same partition Check SR[7] ready busy Check SR[6] Erase suspended Erase completed Data Read Array Addr device address (except Program block being erased) Read array program data from/to block other than being erased Erase Resume Data Addr address
Write
Read Read Status Register Standby SR[7]
Standby Erase Completed Write Read Write Write
SR[6]
Read
Read Program?
Program
Read Array Data
Program Loop
Done?
suspended partition placed Read Array mode Program Loop: Write Read Status Return partition status mode: Data Addr Address within same partition
Write Address
Write Erased Partition Read Array Data
Erase Resumed
Write Same Partition
Block Erase
2-cycle block erase command sequence, consisting Erase Setup (20h) Erase Confirm (D0h), initiates block erase addressed block. Only partition erase mode time; other partitions must read mode. Erase Confirm command internally latches address block erased. Erase forces bits within block SR[7] cleared while erase executes.
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After writing Erase Confirm command, selected partition placed read status register mode reads performed that partition return current status data. address given during Erase Confirm command does need same address used Erase Setup command. Erase Confirm command given partition then selected block partition will erased even Erase Setup command partition 2-cycle erase sequence cannot interrupted with write operation. example, Erase Setup command must immediately followed Erase Confirm command order execute properly. different command issued between setup confirm commands, partition placed read-status mode, status register signals command sequence error, subsequent erase commands that partition ignored until status register cleared. detect block erase completion analyzing SR[7] that partition. error (SR[5,3,1]) flagged, status register cleared issuing Clear Status Register command before attempting next operation. partition remains read-status mode until another command written CUI. instruction follow after erasing completes. read-array mode prevent inadvertent status register reads.
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Figure Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Command Comments Operation Block Data Write Erase Addr Block erased (BA) Setup Write Write Block Address Read Read Status Register
Write Block Address
Erase Confirm
Data Addr Block erased (BA) Read Toggle update Check SR[7] ready busy
Suspend Erase Loop Suspend Erase
Standby
SR[7]
Repeat subsequent block erasures. Full status register check done after each block erase after sequence block erasures.
Full Erase Status Check desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register Range Error Standby
Command Operation Standby Check SR[3] error
Comments
SR[3]
Check SR[5:4] Both Command sequence error Check SR[5] Block erase error Check SR[1] Attempted erase locked block Erase aborted
SR[5:4]
Command Sequence Error Block Erase Error Erase Locked Block Aborted
Standby
SR[5]
Standby
SR[1]
SR[3,1] must cleared before will allow further erase attempts. Only Clear Status Register command clears SR[5:3,1]. error detected, clear Status register before attempting erase retry other error recovery.
Block Erase Successful
Read-While-Write Read-While-Erase
Volt Intel® Wireless Flash memory with supports flexible multi-partition dual-operation architecture. dividing flash memory into many separate partitions, device read from partition while programing erasing another partition; hence terms, RWE. Both these features greatly enhance data storage performance.
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product does support simultaneous program erase operations. Attempting perform operations such these results command sequence error. Only partition programming erasing while another partition reading. However, partition erase suspend mode while second partition performing program operation, another partition executing read command. Table "Command Codes Descriptions" page describes command codes available functions.
Security Modes
Volt Intel Wireless Flash memory with Volt offers both hardware software security features protect flash data. software security feature used executing Lock Block command. hardware security feature used executing Lock-Down Block command asserting signal. Refer Figure "Block Locking State Diagram" page state diagram flash security features. Also Figure "Locking Operations Flowchart" page
Block Lock Operations
Individual instant block locking protects code data allowing block locked unlocked with latency. This locking scheme offers levels protection. first allows software-only control block locking (useful frequently changed data blocks), while second requires hardware interaction before locking changed (protects infrequently changed code blocks). following sections discuss locking system operation. term "state [XYZ]" specifies locking states; example, "state [001]," where value, block lock-down status Block Lock status register Figure "Block Locking State Diagram" page defines possible locking states. following summarizes locking functionality.
blocks power-up locked state. Unlock commands unlock these blocks, lock commands lock them again. Lock-Down command locks block prevents from being unlocked when
asserted. Locked-down blocks unlocked locked with commands long deasserted When asserted, previously locked-down blocks return lock-down. lock-down status cleared only when device reset powered-down.
Block lock registers affected level. They modified read even VPPLK. Each block's locking status locked, unlocked, lock-down, described following sections. Figure "Locking Operations Flowchart" page
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Figure Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown [011]
Hardware Locked [011]
Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) hardware control
NOTE: notation [X,Y,Z] denotes locking state block, current locking state block defined state bits block-lock status D[1:0].
7.1.1
Lock
blocks default locked (state [x01]) after initial power-up reset. Locked blocks fully protected from alteration. Attempted program erase operations locked block will return error SR[1]. Unlocked blocks locked using Lock Block command sequence. Similarly, locked block's status changed unlocked lock-down using appropriate software commands.
7.1.2
Unlock
Unlocked blocks (states [x00] [110]) programmed erased. unlocked blocks return locked state when device reset powered-down. unlocked block's status changed locked locked-down state using appropriate software commands. locked block unlocked writing Unlock Block command sequence block lockeddown.
7.1.3
Lock-Down
Locked-down blocks (state [011]) offer user additional level write protection beyond that regular locked block. block that locked-down cannot have it's state changed software asserted. locked unlocked block locked-down writing Lock-Down Block command sequence. block locked-down, then later changed unlocked, LockDown command should issued prior asserting will that block back locked-down state. When deasserted, locked-down blocks changed locked state then unlocked Unlock Block command.
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7.1.4
Block Lock Status
Every block's lock status read read identifier mode. enter this mode, issue Read Identifier command device. Subsequent reads Block Base Address will output that block's lock status. example, read block lock status block address sent device should 50002h (for top-parameter device). lowest data bits read data, represent lock status. indicates block lock status. Lock Block command cleared Block Unlock command. also when entering lock-down state. indicates lock-down status Lock-Down command. lock-down status cannot cleared software-only device reset power-down. Table
Table Write Protection Truth Table
RST# Write Protection Device inaccessible Word program block erase prohibited lock-down blocks locked lock-down blocks unlocked
7.1.5
Lock During Erase Suspend
Block lock configurations performed during erase suspend operation using standard locking command sequences unlock, lock, lock-down block. This feature useful when another block requires immediate updating. change block locking during erase operation, first write Erase Suspend command. After checking SR[6] determine erase operation suspended, write desired lock command sequence block; lock status will changed. After completing lock, unlock, read, program operations, resume erase operation with Erase Resume command (D0h). block locked locked-down during suspended erase same block, locking status bits change immediately. When erase operation resumed, will complete normally. Locking operations cannot occur during program suspend. Appendix "Write State Machine States" page shows valid commands during erase suspend.
7.1.6
Status Register Error Checking
Using nested locking program command sequences during erase suspend introduce ambiguity into status register results. Because locking changes require 2-cycle command sequences, example, followed lock block, following Configuration Setup command (60h) with invalid command produces command sequence error (SR[5:4]=11b). Lock Block command error occurs during erase suspend, device sets SR[4] SR[5] even after erase resumed. When erase complete, possible errors during erase cannot detected from status register because previous locking command error. similar situation occurs program operation error nested within erase suspend.
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7.1.7
Lock-Down Control
Write Protect signal, WP#, adds additional layer block security. only affects blocks that once Lock-Down command written them. After lock-down status block, asserting forces that block into lock-down state [011] prevents from being unlocked. After deasserted, block's state reverts locked [111] software commands then unlock block (for erase program operations) subsequently re-lock Only device reset power-down clear lock-down status render ineffective.
Figure Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start Command Operation Write Block Address Write 01,D0,2Fh Block Address Write Optional Read Block Lock Status Write Lock Setup Comments Data Addr Block lock/unlock/lock-down (BA)
Write
Lock, Data (Lock block) Unlock, (Unlock block) Lockdown (Lockdown block) Confirm Addr Block lock/unlock/lock-down (BA) Read Plane Data Addr
Write (Optional)
Read Block Lock Block Lock status data (Optional) Status Addr
Locking Change?
Standby (Optional) Read Array
Confirm locking change DQ[1:0]. (See Block Locking State Transitions Table valid combinations.) Data Addr address same partition
Write Partition Address Lock Change Complete
Write
Protection Register
Volt Intel Wireless Flash memory includes 128-bit protection register. This protection register used increase system security identification purposes. protection register value match flash component system's ASIC prevent device substitution. lower bits within protection register programmed Intel with unique number each flash device. upper bits within protection register left customer program. Once programmed, customer segment locked prevent further programming. Note: individual bits user segment protection register OTP, register total. user program each individually, time, desired. After protection
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register locked, however, entire user segment locked more user bits programmed. protection register shares some same internal flash resources parameter partition. Therefore, only allowed between protection register main partitions. Table describes operations allowed protection register, parameter partition, main partition during RWE. Table Simultaneous Operations Allowed with Protection Register
Protection Register Parameter Partition Array Data Description Main Partitions Description While programming erasing main partition, protection register read from other partition. Reading parameter partition data allowed protection register being read from addresses within parameter partition. While programming erasing main partition, read operations allowed parameter partition. Accessing protection registers from parameter partition addresses allowed. While programming erasing main partition, read operations allowed parameter partition. Accessing protection registers partition that different from being programmed erased, also different from parameter partition, allowed. While programming protection register, reads only allowed other main partitions. Access parameter partition allowed. This because programming protection register only occur parameter partition, will exist status mode. While programming erasing parameter partition, reads protection registers allowed partition. Reads other main partitions supported.
Read
Write/Erase
Description
Read
Write/Erase
Read
Read
Write/Erase
Write
Access Allowed
Read
Access Allowed
Write/Erase
Read
7.2.1
Reading Protection Register
Writing Read Identifier command allows protection register data read bits time from addresses shown Table "Device Identification Codes" page protection register read from Read Identifier command read partition.Writing Read Array command returns device read-array mode.
7.2.2
Programing Protection Register
Protection Program command should issued only bottom partition followed data programmed specified location. programs upper bits protection register bits time. Table "Device Identification Codes" page shows allowable addresses. also Figure "Protection Register Programming Flowchart" page Issuing Protection Program command outside register's address space results status register error (SR[4]=1).
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7.2.3
Locking Protection Register
PR-LK.0 programmed Intel protect unique device number. PR-LK.1 programmed user lock user portion (upper bits) protection register (See Figure "Protection Register Locking). This using Protection Program command program "FFFDh" into PR-LK. After PR-LK register bits programmed (locked), protection register's stored values can't changed. Protection Program commands written locked section result status register error (SR[4]=1, SR[5]=1).
Figure Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMINGPROCEDURE
Start Command Comments Operation Protection Data Program Write Addr Protection address Setup Write Write Protect. Register Address Data Read Status Register Protection Data Data program Program Addr Protection address Read Toggle update Check SR[7] Ready Busy
Write Addr=Prot addr
Read
Standby
SR[7]
Protection Program operations addresses must within protection register address space. Addresses outside this space will return error. Repeat subsequent programming operations. Full status register check done after each program after sequence program operations.
Full Status Check desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read Command Operation Standby SR[4:3]
Comments SR[1] SR[3] SR[4] Error Protection register program error Register locked; Operation aborted
Range Error Standby
SR[4,1]
Programming Error
Standby
SR[4,1]
Locked-Register Program Aborted
SR[3] MUST cleared before will allow further program attempts. Only Clear Staus Register command clears SR[4:3,1]. error detected, clear status register before attempting program retry other error recovery.
Program Successful
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Figure Protection Register Locking
0x88 User-Programmable 0x85 0x84 Intel Factory-Programmed 0x81 Lock Register 0x80
Protection
Volt Intel® Wireless Flash memory with provides in-system program erase VPP1. factory programming, also includes low-cost, backward-compatible programming feature.(See "Factory Programming" page 26.) feature also used greatly improve factory program performance explained Section 5.3, "Enhanced Factory Program (EFP)" page addition flexible block locking, holding programming voltage provide absolute hardware write protection flash-device blocks. below VPPLK, program erase operations result error displayed SR[3]. (See Figure 14.)
Figure Examples Power Supply Configurations
System supply supply
System supply Prot# (logic signal)
fast programming Absolute write protection with VPPLK
Low-voltage programming Absolute write protection logic signal
System supply (Note supply
System supply
voltage fast programming
Low-voltage programming
NOTE: supply sink adequate current, appropriately valued resistor.
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Configuration Register
Configuration Register command sets burst order, frequency configuration, burst length, other parameters. two-bus cycle command sequence initiates this operation. configuration register data placed lower bits address (A[15:0]) during both cycles. Configuration Register command written along with configuration data address bus). This followed second write that confirms operation again presents configuration register data address bus. configuration register data latched rising edge ADV#, CE#, (whichever occurs first). This command functions independently applied voltage. After executing this command, device returns read-array mode. configuration register's contents examined writing Read Identifier command then reading location 05h. (See Table Table 14.)
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Table Configuration Register Definitions
Read Mode Res'd First Access Latency Count WAIT Polarity Data Output Config WAIT Config Burst Clock Config Res'd Res'd Burst Wrap Burst Length
Table Configuration Register Descriptions
Name Read Mode LC2-0 Description Notes1
13-11
Synchronous Burst Reads Enabled Asynchronous Reads Enabled (Default) Reserved Reserved Code Code Code Code Reserved (Default)
First Access Latency Count
WAIT Signal Polarity
WAIT signal asserted WAIT signal asserted high (Default) Hold Data Clock Hold Data Clock (Default) WAIT Asserted During Delay WAIT Asserted Data Cycle before Delay (Default) Intel Burst Order Linear Burst Order (Default) Burst Starts Data Output Falling Clock Edge Burst Starts Data Output Rising Clock Edge (Default) Reserved Reserved Wrap bursts within burst length CR[2:0] Don't wrap accesses within burst length CR[2:0].(Default) 4-Word Burst 8-Word Burst 16-Word Burst (Available lithography) Continuous Burst (Default)
Data Output Configuration
WAIT Configuration
Burst Sequence
Clock Configuration
Burst Wrap BL2-0
Burst Length
NOTES: Undocumented combinations bits reserved Intel future implementations. Synchronous page read mode configurations affect reads from main blocks parameter blocks. Status register configuration reads support single read cycles. CR[15]=1 disables configuration CR[14:0]. Data ready when WAIT asserted. synchronous burst length. asynchronous page mode, burst length equals four words. reserved configuration register bits zero.
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Read Mode (CR[15])
partitions support high-performance read configurations: synchronous burst mode asynchronous page mode (default). CR[15] sets read configuration these modes. Status register, query, identifier modes support only asynchronous single-synchronous read operations.
First Access Latency Count (CR[13:11])
First Access Latency Count (CR[13:11]) configuration tells device many clocks must elapse from ADV# de-assertion (VIH) before first data word should driven onto data pins. input clock frequency determines this value. Table "Configuration Register Definitions" page latency values. Figure shows data output latency from ADV# assertion different latencies.
Figure First Access Latency Configuration
Valid Address
Address
ADV# D[15:0] Code
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
D[15:0]
Code
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
D[15:0]
Code
Valid Output
Valid Output
Valid Output
Valid Output
D[15:0]
Code
Valid Output
Valid Output
Valid Output
NOTE: Other First Access Latency Configuration settings reserved.
these equations calculate First Access Latency Count:
Clock Period Frequency Choose number cycles, such that: AVQV tADD-DELAY DATA First Access Latency Count (LC)
must when starting address aligned 4-word boundary CR[3]=1 (no-wrap).
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Table First Latency Count (LC)
Setting Burst Length Wrap Aligned 4-word Boundary? WAIT Asserted 16-Word Boundary Crossing?
Continuous
Disabled Disabled Enabled Enabled
Yes, Occurs Every word boundary crossing Yes, Occurs Once1
NOTE: Section 8.10, "Burst Length (CR[2:0])" page details.
Figure Word Boundary
Word
Word
Word
Word
Word Boundary Word Boundary
NOTE: 16-word boundary device sense word-line.
Parameters defined CPU:
tADD-DELAY Clock CE#, ADV#, Address Valid, whichever occurs last. tDATA Data setup Clock.
Parameters defined flash:
tAVQV Address Output Delay.
Example:
Clock Speed tADD-DELAY (typical speed from CPU) (max) tDATA (typical speed from CPU) (min) tAVQV (from Characteristic Read Only Operations Table) From (1): From 1/40 (MHz) n(25 n(25 80/25 (Integer) From (assuming starting address 4word unaligned, must n-1)
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First Access Latency Count Setting Code (Figure "Data Output with Setting Code page displays sample data.)
formula tAVQV (ns) tADD-DELAY (ns) tDATA (ns) also known initial access time. Figure shows data output available valid after four clocks from assertion ADV# first clock period with setting Figure Data Output with Setting Code
tADD-DELAY ADV#
tDATA
AMAX-0 Code DQ15-0 (D/Q)
Valid Address
High
Valid Output
Valid Output
R103
WAIT Signal Polarity (CR[10])
cleared (CR[10]=0), then WAIT configured asserted low. This means that WAIT signal indicates that data ready data contains invalid data. Conversely, CR[10] set, then WAIT asserted high. either case, WAIT deasserted, then data ready valid. WAIT asserted during asynchronous page mode reads.
WAIT Signal Function
WAIT signal indicates data valid when device operating synchronous mode (CR[15]=0), when addressing partition that currently read-array mode. WAIT signal only "deasserted" when data valid bus. When device operating synchronous non-read-array mode, such read status, read read query, WAIT "asserted" state determined CR[10]. Figure "WAIT Signal Synchronous Non-Read Array Operation Waveform" page
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When device operating asynchronous page mode asynchronous single word read mode, WAIT "asserted" state determined CR[10]. Figure "Page-Mode Read Operation Waveform" page Figure "Asynchronous Read Operation Waveform" page From system perspective, WAIT signal asserted state (based CR[10]) when device operating synchronous non-read-array mode (such Read Read Query, Read Status), device operating asynchronous mode (CR[15]=1). these cases, system software should ignore (mask) WAIT signal, because does convey useful information about validity what appearing data bus.
CONDITION WAIT
Synchronous Array Read Synchronous Non-Array Read Asynchronous Read Write
Tri-State Active No-Effect Active Asserted Asserted
Data Hold (CR[9])
Data Output Configuration (CR[9]) determines whether data word remains valid data clock cycles. processor's minimum data set-up time flash memory's clock-to-data output delay determine whether clocks needed. Data Output Configuration 1-clock data hold corresponds 1-clock data cycle; Data Output Configuration 2-clock data hold corresponds 2-clock data cycle. setting this configuration depends system characteristics. clarification, Figure "Data Output Configuration with WAIT Signal Delay" page method determining this configuration setting shown below. device 1-clock data hold subsequent reads, following condition must satisfied:
tCHQV (ns) DATA (ns) Period (ns)
example, clock frequency clock period Assume data output hold time clock. Apply this data formula above subsequent reads:
This equation satisfied, data output will available valid every clock period. tDATA
long, hold cycles.
During page-mode reads, initial access time determined formula:
tADD-DELAY (ns) tDATA (ns) AVQV (ns)
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Subsequent reads page mode defined
(ns) tDATA (ns) (minimum time)
Figure Data Output Configuration with WAIT Signal Delay
WAIT (CR.8 tCHQV WAIT (CR.8 Note
Valid Output Valid Output Valid Output
Note
Data Hold
DQ15-0
tCHTL/H tCHQV
WAIT (CR.8 WAIT (CR.8
Note Note
Valid Output Valid Output
Data Hold
DQ15-0
NOTE: WAIT shown asserted high (CR[10]=1).
WAIT Delay (CR[8])
WAIT configuration (CR[8]) controls WAIT signal delay behavior synchronous read-array modes. setting depends system characteristics. WAIT asserted either during, data cycle before, valid output. synchronous linear read array (no-wrap mode CR[3]=1) 16-, continuous-word burst mode, output delay occur when burst sequence crosses first device-row boundary (16word boundary). burst start address 4-word boundary aligned, delay does occur. start address misaligned 4-word boundary, delay occurs once burst-mode read sequence. WAIT signal informs system this delay.
Burst Sequence (CR[7])
burst sequence specifies synchronous-burst mode data order (see Table "Sequence Burst Length" page 50). this linear Intel burst order. Continuous burst mode supports only linear burst order. When operating linear burst mode, either 16-word burst length with burst wrap (CR[3]) set, continuous burst mode, device incur output delay when burst sequence crosses first 16-word boundary. (See Figure "Word Boundary" page word boundary description.) This depends starting address. starting address aligned 4-word boundary, there delay. starting address 4-word boundary, output delay clock cycle less than First Access Latency Count; this worst-case
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delay. delay takes place only once, only burst sequence crosses 16-word boundary. WAIT informs system this delay. timing diagrams WAIT functionality, these figures:
Figure "Single Synchronous Read-Array Operation Waveform" page Figure "Synchronous 4-Word Burst Read Operation Waveform" page Figure "WAIT Functionality EOWL (End-of-Word Line) Condition Waveform"
page Table Sequence Burst Length (Sheet
Burst Addressing Sequence (Decimal) Start Addr. (Dec) 4-Word Burst
CR[2:0]=001b
8-Word Burst
CR[2:0]=010b
16-Word Burst1
CR[2:0]=011b
Continuous Burst
CR[2:0]=111b
Linear
Intel
Linear
Intel
Linear
Intel
Linear
Wrap (CR[3]=0)
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-235-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
0-1-2.14-15 1-2-3.14-15-0 2-3-4.15-0-1 3-4-5.15-0-1-2 4-5-6.15-0-1-23 5-6-7.15-0-1.4 6-7-8.15-0-1.5 7-8-9.15-0-1.6
0-1-2-3-4.14-15 1-0-3-2-5.15-14 2-3-0-1-6.12-13 3-2-1-0-7.13-12 4-5-6-7-0.10-11 5-4-7-6-1.11-10 6-7-4-5-2.8-9 7-6-5-4-3.9-8
0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12. 7-8-9-10-11-1213.
14-15-0-1.13
14-15-12-13-10.01
14-15-16-17-18-1920-. 15-16-17-18-19-.
15-0-1-2-3.14
15-14-13-12-11.10
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Table Sequence Burst Length (Sheet
No-Wrap (CR[3]=1)
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-910 4-5-6-7-8-9-1011 5-6-7-8-9-1011-12 6-7-8-9-10-1112-13 7-8-9-10-1112-13-14
0-1-2.14-15 1-2-3.15-16 2-3-4.16-17 3-4-5.17-18 4-5-6.18-19 5-6-7.19-20 6-7-8.20-21 7-8-9.21-22
0-1-2-3-4-5-6-. 1-2-3-4-5-6-7-. 2-3-4-5-6-7-8-. 3-4-5-6-7-8-9-. 4-5-6-7-8-9-10. 5-6-7-8-9-10-11. 6-7-8-9-10-11-12. 7-8-9-10-11-1213.
NOTE: Available lithography
14-15.28-29 15-16.29-30
14-15-16-17-1819-20-. 15-16-17-18-1920-21-.
Clock Edge (CR[6])
Configuring valid clock edge enables flexible memory interface wide range burst CPUs. Clock configuration sets device start burst cycle, output data, assert WAIT clock's rising falling edge.
Burst Wrap (CR[3])
burst wrap determines whether 16-word burst accesses wrap within burstlength boundary whether they cross word-length boundaries perform linear accesses. Nowrap mode (CR[3]=1) enables WAIT hold system processor, does continuous burst mode, until valid data available. no-wrap mode (CR[3]=0), device operates similarly continuous linear burst mode consumes less power during 16-word bursts. example, CR[3]=0 (wrap mode) CR[2:0] (4-word burst), possible linear burst sequences 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. CR[3]=1 (no-wrap mode) CR[2:0] (4-word burst length), then possible linear burst sequences 0-1-2-3, 1-2-3-4, 2-3-4-5, 3-4-5-6. CR[3]=1 only enables limited nonaligned sequential bursts, also reduces power minimizing number internal read operations. Setting CR[2:0] bits continuous linear burst mode (7h) also achieves above 4-word burst sequences. However, significantly more power consumed. 1-2-3-4 sequence, example, consumes power during initial access, again during internal pipeline lookup
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processor reads word possibly again, depending system timing, near sequence device pipelines next 4-word sequence. CR[3]=1 while 4-word burst mode (no-wrap mode) reduces this excess power consumption.
8.10
Burst Length (CR[2:0])
burst length number words device outputs synchronous read access. 16-, continuous-word supported. 16-word burst configuration, burst wrap (CR[3]) determines burst accesses wrap within word-length boundaries whether they cross word-length boundaries perform linear access. Once address given, device outputs data until reaches burstable address space. Continuous burst accesses linear only (burst wrap CR[3] ignored during continuous burst) wrap within word-length boundaries (see Table "Sequence Burst Length" page 50).
Power Consumption
Volt Intel® Wireless Flash memory with devices have layered approach power savings that significantly reduce overall system power consumption. feature reduces power consumption when device selected idle. deasserted, memory enters standby mode, where current consumption even lower. Asserting RST# provides current savings similar standby mode. combination these features minimize memory power consumption, therefore, overall system power consumption.
Active Power
With RST# VIH, device active mode. Refer Section 10.3, Current Characteristics" page values. When device "active" state, consumes most power from system. Minimizing device active current therefore reduces system power consumption, especially battery-powered applications.
Automatic Power Savings (APS)
Automatic Power Saving (APS) provides low-power operation during read's active state. During mode, ICCAPS average current measured over time interval after following events happen:
There internal sense activity; asserted; address lines quiescent, VSSQ VCCQ.
asserted during APS.
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Standby Power
With device read mode, flash memory standby mode, which disables most device circuitry substantially reduces power consumption. Outputs placed highimpedance state independent signal state. transitions during erase program operations, device continues operation consumes corresponding active power until operation complete. ICCS average current measured over time interval after de-assertion.
Power-Up/Down Characteristics
device protected against accidental block erasure programming during power transitions. Power supply sequencing required VCC, VCCQ, connected together; doesn't matter whether powers-up first. VCCQ and/or connected system supply, then should attain VCCMIN before applying VCCQ VPP. Device inputs should driven before supply voltage VCCMIN. Power supply transitions should only occur when RST# low.
9.4.1
System Reset RST#
RST# during system reset important with automated program/erase devices because system expects read from flash memory when comes reset. reset occurs without flash memory reset, proper initialization will occur because flash memory providing status information instead array data. allow proper CPU/flash initialization system reset, connect RST# system RESET# signal. System designers must guard against spurious writes when voltages above VLKO. Because both must command write, driving either signal inhibits writes device. architecture provides additional protection because alteration memory contents only occur after successful completion two-step command sequences. device also disabled until RST# brought VIH, regardless control input states. holding device reset (RST# connected system PowerGood) during power-up/down, invalid conditions during power-up masked, providing another level memory protection.
9.4.2
VCC, VPP, RST# Transitions
latches commands issued system software altered transitions actions. Read-array mode power-up default state after exit from reset mode after transitions above VLKO (Lockout voltage). After completing program block erase operations (even after transitions below VPPLK), Read Array command must reset read-array mode flash memory array access desired.
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Power Supply Decoupling
When device accessed, many internal conditions change. Circuits enabled charge pumps switch voltages. This internal activity produces transient noise. minimize effect this transient noise, device decoupling capacitors required. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control proper decoupling capacitor selection suppresses these transient voltage peaks. Each flash device should have ceramic capacitor connected between each power (VCC, VCCQ, VPP), ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should close possible package signals.
10.0
10.1
Warning:
Thermal Characteristics
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended, extended exposure beyond "Operating Conditions" affect device reliability.
Notice: This datasheet contains information products design phase development. information here subject change without notice. finalize design with this information.
Table Absolute Maximum Ratings
Parameter Note Maximum Rating
Temperature under Bias Storage Temperature Voltage (except VCC, VCCQ, VPP) Voltage VCCQ Voltage Output Short Circuit Current 1,2,3
+125 -0.5 +2.45 -0.2 -0.2 +2.45
NOTES: specified voltages relative VSS. Minimum voltage -0.5 input/output pins -0.2 pins. During transitions, this level undershoot -2.0 periods which, during transitions, overshoot +2.0 periods Maximum voltage overshoot +14.0 periods program voltage normally VPP1. 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. Output shorted more than second. more than output shorted time.
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10.2
Operating Conditions
Table Extended Temperature Operation
Symbol Parameter1 Note Unit
VCCQ VPP1 VPP2 tPPH Block Erase Cycles
Operating Temperature Supply Voltage Supply Voltage Voltage Supply (Logic Level) Factory Programming Maximum Hours Main Parameter Blocks Main Blocks Parameter Blocks
0.90 11.4
1.80 12.0
1.95 1.95 12.6
Hours
100,000 1000 2500 Cycles
NOTES: Section 10.3, Current Characteristics" page Section 10.4, Voltage Characteristics" page specific voltage-range specifications. normally VPP1. connected 11.4 V-12.6 1000 cycles main blocks extended temperatures 2500 cycles parameter blocks extended temperature. Contact your Intel field representative VCC/VCCQ operations down 1.65 tables Section 10.0, "Thermal Characteristics" page Section 11.0, Characteristics" page operating characteristics
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10.3
Current Characteristics
Table Current Characteristics (Sheet
VCCQ= Parameter Note 32/64 Mbit Mbit Unit Test Condition
Input Load
VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax VCCQ VCCMax VCCQ VCCQMax RST# =VCC VCCMax VCCQ VCCQMax VSSQ RST# =VCCQ other inputs =VCCQ VSSQ Word Read Burst length Burst length Burst length Burst length Continuous VPP1, Program Progress VPP2, Program Progress VPP1, Block Erase Progress VPP2, Block Erase Progress VCC, Program Suspended VCC, Erase Suspended VCCMax Inputs
Output Leakage
DQ[15:0]
ICCS
Standby
ICCAPS
Asynchronous Page Mode f=13
ICCR Average Read Synchronous ICCW Program 3,4,5 ICCE Block Erase 3,4,5 ICCWS ICCES Program Suspend Erase Suspend
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Table Current Characteristics (Sheet
VCCQ= Parameter Note 32/64 Mbit Mbit Unit Test Condition
IPPS (IPPWS
IPPES) IPPR
Standby Program Suspend Erase Suspend Read
<VCC VPP1, Program Progress
0.05
0.10 0.10
0.05 0.05
0.10
IPPW
Program
0.05 0.10
VPP2, Program Progress VPP1, Erase Progress VPP2, Erase Progress
IPPE
Erase
NOTES: currents unless noted. Typical values typical VCC, +25°C. Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation. ICCRQ specification details. Sampled, 100% tested. read program current read program currents. read erase current read erase currents. ICCES specified with device deselected. device read while erase suspend, current ICCES plus ICCR. VPPLK inhibits erase program operations. Don't VPPL VPPH outside their valid ranges. undershoot -0.4V overshoot VCCQ+0.4V durations less. VIN>VCC input load current increases max. 10.ICCS average current measured over time interval after de-assertion. Refer section Section 9.2, "Automatic Power Savings (APS)" page ICCAPS measurement details. 12.TBD values determined pending silicon characterization.
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10.4
Voltage Characteristics
Table Voltage Characteristics
VCCQ= Parameter Note 32/64 Mbit Mbit Unit Test Condition
Input Input High Output
VCCQ
VCCQ
VCCQ
VCCQ
VCCMin VCCQ VCCQMin VCCMin VCCQ VCCQMin -100
Output High
VCCQ
VCCQ
VPPLK VLKO VILKOQ
Lock-Out Lock VCCQ Lock
NOTE: numbered note references this table, refer notes Table Current Characteristics" page
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11.0
11.1
Characteristics
Read Operations
Table Read Operations (Sheet
32-Mbit 64-Mbit Parameter Notes Asynchronous Specifications 128-Mbit Unit
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address Output Valid Output Valid Output Valid RST# High Output Valid Output Low-Z Output Low-Z High Output High-Z High Output High-Z (OE#) High Output Low-Z
Latching Specifications
R101 R102 R103 R104 R105 R106 R108
tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA
Address Setup ADV# High ADV# High ADV# Output Valid ADV# Pulse Width ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time
Clock Specifications
R200 R201 R202 R203
fCLK tCLK tCH/L tCHCL
Frequency Period High Time Fall Rise Time
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Table Read Operations (Sheet
32-Mbit 64-Mbit Parameter Notes Synchronous Specifications 128-Mbit Unit
R301 R302 R303 R304 R305 R306 R307 R308 R309 R310
tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV tELTV tEHTZ tEHEL
Address Valid Setup ADV# Setup Setup Output Valid Output Hold from Address Hold from WAIT Valid WAIT Valid High WAIT High-Z Pulse Width High
NOTES: Figure Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. specifications assume data voltage less than equal VCCQ when read operation initiated. Address hold synchronous-burst mode defined tCHAX tVHAX, whichever timing specification satisfied first. delayed tELQV- tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Applies only subsequent synchronous reads. During initial access synchronous burst read, data from first word begin driven onto data early first clock edge after tAVQV. specs above apply densities.
Volt Intel® Wireless Flash Memory with Volt
Figure Asynchronous Read Operation Waveform
Address
Valid Address
High High
WAIT
Note
Data [D/Q]
High
Valid Output
RST#
NOTES:. WAIT shown asserted (CR.10=0) ADV# assumed driven this waveform
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Figure Latched Asynchronous Read Operation Waveform
A[MAX:2]
Valid Address
Valid Address
A[1:0]
R101 R105 R106
Valid Address
Valid Address
ADV#
R104 R103
R102
Data
High
Valid Output
RST#
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Figure Page-Mode Read Operation Waveform
A[MAX:2]
Valid Address
A[1:0]
R101 R105 R106
Valid Address
Valid Address
Valid Address
Valid Address
ADV#
R104 R103
R102
WAIT
High Valid Output Valid Output Valid Output Valid Output High
Note
R108
High
Data [D/Q]
RST#
NOTE: WAIT shown asserted (CR.10
Volt Intel® Wireless Flash Memory with Volt
Figure Single Synchronous Read-Array Operation Waveform
R301 R306 Note
Address
Valid Address
R101 R105 R106 R302
ADV#
R104 R103
R102
R303
R308 R309 Note R304 R305
Valid Output High
WAIT
High
Data
High
RST#
NOTES: Section 8.2, "First Access Latency Count (CR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; CR.10=0) configured assert either during, data cycle before, valid data. This waveform illustrates case which x-word burst initiated main array terminated de-assertion after first word burst. this access been done Status, Query reads, asserted (low) WAIT signal would have remained asserted (low) long asserted (low).
Volt Intel® Wireless Flash Memory with Volt
Figure Synchronous 4-Word Burst Read Operation Waveform
R301 R306 Note
Address
Valid Address
R101 R105 R106 R302
ADV#
R104 R103 R310
R102
R303
R308 R307 R309
High
WAIT
High
Note R304 R305
Valid Output Valid Output Valid Output Valid Output
Data
High
High
RST#
NOTES: Section 8.2, "First Access Latency Count (CR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; CR.10 configured assert either during, data cycle before, valid data.
Volt Intel® Wireless Flash Memory with Volt
Figure WAIT Functionality EOWL (End-of-Word Line) Condition Waveform
R301 R306
Note
Address
Valid Address
R101 R105 R106 R302
ADV#
R104 R103
R102
R303
R308 R307
WAIT
High
Note R304 R305
Valid Output Valid Output Valid Output Valid Output
High
Data [D/Q]
High
RST#
NOTES: Section 8.2, "First Access Latency Count (CR[13:11])" page describes insert clock cycles during initial access. WAIT (shown asserted; CR.10=0) configured assert either during, data cycle before, valid data. (assumed wait delay clocks example)
Volt Intel® Wireless Flash Memory with Volt
Figure WAIT Signal Synchronous Non-Read Array Operation Waveform
Note R301 R306
Address
Valid Address
R101 R105 R106 R302
ADV#
R104 R103
R102
R303
R308 R309 Note R304 R305
Valid Output High
WAIT
High
Data
High
RST#
NOTES: Section 8.2, "First Access Latency Count (CR[13:11])" page describes insert clock cycles during initial access. WAIT shown asserted (CR.10=0).
Volt Intel® Wireless Flash Memory with Volt
Figure Burst Suspend
R304 Address R101 R105 ADV# WAIT DATA [D/Q] R304 R304 R305 R305 R305
R106
NOTE: During Burst Suspend Clock signal held high
Volt Intel® Wireless Flash Memory with Volt
11.2
Write Characteristics
Table Write Characteristics
32-Mbit 64-Mbit 128-Mbit Parameter Notes -85/-90 Unit
tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH) tQVVL tQVBL tBHWH (tBHEH) tWHGL (tEHGL) tWHQV tWHAV tWHCV tWHVH
RST# High Recovery (CE#) (WE#) Setup (CE#) (CE#) Write Pulse Width Data Setup (CE#) High Address Setup (CE#) High (WE#) Hold from (CE#) High Data Hold from (CE#) High Address Hold from (CE#) High (CE#) Pulse Width High Setup (CE#) High Hold from Valid Hold from Valid Setup (CE#) High Write Recovery before Read High Valid Data High Address Valid High Valid High ADV# High
tAVQV
5,6,7
3,6,10 3,9,10 3,10 3,10
tAVQV
NOTES: Write timing characteristics during erase suspend same during write-only operations. write operation terminated with either WE#. Sampled, 100% tested. Write pulse width (tWLWH tELEH) defined from (whichever occurs last) high (whichever occurs first). Hence, tWLWH tELEH tWLEH tELWH. Write pulse width high (tWHWL tEHEL) defined from high (whichever first) (whichever last). Hence, tWHWL tEHEL tWHEL tEHWL.
Volt Intel® Wireless Flash Memory with Volt
System designers should take this into account insert software No-Op instruction delay first read after issuing command. commands other than resume commands. should held VPP1 VPP2 until block erase program success determined. Applicable during asynchronous reads following write. 10.tWHCH/L tWHVH must when transitioning from write cycle synchronous burst read. tWHCH/L tWHVH both refer address latching event (either rising/falling clock edge rising ADV# edge, whichever occurs first). NOTES:
Figure Write Operations Waveform
Note
Note
Valid Address
Note
Valid Address
Note
Note
Valid Address
Address
R101 R105 R106
ADV#
R104
(WE#) [E(W)]
Note
(CE#) [W(E)]
Note
Data
Data Data
Valid
RST#
VPPH
VPPLK
NOTES: power-up standby. Write Program Erase Setup command. Write valid address data (for program) Erase Confirm command. Automated program/erase delay. Read status register data (SRD) determine program/erase operation completion. must asserted must deasserted read operations. ignored. (but kept active/toggling)
Volt Intel® Wireless Flash Memory with Volt
Figure Asynchronous Read Write Operation Waveform
Address Data [D/Q] RST#
Figure Asynchronous Write Read Operation
Address
Data [D/Q]
Volt Intel® Wireless Flash Memory with Volt
Figure Synchronous Read Write Operation
Latency Count R301 R302 R306 R101 Address R105 R106 R102 ADV# R303 WAIT R304 Data [D/Q] R305 R307 R104
Figure Synchronous Write Read Operation
ency Count R302 R301 Address ADV# R303 R106 R104 R306
WAIT Data [D/Q RST# R304 R304 R305 R307
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11.3
Erase Program Times
Table Erase Program Times
Operation Symbol Parameter Description1 VPP1 Notes Erasing Suspending VPP2 Unit
W500 Erase Time Suspend Latency
Programming
tERS/PB tERS/MB tSUSP/P tSUSP/E
4-Kword Parameter Block 32-Kword Main Block Program Suspend Erase Suspend
0.25
W501 W600 W601
W200 Program Time W201 W202
tPROG/W tPROG/PB tPROG/MB
Single Word 4-Kword Parameter Block 32-Kword Main Block
0.05
0.03 0.24
0.07
Enhanced Factory Programming5
W400 Program W401 W402 W403 Operation Latency W404 W405
tEFP/W tEFP/PB tEFP/MB tEFP/SETUP tEFP/TRAN tEFP/VERIFY
Single Word 4-Kword Parameter Block 32-Kword Main Block Setup Program Verify Transition Verify
NOTES: Unless noted otherwise, parameters measured nominal voltages, they sampled, 100% tested. Excludes external system-level overhead. Exact results vary based system overhead. W400-Typ calculated delay single programming pulse. W400-Max includes delay when programming within word-line. Some performance degradation occur block cycling exceeds
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11.4
Reset Specifications
Table Reset Specifications
Symbol Parameter1 Notes Unit
tPLPH tPLRH tVCCPH
RST# Reset during Read RST# Reset during Block Erase RST# Reset during Program Power Valid Reset
1,3,4,5,6
NOTES: These specifications valid product versions (packages speeds). device reset tPLPH< tPLPHMin, this guaranteed. applicable RST# tied VCC. Sampled, 100% tested. RST# tied VCC, device ready until tVCCPH occurs after when VCCMin. RST# tied supply/signal with VCCQ voltage levels, RST# input voltage must exceed until VCCMin.
Figure Reset Operations Waveforms
Reset during read mode
RST#
Reset during program block erase
Abort Complete
RST#
Reset during program block erase
Abort Complete
RST#
Power-up RST# high
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11.5
Test Conditions
Figure Input/Output Reference Waveform
VCCQ Input
NOTE: Input timing begins, output timing ends, VCCQ/2. Input rise fall times (10% 90%) Worst case speed conditions when VCCMin.
VCCQ
Test Points
VCCQ/2
Output
Figure Transient Equivalent Testing Load Circuit
VCCQ
Device Under Test
NOTE: Table component values.
Table Test Configuration Component Values Worst Case Speed Conditions
Test Configuration (pF)
VCCQMin Standard Test
NOTE: includes capacitance.
Figure Clock Input Waveform
R201
R202 R203
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11.6
Device Capacitance
Symbol Unit Condition
COUT
Input Capacitance Output Capacitance Input Capacitance
VOUT
Sampled, 100% tested.
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