28F320J5 28F640J5 (x8/x16) High-Density Symmetrically-Blocked Arc

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

28F320J5 28F640J5 (x8/x16) High-Density Symmetrically-Blocked Arc

Datasheet Thumbnail

Top Searches for this datasheet

Volt Intel StrataFlash® Memory
28F320J5 28F640J5 (x8/x16)
High-Density Symmetrically-Blocked Architecture 128-Kbyte Erase Blocks 128-Kbyte Erase Blocks V-5.5 Operation V-3.6 V-5.5 Capable Read Access Time Read Access Time Enhanced Data Protection Features Absolute Protection with VPEN Flexible Block Locking Block Erase/Program Lockout during Power Transitions Industry-Standard Packaging SSOP Package (32, TSOP Package
Cross-Compatible Command Support Intel Basic Command Common Flash Interface Scalable Command 32-Byte Write Buffer Byte Effective Programming Time 6,400,000 Total Erase Cycles 3,200,000 Total Erase Cycles 100,000 Erase Cycles Block Automation Suspend Options Block Erase Suspend Read Block Erase Suspend Program System Performance Enhancements Status Output Operating Temperature (-40 micron ETOX
process technology parts)
Capitalizing two-bit-per-cell technology, Volt Intel StrataFlash® memory products provide bits space. Offered 64-Mbit (8-Mbyte) 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices first bring reliable, two-bit-per-cell storage technology flash market. Intel StrataFlash memory benefits include: more density less space, lowest cost-per-bit devices, support code data storage, easy migration future devices. Using same NOR-based ETOXtechnology Intel's one-bit-per-cell products, Intel StrataFlash memory devices take advantage million units manufacturing experience since 1988. result, Intel StrataFlash components ideal code data applications where high density cost required. Examples include networking, telecommunications, audio recording, digital imaging. Intel StrataFlash memory components deliver generation forward-compatible software support. using Common Flash Interface (CFI) Scalable Command (SCS), customers take advantage density upgrades optimized write capabilities future Intel StrataFlash memory devices. Manufactured Intel's micron ETOXV process technology Intel's 0.25 micron ETOX process technology, Volt Intel StrataFlash memory provides highest levels quality reliability.
Notice: This document contains information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 290606-015 April 2002
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. 28F320J5 28F640J5 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation 1997-2002. *Other names brands claimed property others.
28F320J5 28F640J5
Contents
Product Overview Principles Operation
Data Protection.11 Read.13 Output Disable.13 Standby Reset/Power-Down Read Query Read Identifier Codes.14 Write Read Array Command.18 Read Query Mode Command 4.2.1 Query Structure Output 4.2.2 Query Structure Overview 4.2.3 Block Status Register 4.2.4 Query Identification String 4.2.5 System Interface Information 4.2.6 Device Geometry Definition.23 4.2.7 Primary-Vendor Specific Extended Query Table.23 Read Identifier Codes Command Read Status Register Command.25 Clear Status Register Command.25 Block Erase Command.26 Block Erase Suspend Command Write Buffer Command.27 Byte/Word Program Commands Configuration Command Block Master Lock-Bit Commands.28 Clear Block Lock-Bits Command.29 Three-Line Output Control.38 Block Erase, Program, Lock-Bit Configuration Polling Power Supply Decoupling Input Signal Transitions Reducing Overshoots Undershoots When Using Buffers/Transceivers VCC, VPEN, Transitions Power-Up/Down Protection Power Dissipation.40 Absolute Maximum Ratings.40
Operation.12
Command Definitions
4.10 4.11 4.12
Design Considerations
Electrical Specifications.40
28F320J5 28F640J5
Operating Conditions Capacitance Characteristics Characteristics-Read-Only Operations Characteristics- Write Operations Block Erase, Program, Lock-Bit Configuration Performance
Ordering Information Additional Information
28F320J5 28F640J5
Revision History
Date Revision 09/01/97 09/17/97 12/01/97 Version -001 -002 -003 Original version Modifications made cover sheet VCC/GND Pins Converted Connects Specification Change added ICCS, ICCD, ICCW ICCE Specification Change added Order Codes Specification Change added µBGA* chip-scale package Figure changed 52-ball package appropriate documentation added. 64-Mb µBGA package dimensions were changed Figure Changed Figure read SSOP instead TSOP. 32-Mbit Intel StrataFlash memory read access time added. number block erase cycles changed. write buffer program time changed. operating temperature changed. read parameter added. Several program, erase, lock-bit specifications were changed. Minor documentation changes were made well. Datasheet designation changed from Advance Information Preliminary. Intel StrataFlash memory 32-Mbit µBGA package removed. tEHEL read specification reduced. Table modified. Ordering Information updated. Removed Mbit, references ordering information same. Provided clearer specifications. Provided maximum program/erase specification. Added Input Signal Transitions-Reducing Overshoots Undershoots When Using Buffers/Transceivers Design Considerations section. Name document changed from Intel® StrataFlashMemory Technology Mbit. Updated Tables, Section 4.2.1-Section 4.2.7. Operating Temperature Range Specification increased +85° 32-Mbit Read Access changed (Section 6.5, Characteristics-Read Only Operations). Modified Write Pulse Width definition Added lock-bit default status (Section 4.11) Added order code information Modified Chip Enable Truth Table Corrected error command table Removed erase queuing option from Figure Block Erase Flowchart reference 0.25 micron process cover page Corrected error Table Maximum buffer write time. Updated section program/erase times. Corrected error table maximum temperature range Changed Clear Block-Lock Time Section 6.7. Added micron ETOX process technology ordering information Removed µBGA information Description
01/31/98
-004
03/23/98
-005
07/13/98 12/01/98
-006 -007
05/04/99 09/16/99
-008 -009
10/20/99
-010
11/08/99 12/16/99 06/26/00
-011 -012 -013
03/28/01 04/23/02
-014 -015
28F320J5 28F640J5
28F320J5 28F640J5
Product Overview
Intel StrataFlash® memory family contains high-density memories organized Mbytes Mwords (64-Mbit) Mbytes Mwords (32-Mbit). These devices accessed 16-bit words. 64-Mbit device organized sixty-four 128-Kbyte (131,072 bytes) erase blocks while 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks selectively individually lockable unlockable in-system. memory Figure page Common Flash Interface (CFI) permits software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward- backwardcompatible software support specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. Scaleable Command (SCS) allows single, simple software driver host systems work with SCS-compliant flash memory devices, independent system-level packaging (e.g., memory card, SIMM, direct-to-board placement). Additionally, provides highest system/device data transfer rates minimizes device system-level implementation costs. Command User Interface (CUI) serves interface between system processor internal operation device. valid command sequence written initiates device automation. internal Write State Machine (WSM) automatically executes algorithms timings necessary block erase, program, lock-bit configuration operations. block erase operation erases device's 128-Kbyte blocks typically within second- independent other blocks. Each block independently erased 100,000 times. Block erase suspend mode allows system software suspend block erase read program data from other block. Each device incorporates Write Buffer bytes words) allow optimum programming performance. using Write Buffer, data programmed buffer increments. This feature improve system program performance times over non-Write Buffer writes. Individual block locking uses combination bits, block lock-bits master lock-bit, lock unlock blocks. Block lock-bits gate block erase program operations while master lockbit gates block lock-bit modification. Three lock-bit configuration operations clear lock-bits (Set Block Lock-Bit, Master Lock-Bit, Clear Block Lock-Bits commands). status register indicates when WSM's block erase, program, lock-bit configuration operation finished. (STATUS) output gives additional indicator activity providing both hardware signal status (versus software polling) status masking (interrupt masking background block erase, example). Status indication using minimizes both overhead system power consumption. When configured level mode (default mode), acts pin. When low, indicates that performing block erase, program, lock-bit configuration. STS-high indicates that ready command, block erase suspended (and programming inactive), device reset/power-down mode. Additionally, configuration command allows configured pulse completion programming and/or block erases.
28F320J5 28F640J5
Three pins used enable disable device. unique logic design (see Table "Chip Enable Truth Table" page reduces decoder logic typically required multi-chip designs. External logic required when designing single chip, dual chip, 4-chip miniature card SIMM module. BYTE# allows either read/writes device. BYTE# logic selects 8-bit mode; address selects between byte high byte. BYTE# logic high enables 16-bit operation; address becomes lowest order address address used (don't care). device block diagram shown Figure When device disabled (see Table page VCC, standby mode enabled. When GND, further power-down mode enabled which minimizes power consumption provides write protection during reset. reset time (tPHQV) required from switching high until outputs valid. Likewise, device wake time (tPHWL) from RP#-high until writes recognized. With GND, reset status register cleared. Intel StrataFlash memory devices available several package types. 64-Mbit available 56-lead SSOP (Shrink Small Outline Package) µBGA* package (micro Ball Grid Array). 32-Mbit available 56-lead TSOP (Thin Small Outline Package) 56-lead SSOP. Figures show pinouts.
Figure Intel StrataFlash® Memory Block Diagram
DQ15
VCCQ
Output Buffer
Input Buffer
Query Output Multiplexer Write Buffer Data Register
Logic Logic
BYTE#
Identifier Register Status Register
Command User Interface
Multiplexer Data Comparator
32-Mbit: 64-Mbit:
Y-Decoder Input Buffer
Y-Gating Write State Machine 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Kbyte Blocks Program/Erase Voltage Switch
VPEN
Address Latch Address Counter
X-Decoder
28F320J5 28F640J5
Table
Symbol
Lead Descriptions
Type INPUT Name Function BYTE-SELECT ADDRESS: Selects between high byte when device mode. This address latched during program cycle. used mode (i.e., input buffer turned when BYTE# high). ADDRESS INPUTS: Inputs addresses during read program operations. Addresses internally latched during program cycle. 32-Mbit: A0-A21 64-Mbit: A0-A22 LOW-BYTE DATA BUS: Inputs data during buffer writes programming, inputs commands during Command User Interface (CUI) writes. Outputs array, query, identifier, status data appropriate read mode. Floated when chip de-selected outputs disabled. Outputs DQ6-DQ0 also floated when Write State Machine (WSM) busy. Check SR.7 (status register determine status. HIGH-BYTE DATA BUS: Inputs data during buffer writes programming operations. Outputs array, query, identifier data appropriate read mode; used status register reads. Floated when chip de-selected, outputs disabled, busy. CHIP ENABLES: Activates device's control logic, input buffers, decoders, sense amplifiers. When device de-selected (see Table page power reduces standby levels. timing specifications same these three signals. Device selection occurs with first edge CE0, CE1, that enables device. Device deselection occurs with first edge CE0, CE1, that disables device (see Table RESET/ POWER-DOWN: Resets internal automation puts device power-down mode. RP#-high enables normal operation. Exit from reset sets device read array mode. When driven low, inhibits write operations which provides data protection during power transitions. enables master lock-bit setting block lock-bits configuration when master lock-bit set. overrides block lock-bits thereby enabling block erase programming operations locked memory blocks. permanently connect VHH. OUTPUT ENABLE: Activates device's outputs through data buffers during read cycle. active low. WRITE ENABLE: Controls writes Command User Interface, Write Buffer, array blocks. active low. Addresses data latched rising edge pulse. STATUS: Indicates status internal state machine. When configured level mode (default mode), acts RY/BY# pin. When configured pulse modes, pulse indicate program and/or erase completion. alternate configurations STATUS pin, Configurations command. VCCQ with pull-up resistor. BYTE ENABLE: BYTE# places device mode. data then input output DQ0-DQ7, while DQ8-DQ15 float. Address selects between high byte. BYTE# high places device mode, turns input buffer. Address then becomes lowest order address. ERASE PROGRAM BLOCK LOCK ENABLE: erasing array blocks, programming data, configuring lock-bits. With VPEN VPENLK, memory contents cannot altered. SUPPLY OUTPUT BUFFER SUPPLY SUPPLY DEVICE POWER SUPPLY: With VLKO, write attempts flash memory inhibited. OUTPUT BUFFER POWER SUPPLY: This voltage controls device's output voltages. obtain output voltages compatible with system data voltages, connect VCCQ system supply voltage. GROUND: float ground pins. CONNECT: Lead internally connected; driven floated.
A1-A22
INPUT
DQ0-DQ7
INPUT/ OUTPUT
DQ8-DQ15
INPUT/ OUTPUT
CE0, CE1,
INPUT
INPUT
INPUT INPUT OPEN DRAIN OUTPUT
BYTE#
INPUT
VPEN VCCQ
INPUT
28F320J5 28F640J5
Figure TSOP Lead Configuration Mbit)
28F160S5 28F016SV 28F032SA 28F320J5 28F016SA 3/5# 3/5# VPEN 28F320J5 DQ15 DQ14 DQ13 DQ12 VCCQ DQ11 DQ10 BYTE# 28F032SA 28F016SV 28F160S5 28F016SA RY/BY# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 BYTE# RY/BY# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 BYTE# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 BYTE#
Intel StrataFlash Memory 56-Lead TSOP Standard Pinout View
Highlights pinout changes
NOTES: (Pin (Pin internally connected. future device revisions, recommended that these pins connected their respected power supplies (i.e., GND). compatibility with future generations Intel StrataFlash® memory, this (pin should connected GND.
Figure SSOP Lead Configuration Mbit Mbit)
28F016SA 28F160S5 28F320S5 28F016SV CE0# 3/5# CE1# DQ14 DQ15 RY/BY# DQ13 DQ12 CE0# CE1# DQ14 DQ15 RY/BY# DQ13 DQ12 CE0# CE1# DQ14 DQ15 RY/BY# DQ13 DQ12 28F640J5 DQ14 DQ15 DQ13 DQ12 VCCQ 28F320J5 DQ14 DQ15 DQ13 DQ12 VCCQ Intel StrataFlash Memory 56-Lead SSOP Standard Pinout 23.7 View 28F320J5 VPEN BYTE# DQ10 DQ11 28F640J5 28F320S5 28F160S5 28F016SA 28F016SV VPEN BYTE# DQ10 DQ11 BYTE# DQ10 DQ11 BYTE# DQ10 DQ11 BYTE# DQ10 DQ11
Highlights pinout changes.
NOTES: (Pin (Pin internally connected. future device revisions, recommended that these pins connected their respected power supplies (i.e., GND). compatibility with future generations Intel StrataFlash® memory, this (pin should connected GND.
28F320J5 28F640J5
Principles Operation
Intel StrataFlash memory devices include on-chip manage block erase, program, lock-bit configuration functions. allows 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, minimal processor overhead with RAM-like interface timings. After initial device power-up return from reset/power-down mode (see Operations), device defaults read array mode. Manipulation external memory control pins allows array read, standby, output disable operations. Read array, status register, query, identifier codes accessed through (Command User Interface) independent VPEN voltage. VPENH VPEN enables successful block erasure, programming, lock-bit configuration. functions associated with altering memory contents-block erase, program, lock-bit configuration-are accessed verified through status register. Commands written using standard micro-processor write timings. contents serve input WSM, which controls block erase, program, lock-bit configuration. internal algorithms regulated WSM, including pulse repetition, internal verification, margining data. Addresses data internally latched during program cycles. Interface software that initiates polls progress block erase, program, lock-bit configuration stored block. This code copied executed from system during flash memory updates. After successful completion, reads again possible Read Array command. Block erase suspend allows system software suspend block erase read program data from/to other block.
Data Protection
Depending application, system designer choose make VPEN switchable (available only when memory block erases, programs, lock-bit configurations required) hardwired VPENH. device accommodates either design practice encourages optimization processor-memory interface. When VPEN VPENLK, memory contents cannot altered. CUI's two-step block erase, byte/ word program, lock-bit configuration command sequences provide protection from unwanted operations even when VPENH applied VPEN. program functions disabled when below write lockout voltage VLKO when VIL. device's block locking capability provides additional protection from inadvertent code data alteration gating erase program operations.
28F320J5 28F640J5
Operation
local reads writes flash memory in-system. cycles from flash memory conform standard microprocessor cycles.
Figure Memory
[22-0]: 64-Mbit [21-0]: 32-Mbit
7FFFFF
[22-1]: 64-Mbit [21-1]: 32-Mbit
3FFFFF
128-Kbyte Block
7E0000
3F0000
64-Kword Block
128-Kbyte Block
3E0000
1F0000
64-Kword Block
03FFFF
01FFFF
128-Kbyte Block
020000 01FFFF
010000 00FFFF 000000
64-Kword Block 64-Kword Block
128-Kbyte Block
000000
Byte-Wide (x8) Mode
Word Wide (x16) Mode
Table
Chip Enable Truth Table
DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTES: Application Note, AP-647 Volt Intel StrataFlash® Memory Design Guide typical configurations. single-chip applications strapped GND.
32-Mbit
64-Mbit
3FFFFF
1FFFFF
28F320J5 28F640J5
Read
Information read from block, query, identifier codes, status register independent VPEN voltage. either VHH. Upon initial device power-up after exit from reset/power-down mode, device automatically resets read array mode. Otherwise, write appropriate read mode command (Read Array, Read Query, Read Identifier Codes, Read Status Register) CUI. control pins dictate data flow component: CE0, CE1, CE2, OE#, WE#, RP#. device must enabled (see Table must driven active obtain data outputs. CE0, CE1, device selection controls and, when enabled (see Table select memory device. data output (DQ0-DQ15) control and, when active, drives selected memory data onto bus. must VIH.
Output Disable
With logic-high level (VIH), device outputs disabled. Output pins DQ0-DQ15 placed high-impedance state.
Standby
CE0, CE1, disable device (see Table place standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs placed highimpedance state independent OE#. deselected during block erase, program, lock-bit configuration, continues functioning, consuming active power until operation completes.
Reset/Power-Down
initiates reset/power-down mode. read modes, RP#-low deselects memory, places output drivers high-impedance state, turns numerous internal circuits. must held minimum tPLPH. Time tPHQV required after return from reset mode until initial memory access outputs valid. After this wakeup interval, normal operation restored. reset read array mode status register 80H. During block erase, program, lock-bit configuration modes, RP#-low will abort operation. default mode, transitions remains maximum time tPLPH tPHRH until reset operation complete. Memory contents being altered longer valid; data partially corrupted after program partially altered after erase lock-bit configuration. Time tPHWL required after goes logic-high (VIH) before another command written. with automated device, important assert during system reset. When system comes reset, expects read from flash memory. Automated flash memories provide status information when accessed during block erase, program, lock-bit configuration modes. reset occurs with flash memory reset, proper initialization occur because
28F320J5 28F640J5
flash memory providing status information instead array data. Intel® Flash memories allow proper initialization following system reset through input. this application, controlled same RESET# signal that resets system CPU.
Read Query
read query operation outputs block status information, (Common Flash Interface) string, system interface information, device geometry information, Intel-specific extended query information.
Read Identifier Codes
read identifier codes operation outputs manufacturer code, device code, block lock configuration codes each block, master lock configuration code (see Figure Using manufacturer device codes, system automatically match device with proper algorithms. block lock master lock configuration codes identify locked unlocked blocks master lock-bit setting.
28F320J5 28F640J5
Figure Device Identifier Code Memory
Word Address 3FFFFF A[22-1]: Mbit A[21-1]: Mbit Block Reserved Future Implementation Block Lock Configuration Reserved Future Implementation (Blocks through Block Reserved Future Implementation 1F0003 1F0002 Block Lock Configuration Mbit Mbit Reserved Future Implementation (Blocks through Block Reserved Future Implementation Block Lock Configuration Reserved Future Implementation Block Reserved Future Implementation Master Lock Configuration Block Lock Configuration Device Code Manufacturer Code
3F0003 3F0002
3F0000 3EFFFF
1F0000 1EFFFF 01FFFF
010003 010002
010000 00FFFF
000004 000003 000002 000001 000000
NOTE: used either modes when obtaining these identifier codes. Data always given byte mode (upper byte contains 00h).
28F320J5 28F640J5
Write
Writing commands enables reading device data, query, identifier codes, inspection clearing status register, and, when VPEN VPENH, block erasure, program, lock-bit configuration. Block Erase command requires appropriate command data address within block erased. Byte/Word Program command requires command address location written. Master Block Lock-Bit commands require command address within device (Master Lock) block within device (Block Lock) locked. Clear Block LockBits command requires command address within device. does occupy addressable memory location. written when device enabled active. address data needed execute command latched rising edge first edge CE0, CE1, that disables device (see Table page 12). Standard microprocessor write timings used.
Table
Mode Read Array Output Disable Standby Reset/PowerDown Mode Read Identifier Codes Read Query Read Status (WSM off) Read Status (WSM Write
Operations
Notes 4,5,6 6,10,11 CE0,1,2(1) Enabled Enabled Disabled Enabled Enabled Enabled Enabled Enabled OE#(2) WE#(2) Address Figure Table VPEN VPENH DQ(3) DOUT High High High Note Note DOUT DOUT DQ15-8 High DQ6-0 High (default mode) High Z(7) High Z(7) High Z(7) High Z(7)
NOTES: Table valid configurations. should never enabled simultaneously. refers DQ0-DQ7 BYTE# DQ0-DQ15 BYTE# high. Refer Characteristics. When VPEN VPENLK, memory contents read, altered. control address pins, VPENLK VPENH VPEN. Characteristics VPENLK VPENH voltages. default mode, when executing internal block erase, program, lock-bit configuration algorithms. when busy, block erase suspend mode (with programming inactive), reset/power-down mode. High will with external pull-up resistor. Read Identifier Codes Command section read identifier code data. Read Query Mode Command section read query data. 10.Command writes involving block erase, program, lock-bit configuration reliably executed when VPEN VPENH within specification. Block erase, program, lock-bit configuration with produce spurious results should attempted. 11.Refer Table valid during write operation.
28F320J5 28F640J5
Command Definitions
When VPEN voltage VPENLK, only read operations from status register, query, identifier codes, blocks enabled. Placing VPENH VPEN additionally enables block erase, program, lock-bit configuration operations. Device operations selected writing specific commands into CUI. Table defines these commands.
Table
Command
Intel StrataFlash® Memory Command Definitions(1,2)
Scaleable Basic Command Set(2) Cycles Req'd. Notes First Cycle Second Cycle
Oper(3) Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write Buffer Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Read Configuration Block LockBit Clear Block Lock-Bits Protection Program SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS 12,13 11,12 12,14 Write Write Write Write Write Write
Addr(4)
Data(5,6)
Oper(3)
Addr(4)
Data(5,6)
Read Read Read
Write
SCS/BCS SCS/BCS SCS/BCS
Write Write Write
Write Write
SCS/BCS
Write Write Write Write
Write Write Write Write Write
Write Write
NOTES: Commands other than those shown above reserved Intel future device implementations should used. running, only valid; DQ15-DQ8 DQ6-DQ0 float, which places them highimpedance state.
28F320J5 28F640J5
Basic Command (BCS) same 28F008SA Command Intel Standard Command Set. Scaleable Command (SCS) also referred Intel Extended Command Set. operations defined Table valid address within device. Address within block. Identifier Code Address: Figure Table Query database Address. Address memory location programmed. Data read from Identifier Codes. Data read from Query database. Data read from status register. Table description status register bits. Data programmed location Data latched rising edge WE#. Configuration Code. upper byte data (DQ8-DQ15) during command writes "Don't Care" operation. Following Read Identifier Codes command, read operations access manufacturer, device, block lock, master lock codes. Read Identifier Codes Command section read identifier code data. After Write Buffer command issued check make sure buffer available writing. 10.The number bytes/words written Write Buffer where byte/word count argument. Count ranges this device byte mode word mode 0000H 000FH. third consecutive cycles, determined writing data into Write Buffer. Confirm command (D0H) expected after exactly write cycles; other command that point sequence aborts write buffer operation. Please Figure "Write Buffer Flowchart" page additional information. 11.Programming write buffer flash initiating erase operation does begin until confirm command (D0h) issued. 12.If block locked, must enable block erase program operations. Attempts issue block erase program locked block while will fail. 13.Either recognized byte/word program setup. 14.If master lock-bit set, must block lock-bit. must master lock-bit. master lock-bit set, block lock-bit while VIH. 15.If master lock-bit set, must clear block lock-bits. clear block lock-bits operation simultaneously clears block lock-bits. master lock-bit set, Clear Block Lock-Bits command done while VIH.
Read Array Command
Upon initial device power-up after exit from reset/power-down mode, device defaults read array mode. This operation also initiated writing Read Array command. device remains enabled reads until another command written. Once internal started block erase, program, lock-bit configuration, device will recognize Read Array command until completes operation unless suspended Erase Suspend command. Read Array command functions independently VPEN voltage VHH.
Read Query Mode Command
This section defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
28F320J5 28F640J5
4.2.1
Query Structure Output
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (DQ0-DQ7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (DQ0-DQ7) high byte (DQ8-DQ15). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode.
Table
Summary Query Structure Output Function Device Mode
Device Type/ Mode Query start location maximum device width addresses Query data with maximum device width addressing Offset device mode device mode Code 0051 0052 0059 N/A(1 ASCII Value Query data with byte addressing Offset Code ASCII Value "Null"
N/A(1)
NOTE: system must drive lowest order addresses access device's array data when device configured mode. Therefore, word addressing, where these lower addresses toggled system, "Not Applicable" x8-configured devices.
28F320J5 28F640J5
Table
Example Query Structure Output x16- x8-Capable Device
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI Code D15-D0 PrVendor PrVendor TblAdr AltVendor Value Offset A7-A0 P_IDLO P_IDLO P_IDHI Byte Addressing Code D7-D0 PrVendor Value
4.2.2
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." AP-646 Common Flash Interface (CFI) Command Sets (order number 292204) full description CFI. following sections describe Query structure sub-sections detail.
Table
Query Structure(1)
Offset (BA+2)h(2) 04-0Fh P(3) Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Manufacturer Code Device Code Block-Specific Information Reserved Vendor-Specific Information Reserved Vendor-Specific Information Command Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm Description
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. Block Address beginning location (i.e., 02000h block beginning location when block size Kbyte). Offset defines which points Primary Intel-Specific Extended Query Table.
28F320J5 28F640J5
4.2.3
Block Status Register
Block Status Register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations. Block Erase Status (BSR.1) allows system software determine success last block erase operation. BSR.1 used just after power-up verify that supply accidentally removed during erase operation. This only reset issuing another erase operation block. Block Status Register accessed from word address within each block.
Table
Block Status Register
Offset (BA+2)h(1) Length Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked BSR.1 Block Erase Status Last erase operation completed successfully Last erase operation complete successfully 2-7: Reserved Future Address BA+2: BA+2: Value (bit
BA+2: BA+2:
(bit (bit 2-7):
NOTE: beginning location Block Address (i.e., 008000h block (64-KB block) beginning location word mode).
4.2.4
Query Identification String
Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table
Identification
Offset Length Description Query-unique ASCII string "QRY" Add. Code Value
Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code. 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
28F320J5 28F640J5
4.2.5
System Interface Information
following device information optimize system interface software.
Table System Interface Information
Offset Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical
Add.
Code
Value
28F320J5 28F640J5
4.2.6
Device Geometry Definition
This field provides critical details flash device geometry.
Table Device Geometry Definition
Offset Length Description such that device size number bytes Flash device interface: async async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 such that maximum number bytes write buffer
Code Table Below
Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes
Table Device Geometry Definition
Address Mbit Mbit Mbit (Info Only
4.2.7
Primary-Vendor Specific Extended Query Table
Certain flash features commands optional. Primary Vendor-Specific Extended Query table specifies this other similar information.
28F320J5 28F640J5
Table Primary Vendor-Specific Extended Query
Offset(1) (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Length Description (Optional Flash Features Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts Reserved Future Add. Code Value
(P+9)h
(P+A)h (P+B)h
(P+C)h
(P+D)h (P+E)h
NOTE: variable pointer which defined offset 15h.
Read Identifier Codes Command
identifier code operation initiated writing Read Identifier Codes command. Following command write, read cycles from addresses shown Figure retrieve manufacturer, device, block lock configuration master lock configuration codes (see Table identifier code values). terminate operation, write another valid command. Like Read Array command, Read Identifier Codes command functions independently VPEN voltage VHH. This command valid only when device suspended. Following Read Identifier Codes command, following information read:
28F320J5 28F640J5
Table Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit Block Lock Configuration Block Unlocked Block Locked Reserved Future Master Lock Configuration Device Unlocked Device Locked Reserved Future 00003 DQ1-7 Address(1) 00000 00001 00001
X0002(2)
Data (00) (00) (00) DQ1-7
NOTES: used either modes when obtaining identifier codes. lowest order address line Data always presented byte mode (upper byte contains 00h). selects specific block's lock configuration code. Figure device identifier code memory map.
Read Status Register Command
status register read determine when block erase, program, lock-bit configuration complete whether operation completed successfully. read time writing Read Status Register command. After writing this command, subsequent read operations output data from status register until another valid command written. status register contents latched falling edge first edge CE0, CE1, that enables device (see Table must toggle device must disabled (Table before further reads update status register latch. Read Status Register command functions independently VPEN voltage. VHH. During program, block erase, lock-bit, clear lock-bit command sequence, only SR.7 valid until completes suspends operation. Device pins DQ0-DQ6 DQ8-DQ15 placed high-impedance state. When operation completes suspends (check status register contents status register valid when read.
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, SR.1 "1"s only reset Clear Status Register command. These bits indicate various failure conditions (see Table 16). allowing system software reset these bits, several operations (such cumulatively erasing locking multiple blocks writing several bytes sequence) performed. status register polled determine error occurred during sequence. clear status register, Clear Status Register command (50H) written. functions independently applied VPEN voltage. VHH. Clear Status Register command only valid when device suspended.
28F320J5 28F640J5
Block Erase Command
Erase executed block time initiated two-cycle command. block erase setup first written, followed block erase confirm. This command sequence requires appropriate address within block erased (erase changes block data FFH). Block preconditioning, erase, verify handled internally (invisible system). After two-cycle block erase sequence written, device automatically outputs status register data when read (see Figure "Block Erase Flowchart" page 34). detect block erase completion analyzing output status register SR.7. Toggle OE#, CE0, CE1, update status register. When block erase complete, status register SR.5 should checked. block erase error detected, status register should cleared before system software attempts corrective actions. remains read status register mode until command issued. This two-step command sequence set-up followed execution ensures that block contents accidentally erased. invalid Block Erase command sequence will result both status register bits SR.4 SR.5 being "1." Also, reliable block erasure only occur when valid VPEN VPENH. block erase attempted while VPEN VPENLK, SR.3 SR.5 will "1." Successful block erase requires that corresponding block lock-bit cleared set, that VHH. block erase attempted when corresponding block lock-bit VIH, SR.1 SR.5 will "1." Block erase operations with produce spurious results should attempted.
Block Erase Suspend Command
Block Erase Suspend command allows block-erase interruption read program data another block memory. Once block erase process starts, writing Block Erase Suspend command requests that suspend block erase sequence predetermined point algorithm. device outputs status register data when read after Block Erase Suspend command written. Polling status register SR.7 then SR.6 determine when block erase operation been suspended (both will "1"). default mode, will also transition VOH. Specification tWHRH defines block erase suspend latency. this point, Read Array command written read data from blocks other than that which suspended. program command sequence also issued during erase suspend program data other blocks. During program operation with block erase suspended, status register SR.7 will return output default mode) will transition VOL. only other valid commands while block erase suspended Read Query, Read Status Register, Clear Status Register, Configure, Block Erase Resume. After Block Erase Resume command written flash memory, will continue block erase process. Status register bits SR.6 SR.7 will automatically clear default mode) will return VOL. After Erase Resume command written, device automatically outputs status register data when read (see Figure "Block Erase Suspend/Resume Flowchart" page 35). VPEN must remain VPENH (the same VPEN level used block erase) while block erase suspended. must also remain (the same level used block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed.
28F320J5 28F640J5
Write Buffer Command
program flash device, Write Buffer command sequence initiated. variable number bytes, buffer size, loaded into buffer written flash device. First, Write Buffer setup command issued along with Block Address (see Figure "Write Buffer Flowchart" page 32). this point, eXtended Status Register (XSR, Table "Status Register Definition" page information loaded XSR.7 reverts "buffer available" status. XSR.7 write buffer available. retry, continue monitoring XSR.7 issuing Write Buffer setup command with Block Address until XSR.7 When XSR.7 transitions "1," buffer ready loading. word/byte count given part with Block Address. next write, device start address given along with write buffer data. Subsequent writes provide additional device addresses data, depending count. subsequent addresses must within start address plus count. Internally, this device programs many flash cells parallel. Because this parallel programming, maximum programming performance lower power obtained aligning start address beginning write buffer boundary (i.e., A4-A0 start address After final buffer data given, Write Confirm command issued. This initiates (Write State Machine) begin copying buffer data flash array. command other than Write Confirm written device, "Invalid Command/Sequence" error will generated status register bits SR.5 SR.4 will "1." additional buffer writes, issue another Write Buffer setup command check XSR.7. error occurs while writing, device will stop writing, status register SR.4 will indicate program failure. internal verify only detects errors "1"s that successfully program "0"s. program error detected, status register should cleared. time SR.4 and/or SR.5 (e.g., media failure occurs during program erase), device will accept more Write Buffer commands. Additionally, user attempts program past erase block boundary with Write Buffer command, device will abort write buffer operation. This will generate "Invalid Command/Sequence" error status register bits SR.5 SR.4 will "1." Reliable buffered writes only occur when VPEN VPENH. buffered write attempted while VPEN VPENLK, status register bits SR.4 SR.3 will "1." Buffered write attempts with invalid VPEN voltages produce spurious results should attempted. Finally, successful programming requires that corresponding Block Lock-Bit reset set, that VHH. buffered write attempted when corresponding Block Lock-Bit VIH, SR.1 SR.4 will "1." Buffered write operations with produce spurious results should attempted.
Byte/Word Program Commands
Byte/Word program executed two-cycle command sequence. Byte/Word program setup (standard alternate 10H) written followed second write that specifies address data (latched rising edge WE#). then takes over, controlling program program verify algorithms internally. After program sequence written, device automatically outputs status register data when read (see Figure "Byte/Word Program Flowchart" page 33). detect completion program event analyzing status register SR.7.
28F320J5 28F640J5
When program complete, status register SR.4 should checked. program error detected, status register should cleared. internal verify only detects errors "1"s that successfully program "0"s. remains read status register mode until receives another command. Reliable byte/word programs only occur when VPEN valid. byte/word program attempted while VPEN VPENLK, status register bits SR.4 SR.3 will "1." Successful byte/word programs require that corresponding block lock-bit cleared set, that VHH. byte/word program attempted when corresponding block lock-bit VIH, SR.1 SR.4 will "1." Byte/word program operations with produce spurious results should attempted.
4.10
Configuration Command
Status (STS) configured different states using Configuration command. Once been configured, remains that configuration until another configuration command issued asserted low. Initially, defaults RY/BY# operation where RY/BY# indicates that state machine busy. RY/BY# high indicates that state machine ready operation suspended. Table "Write Protection Alternatives" page displays possible configurations. reconfigure Status (STS) other modes, Configuration command given followed desired configuration code. three alternate configurations pulse mode system interrupt described below. these configurations, controls Erase Complete interrupt pulse, controls Program Complete interrupt pulse. Supplying configuration code with Configuration command resets default RY/BY# level mode. possible configurations their usage described Table Configuration command only given when device busy suspended. Check SR.7 device status. invalid configuration code will result both status register bits SR.4 SR.5 being "1." When configured pulse modes, pulses with typical pulse width
4.11
Block Master Lock-Bit Commands
flexible block locking unlocking scheme enabled combination block lock-bits master lock-bit. factory, block lock-bits master lock-bit unlocked. block lock-bits gate program erase operations while master lock-bit gates block-lock modification. With master lock-bit set, individual block lock-bits using Block Lock-Bit command. Master Lock-Bit command, conjunction with VHH, sets master lock-bit. After master lock-bit set, subsequent setting block lock-bits requires both Block Lock-Bit command pin. These commands invalid while running device suspended. Table "Identifier Codes" page summary hardware software write protection options. block lock-bit master lock-bit commands executed two-cycle sequence. block master lock-bit setup along with appropriate block device address written followed either block lock-bit confirm (and address within block locked) master lock-bit confirm (and device address). then controls lock-bit algorithm. After sequence written, device automatically outputs status register data when read (see Figure "Set Block Lock-Bit Flowchart" page 36). detect completion lock-bit event analyzing output status register SR.7.
28F320J5 28F640J5
When lock-bit operation complete, status register SR.4 should checked. error detected, status register should cleared. will remain read status register mode until command issued. This two-step sequence set-up followed execution ensures that lock-bits accidentally set. invalid Block Master Lock-Bit command will result status register bits SR.4 SR.5 being "1." Also, reliable operations occur only when VPEN valid. With VPEN VPENLK, lock-bit contents protected against alteration. successful block lock-bit operation requires that master lock-bit zero master lock-bit set, that VHH. attempted with master lock-bit VIH, SR.1 SR.4 will operation will fail. block lock-bit operations while produce spurious results should attempted. successful master lock-bit operation requires that VHH. attempted with VIH, SR.1 SR.4 will operation will fail. master lock-bit operations with produce spurious results should attempted.
4.12
Clear Block Lock-Bits Command
block lock-bits cleared parallel Clear Block Lock-Bits command. With master lock-bit set, block lock-bits cleared using only Clear Block Lock-Bits command. master lock-bit set, clearing block lock-bits requires both Clear Block LockBits command pin. This command invalid while running device suspended. Table "Identifier Codes" page summary hardware software write protection options. Clear block lock-bits command executed two-cycle sequence. clear block lock-bits setup first written. device automatically outputs status register data when read (see Figure "Clear Block Lock-Bit Flowchart" page 37). detect completion clear block lock-bits event analyzing output status register SR.7. When operation complete, status register SR.5 should checked. clear block lock-bit error detected, status register should cleared. will remain read status register mode until another command issued. This two-step sequence set-up followed execution ensures that block lock-bits accidentally cleared. invalid Clear Block Lock-Bits command sequence will result status register bits SR.4 SR.5 being "1." Also, reliable clear block lock-bits operation only occur when VPEN valid. clear block lock-bits operation attempted while VPEN VPENLK, SR.3 SR.5 will "1." successful clear block lock-bits operation requires that master lock-bit master lock-bit set, that VHH. attempted with master lock-bit VIH, SR.1 SR.5 will operation will fail. clear block lock-bits operation with produce spurious results should attempted. clear block lock-bits operation aborted VPEN transitioning valid range active transition, block lock-bit values left undetermined state. repeat clear block lock-bits required initialize block lock-bit contents known values. Once master lock-bit set, cannot cleared.
28F320J5 28F640J5
Table Write Protection Alternatives
Operation Block Erase Program Master Lock-Bit Block Lock-Bit Clear Block Lock-Bits Master Lock-Bit Effect Block Erase Program Enabled Block Locked. Block Erase Program Disabled Block Lock-Bit Override. Block Erase Program Enabled Clear Block Lock-Bit Enabled Master Lock-Bit Set. Clear Block Lock-Bit Disabled Master Lock-Bit Override. Clear Block Lock-Bit Enabled Master Lock-Bit Disabled Master Lock-Bit Enabled
Table Configuration Coding Definitions
Reserved Pulse Program Complete(1) DQ7-DQ2 reserved future use. default (DQ1-DQ0 RY/BY#, level mode used control HOLD memory controller prevent accessing flash memory subsystem while flash device's busy. configuration INT, pulse mode used generate system interrupt pulse when flash device array completed Block Erase sequence Queued Block Erases. Helpful reformatting blocks after file system free space reclamation "cleanup" configuration INT, pulse mode used generate system interrupt pulse when flash device array complete Program operation. Provides highest performance servicing continuous buffer write operations. configuration ER/PR INT, pulse mode used generate system interrupts trigger servicing flash arrays when either erase program operations completed when common interrupt service routine desired. Pulse Erase Complete(1)
Bits DQ7-DQ2 Reserved DQ1-DQ0 Configuration Codes default, level mode RY/BY# (device ready) indication pulse Erase complete pulse Program complete pulse Erase Program Complete Configuration Codes 01b, 10b, pulse mode such that pulses then high when operation indicated given configuration completed. Configuration Command Sequences configuration (masking bits DQ7-DQ2 00h) follows: Default RY/BY# level mode: B8h, (Erase Interrupt): B8h, Pulse-on-Erase Complete (Program Interrupt): B8h, Pulse-on-Program Complete ER/PR (Erase Program Interrupt): B8h, Pulse-on-Erase Program Complete
NOTE: When device configured pulse modes, pulses with typical pulse width
28F320J5 28F640J5
Table Status Register Definition
WSMS High When Busy? ECLBS PSLBS VPENS Notes Check SR.7 determine block erase, program, lock-bit configuration completion. SR.6-SR.0 driven while SR.7 "0." both SR.5 SR.4 "1"s after block erase lock-bit configuration attempt, improper command sequence entered. SR.3 does provide continuous programming voltage level indication. interrogates indicates programming voltage level only after Block Erase, Program, Block/Master Lock-Bit, Clear Block Lock-Bits command sequences. SR.1 does provide continuous indication master block lock-bit values. interrogates master lock-bit, block lock-bit, only after Block Erase, Program, Lock-Bit configuration command sequences. informs system, depending attempted operation, block lock-bit set, master lock-bit set, and/or VHH. Read block lock master lock configuration codes using Read Identifier Codes command determine master block lock-bit status. SR.2 SR.0 reserved future should masked when polling status register.
Status Register Bits SR.7 WRITE STATE MACHINE STATUS Ready Busy SR.6 ERASE SUSPEND STATUS Block Erase Suspended Block Erase Progress/Completed SR.5 ERASE CLEAR LOCK-BITS STATUS Error Block Erasure Clear Lock-Bits Successful Block Erase Clear Lock-Bits SR.4 PROGRAM LOCK-BIT STATUS Error Programming Master/Block Lock-Bit Successful Programming Master/Block Lock SR.3 PROGRAMMING VOLTAGE STATUS Programming Voltage Detected, Operation Aborted Programming Voltage SR.2 RESERVED FUTURE ENHANCEMENTS SR.1 DEVICE PROTECT STATUS Master Lock-Bit, Block Lock-Bit and/or Lock Detected, Operation Abort Unlock SR.0 RESERVED FUTURE ENHANCEMENTS
Table eXtended Status Register Definition
High When Busy? Status Register Bits XSR.7 WRITE BUFFER STATUS Write buffer available Write buffer available XSR.6-XSR.0 RESERVED FUTURE ENHANCEMENTS Reserved bits Notes After Buffer-Write command, XSR.7 indicates that Write Buffer available. SR.6-SR.0 reserved future should masked when polling status register.
28F320J5 28F640J5
Figure Write Buffer Flowchart
Start Time-Out Issue Write Buffer Command E8H, Block Address Read Extended Status Register Operation Write Read
Command Write Buffer
Comments Data Block Address XSR. Valid Addr Block Address Check XSR. Write Buffer Available Write Buffer Available Data Word/Byte Count Corresponds Count Addr Block Address Data Write Buffer Data Addr Device Start Address Data Write Buffer Data Addr Device Address
Standby
XSR.7 Write Word Byte Count, Block Address Write Buffer Data, Start Address Check Abort Write Buffer Command? Write Next Buffer Data, Device Address X=X+1 Program Buffer Flash Confirm
Write Buffer Time-Out?
Write (Note Write (Note Write (Note Write Program Buffer Flash Confirm
Data Addr Block Address Status Register Data with Device Enabled, Updates Addr Block Address Check SR.7 Ready Busy
Read (Note
Standby Write Another Block Address
Write Buffer Aborted
Byte word count values loaded into count register. Count ranges this device byte mode word mode 0000H 000FH. device outputs status register when read (XSR longer available). Write Buffer contents will programmed device start address destination flash address. Align start address Write Buffer boundary maximum programming performance (i.e., start address device aborts Write Buffer command current address outside original block address. status register indicates "improper command sequence" Write Buffer command aborted. Follow this with Clear Status Register command. Toggling (low high low) updates status register. This done place issuing Read Status Register command. Full status check done after erase write sequences complete. Write after last operation reset device read array mode.
Another Write Buffer? Read Status Register SR.7 Full Status Check Desired Programming Complete Issue Read Status Command
0606_07
28F320J5 28F640J5
Figure Byte/Word Program Flowchart
Start
Operation Write Write
Command Setup Byte/ Word Program Byte/Word Program
Comments Data Addr Location Programmed Data Data Programmed Addr Location Programmed Status Register Data Check SR.7 Ready Busy
Write 40H, Address Write Data Address Read Status Register
Read (Note Standby
SR.7 Full Status Check Desired Byte/Word Program Complete
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. full status check done after each program operation, after sequence programming operations. Write after last program operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.1 SR.4 Byte/Word Program Successful Programming Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.1 Device Protect Detect Block Lock-Bit Only required systems implemeting lock-bit configuration. Check SR.4 Programming Error
Device Protect Error
Standby
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. SR.4, SR.3 SR.1 only cleared Clear Status Register command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
0606_08
28F320J5 28F640J5
Figure Block Erase Flowchart
Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note
Start
Command Erase Block Erase Confirm
Comments Data Addr Block Address Data Addr Status register data With device enabled, updates Addr Check SR.7 Ready Busy
Read
Standby Write Confirm Block Address
Erase Confirm byte must follow Erase Setup. This device does support erase queuing. Please Application note AP-646 software erase queuing compatibility. Full status check done after erase write sequences complete. Write after last operation reset device read array mode. Suspend Erase Loop
Read Status Register
SR.7
Suspend Erase
Full Status Check Desired
Erase Flash Block(s) Complete
0606_09
28F320J5 28F640J5
Figure Block Erase Suspend/Resume Flowchart
Start
Operation Write
Command Erase Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Block Erase Suspended Block Erase Completed
Write Read
Read Status Register
Standby
SR.7
Standby
Write SR.6 Block Erase Completed
Erase Resume
Data Addr
Read Read Program? Read Array Data Done? Write Write Program Loop Program
Block Erase Resumed
Read Array Data
0606_10
28F320J5 28F640J5
Figure Block Lock-Bit Flowchart
Start
Operation Write
Command Block/Master Lock-Bit Setup
Comments Data Addr =Block Address (Block), Device Address (Master) Data (Block) (Master) Addr Block Address (Block), Device Address (Master) Status Register Data Check SR.7 Ready Busy
Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address
Write
Block Master Lock-Bit Confirm
Read Status Register
Read
Standby
SR.7 Full Status Check Desired
Repeat subsequent lock-bit operations. Full status check done after each lock-bit operation after sequence lock-bit operations Write after last lock-bit operation place device read array mode.
Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.4 Lock-Bit Successful
0606_11
Operation Standby
Command
Comments Check SR.3 Programming Voltage Error Detect Check SR.1 Device Protect (Set Master Lock-Bit Operation) Master Lock-Bit (set Block Lock-Bit Operation) Check SR.4, Both Command Sequence Error Check SR.4 Lock-Bit Error
Voltage Range Error
Standby
Device Protect Error
Standby
Command Sequence Error
Standby
Lock-Bit Error
SR.5, SR.4, SR.3 SR.1 only cleared Clear Status Register command, cases where multiple lock-bits before full status checked. error detected, clear status register before attempting retry other error recovery.
28F320J5 28F640J5
Figure Clear Block Lock-Bit Flowchart
Start
Operation Write
Command Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
Comments Data Addr Data Addr Status Register Data Check SR.7 Ready Busy
Write
Write
Write
Read
Read Status Register
Standby
SR.7 Full Status Check Desired Clear Block Lock-Bits Complete
Write after clear lock-bits operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 Clear Block Lock-Bits Successful
0606_12
Operation Standby
Command
Comments Check SR.3 Programming Voltage Error Detect Check SR.1 Device Protect Master Lock-Bit Check SR.4, Both Command Sequence Error Check SR.5 Clear Block Lock-Bits Error
Voltage Range Error
Standby
Device Protect Error
Standby
Standby
Command Sequence Error
SR.5, SR.4, SR.3 SR.1 only cleared Clear Status Register command. error detected, clear status register before attempting retry other error recovery.
Clear Block Lock-Bits Error
28F320J5 28F640J5
Design Considerations
Three-Line Output Control
device will often used large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, RP#) accommodate multiple memory connections. This control provides for:
Lowest possible memory power dissipation. Complete assurance that data contention will occur.
these control inputs efficiently, address decoder should enable device (see Table while should connected memory devices system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices standby mode. should connected system POWERGOOD signal prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
Block Erase, Program, Lock-Bit Configuration Polling
open drain output that should connected VCCQ pull-up resistor provide hardware method detecting block erase, program, lock-bit configuration completion. default mode, transitions after block erase, program, lock-bit configuration commands returns High when finished executing internal algorithm. alternate configurations pin, Configuration command. connected interrupt input system controller. active times. STS, default mode, also High when device block erase suspend (with programming inactive) reset/power-down mode.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers interested three supply current issues; standby current levels, active current levels transient peaks produced falling rising edges CE0, CE1, CE2, OE#. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from three pins (these devices include pin), recommended that systems without separate power ground planes attach ceramic capacitor between each device's three pins (this includes VCCQ) ground. These high-frequency, low-inductance capacitors should placed close possible package leads each Intel StrataFlash memory device. Each device should have ceramic capacitor connected between GND. These high-frequency, inductance capacitors should placed close possible package leads. Additionally, every eight devices, electrolytic capacitor should placed between array's power supply connection. bulk capacitor will overcome voltage slumps caused board trace inductance.
28F320J5 28F640J5
Input Signal Transitions Reducing Overshoots Undershoots When Using Buffers/Transceivers
faster, high-drive devices such transceivers buffers drive input signals flash memory devices, overshoots undershoots sometimes cause input signals exceed flash memory specifications (see Section 6.1, Absolute Maximum Ratings). Many buffer/transceiver vendors carry bus-interface devices with internal output-damping resistors reduced-drive outputs. Internal output-damping resistors diminish nominal output drive currents, while still leaving sufficient drive capability most applications. These internal output-damping resistors help reduce unnecessary overshoots undershoots. Transceivers buffers with balanced- lightdrive outputs also reduce overshoots undershoots diminishing output-drive currents. When selecting buffer/transceiver interface design flash, devices with internal output-damping resistors reduced-drive outputs should considered minimize overshoots undershoots. additional information, please refer AP-647, Volt Intel StrataFlash® Memory Design Guide (order 292205).
VCC, VPEN, Transitions
Block erase, program, lock-bit configuration guaranteed VPEN falls outside specified operating ranges, VHH. transitions during block erase, program, lock-bit configuration, default mode) will remain maximum time tPLPH tPHRH until reset operation complete. Then, operation will abort device will enter reset/power-down mode. aborted operation leave data partially corrupted after programming, partially altered after erase lock-bit configuration. Therefore, block erase lock-bit configuration commands must repeated after normal operation restored. Device power-off clears status register. latches commands issued system software altered VPEN, CE0, CE1, transitions, actions. state read array mode upon power-up, after exit from reset/ power-down mode, after transitions below VLKO. must kept above VPEN during transitions. After block erase, program, lock-bit configuration, even after VPEN transitions down VPENLK, must placed read array mode Read Array command subsequent access memory array desired. VPEN must kept below during VPEN transitions.
Power-Up/Down Protection
device designed offer protection against accidental block erasure, programming, lockbit configuration during power transitions. Internal circuitry resets read array mode power-up. system designer must guard against spurious writes voltages above VLKO when VPEN active. Since must device enabled (see Table command write, driving disabling device will inhibit writes. CUI's two-step command sequence architecture provides added protection against data alteration. Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock unlock capability protects device against inadvertent programming. device disabled while regardless control inputs.
28F320J5 28F640J5
Power Dissipation
When designing portable systems, designers must consider battery power consumption only during device operation, also data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data retained when system power removed.
Electrical Specifications
Absolute Maximum Ratings
Maximum Rating Commercial Temperature Devices +125 -2.0 +7.0 -2.0 +14.0 Maximum Rating Extended Temperature Devices +125 -2.0 +7.0 -2.0 +14.0
Parameter Temperature under Bias Expanded Storage Temperature Voltage (except RP#) Voltage with Respect during Lock-Bit Configuration Operations Output Short Circuit Current
Notes 1,2,3
NOTES: specified voltages with respect GND. Minimum voltage -0.5 input/output pins -0.2 VPEN pins. During transitions, this level undershoot -2.0 periods Maximum voltage input/output pins, VCC, VPEN +0.5 which, during transitions, overshoot +2.0 periods Maximum voltage overshoot +14.0 periods voltage normally VIH. Connection supply allowed maximum cumulative period hours. Output shorted more than second. more than output shorted time. Extended temperature micron ETOXV process technology from -20° +85°
NOTICE: This datasheet contains preliminary information products production. specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design. Warning: Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
Operating Conditions
Table Temperature Operating Conditions
Symbol VCCQ1 VCCQ2 Parameter Operating Temperature VCC1 Supply Voltage 10%) VCCQ1 Supply Voltage 10%) VCCQ2 Supply Voltage (2.7 -3.6 Notes 4.50 4.50 2.70 5.50 5.50 3.60 Unit Test Condition Ambient Temperature
28F320J5 28F640J5
Capacitance
+25°C,
Symbol COUT Parameter(1) Input Capacitance Output Capacitance Unit Condition VOUT
NOTE: Sampled, 100% tested.
Symbol ICCS
Characteristics
Parameter Input VPEN Load Current Output Leakage Current Standby Current Notes 1,2,3 Unit Test Conditions Max, Max, CMOS Inputs, Max, VCCQ1 CMOS Inputs, Max, VCCQ2 CMOS Inputs, Max, GND, VCCQ2 CMOS Inputs, Max, GND, VCCQ2 GND, VCCQ2 Inputs, Max, IOUT (STS) CMOS Inputs, VCCQ =VCC Device enabled (see Table IOUT Inputs ,VCC Device enabled (see Table IOUT CMOS Inputs, VPEN Inputs, VPEN CMOS Inputs, VPEN Inputs, VPEN Device disabled (see Table
0.71 ICCD Power-Down Current
ICCR
Read Current
1,3,4
ICCW
Program Lock-Bit Current
1,4,5
ICCE
Block Erase Clear Block Lock-Bits Current
1,4,5
ICCES
Block Erase Suspend Current
28F320J5 28F640J5
Characteristics, Continued
Symbol Parameter Input Voltage Input High Voltage Output Voltage Notes -0.5 0.45 Output High Voltage Unit VCCQ VCCQ1 Min, VCCQ VCCQ2 Min, VCCQ VCCQ1 VCCQ VCCQ2 -2.5 (VCCQ1) (VCCQ2) 0.85 VCCQ VCCQ -0.4 VPENLK VPENH VLKO VPEN Lockout during Normal Operations VPEN during Block Erase, Program, Lock-Bit Operations Lockout Voltage Unlock Voltage 5,7,8 10,11 3.25 11.4 12.6 master lock-bit Override lock-bit VCCQ VCCQ1 VCCQ VCCQ2 -2.5 VCCQ VCCQ1 VCCQ VCCQ2 -100 Test Conditions
NOTES: currents unless otherwise noted. These currents valid product versions (packages speeds). Contact Intel's Application Support Hotline your local sales office information about typical specifications. Includes STS. CMOS inputs either inputs either VIH. VCCQ VCCQ2 min. Sampled, 100% tested. ICCES specified with device de-selected. device read written while erase suspend mode, device's current draw ICCR ICCW. VPEN (4.5 V-5.5 Block erases, programming, lock-bit configurations inhibited when VPEN VPENLK, guaranteed range between VPENLK (max) VPENH (min), above VPENH (max). Block erases, programming, lock-bit configurations inhibited when VLKO, guaranteed range between VLKO (min) (min), above (max). 10.Master lock-bit operations inhibited when VIH. Block lock-bit configuration operations inhibited when master lock-bit VIH. Block erases programming inhibited when corresponding block-lock VIH. Block erase, program, lock-bit configuration operations guaranteed should attempted with VHH. 11.RP# connection supply allowed maximum cumulative period hours.
28F320J5 28F640J5
Figure Transient Input/Output Reference Waveform VCCQ (Standard Testing Configuration)
Input 0.45
Test Points
Output
NOTE: test inputs driven (2.4 VTTL) Logic (0.45 VTTL) Logic "0." Input timing begins
(2.0 VTTL) (0.8 VTTL). Output timing ends VIL. Input rise fall times (10% 90%)
Figure Transient Input/Output Reference Waveform
Input 1.35 Test Points 1.35 Output
NOTE: test inputs driven Logic Logic "0." Input timing begins, output timing ends,
1.35 (50% VCCQ). Input rise fall times (10% 90%)
Figure Transient Equivelent Testing Load Circuit
1.3V 1N914 Device Under Test
NOTE: Includes Capacitance
Table Test Configuration Capacitance Loading Value
Test Configuration VCCQ VCCQ V-3.6 (pF)
28F320J5 28F640J5
Characteristics-Read-Only Operations(1)
Versions VCCQ V-10% VCCQ Notes Mbit +85° +85° Mbit +85° 1000 1000 -120/-150(2) -120/-150(2)
(All units unless otherwise noted) Parameter
tAVAV
Read/Write Cycle Time Mbit Mbit
tAVQV
Address Output Delay Mbit Mbit
tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tELFL tELFH tFLQV tFHQV tFLQZ tEHEL
Output Delay Mbit Output Delay High Output Delay Mbit Output Output High Output High High Output High Output Hold from Address, CEX, Change, Whichever Occurs First BYTE# High BYTE# Output Delay BYTE# Output High Disable Pulse Width
NOTE: defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (seeTable Figure Waveform Read Operations" page maximum allowable input slew rate. Figure Figure Figure page testing characteristics delayed tELQV-tGLQV after first edge CE0, CE1, that enables device (see Table without impact tELQV. Sampled, 100% tested.
28F320J5 28F640J5
Figure Waveform Read Operations
Standby Device Address Selection Address Stable Data Valid
ADDRESSES
Disabled (VIH)
Enabled (VIL) High Valid Output High
DATA [D/Q] DQ0-DQ15
BYTE#
0606_16
NOTE: defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table "Chip Enable Truth Table" page 12).
28F320J5 28F640J5
Characteristics- Write Operations(1,2)
Valid Speeds Parameter High Recovery (CEX Going (WE#) (CEX) Going Write Pulse Width Data Setup (CEX Going High Address Setup (CEX Going High (WE#) Hold from (CEX) High Data Hold from (CEX High Address Hold from (CEX High Write Pulse Width High Setup (CEX Going High VPEN Setup (CEX Going High Write Recovery before Read (CEX High Going Hold from Valid SRD, Going High VPEN Hold from Valid SRD, Going High 3,8,9 3,8,9 Notes Unit
Versions tPHWL (tPHEL) tELWL (tWLEL) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tPHHWH (tPHHEH) tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVPH tQVVL
NOTE: defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table page 12). Read timing characteristics during block erase, program, lock-bit configuration operations same during read-only operations. Refer Characteristics-Read-Only Operations. write operation initiated terminated with either WE#. Sampled, 100% tested. Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. driven before going low, pulse width requirement decreases Refer Table page valid block erase, program, lock-bit configuration. Write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. array access, tAVQV required addition tWHGL accesses after write. timings based configured RY/BY# default mode. VPEN should held VPENH (and necessary should held VHH) until determination block erase, program, lock-bit configuration success (SR.1/3/4/5
28F320J5 28F640J5
Figure Waveform Write Operations
Disabled CEX, (WE#) [E(W)] Enabled
ADDRESSES
Disabled WE#, [W(E)] Enabled
Valid High
DATA [D/Q]
VPENH VPENLK VPEN
0606_17
NOTE: defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table page 12). shown
default mode (RY/BY#).
power-up standby. Write block erase, write buffer, program setup. Write block erase write buffer confirm, valid address data. Automated erase delay. Read status register query data. Write Read Array command.
28F320J5 28F640J5
Figure Waveform Reset Operation
0606_18
NOTE: shown default mode (RY/BY#).
Table Reset Specifications(1)
tPLPH tPHRH Parameter Pulse Time tied VCC, this specification applicable) High Reset during Block Erase, Program, Lock-Bit Configuration Notes
NOTES: These specifications valid product versions (packages speeds). asserted while block erase, program, lock-bit configuration operation executing then minimum required Pulse Time reset time, tPHQV, required from latter RY/BY# mode) going high until outputs valid.
28F320J5 28F640J5
Block Erase, Program, Lock-Bit Configuration Performance(1,2)
Write Buffer Program Time tWHQV3 tEHQV3 Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write Buffer Command) Parameter Notes 4,5,6,7 Typ(3) Unit
tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH tEHRH
Block Erase Time Lock-Bit Time Clear Block Lock-Bits Time Erase Suspend Latency Time Read
NOTES: These performance numbers valid speed versions. Sampled 100% tested. Typical values measured nominal voltages. Assumes corresponding lock-bits set. Subject change based device characterization. Excludes system-level overhead. These values valid when buffer full, start address aligned 32-byte boundary. Effective per-byte program time (tWHQV1, tEHQV1) µs/byte (typical). Effective per-word program time (tWHQV2, tEHQV2) 13.6 µs/byte (typical).
28F320J5 28F640J5
Additional Information
Order Number Contact Intel/Distribution Sales Office 290667 290608 290609 290429 290598 290597 292235 297859 292222 292221 292218 292205 292204 292202 297846
Document/Tool Volt Intel StrataFlash® Memory 0.25 Generation/32-, 64-Mbit Densities Volt Intel StrataFlash® Memory; 28F128J3A, 28F640J3A, 28F320J3A datasheet Volt FlashFileMemory; 28F160S3 28F320S3 datasheet Volt FlashFileMemory; 28F160S5 28F320S5 datasheet Volt FlashFileMemory; 28F008SA datasheet Volt FlashFileMemory; 28F004S3, 28F008S3, 28F016S3 datasheet Volt FlashFileMemory; 28F004S5, 28F008S5, 28F016S5 datasheet AP-687 Volt Intel StrataFlash® Memory Interface SA-1100 AP-677 Intel StrataFlash® Memory Technology AP-664 Designing Intel StrataFlash® Memory into Intel® Architecture AP-663 Using Intel StrataFlash® Memory Write Buffer AP-660 Migration Guide Volt Intel StrataFlash® Memory AP-647 Volt Intel StrataFlash® Memory Design Guide AP-646 Common Flash Interface (CFI) Command Sets AP-644 Migration Guide Volt Intel StrataFlash® Memory Comprehensive User's Guide µBGA* Packages
NOTES: Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.intel.com technical documentation tools. most current information Intel StrataFlash memory, visit website http://developer.intel.com/ design/flash/isf.
28F320J5 28F640J5
Ordering Information
Package 56-Lead TSOP 56-Lead SSOP
(Commercial Temp)
Access Speed (ns) Mbit Mbit Intel® micron ETOX VIProcess Technology Voltage (VCC/VPEN) Product Family Intel StrataFlash® memory, bits-per-cell
56-Lead SSOP
(Extended Temp)
Product line designator Intel® Flash products Device Density x8/x16 Mbit) x8/x16 Mbit)
NOTE: Extended temperature micron ETOXV process technology from -20° +85°
Order Code Density Mbit DA28F320J5-120 E28F320J5-120 DT28F320J5-120 DA28F320J5A-120 E28F320J5A-120 DT28F320J5A-120 Mbit DA28F640J5-150 DT28F640J5-150 DA28F640J5A-150 DT28F640J5A-150
Valid Operational Conditions VCCQ VCCQ

28F320J5 28F640J5 (x8/x16) High-Density Symmetrically-Blocked Arc

Top Searches for this datasheet

Other recent searches