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Intel® XeonProcessor 1.40 GHz, 1.50 1.60
Available 1.40, 1.50 1.60GHz 4-way greater multi-processing server support Binary compatible with applications running Intel IA-32 architecture processors Hyper-Threading Technology enabling multi-threading server software execute threads parallel each processor system Bandwidth Gbytes/sec Rapid Execution Engine: Arithmetic Logic Units (ALUs) twice processor core frequency Enables system support physical memory Advance Dynamic Execution Very deep out-of-order execution Enhanced branch prediction Level Execution Trace Cache stores micro-ops removes decoder latency from main execution loops Includes Level data cache
Intel® NetBurstmicro-architecture Advanced Transfer Cache (on-die, full speed Level (L2) cache) with 8-way associativity Error Correcting Code (ECC) Integrated Level Cache (on-die, full speed Level Cache) with Error Correcting Code (ECC) provides faster access large server instruction data sets Streaming SIMD Extensions (SSE2) instructions Enhanced floating point multimedia unit enhanced video, audio, encryption, performance Power Management capabilities System Management mode Multiple low-power states Advanced System Management Features Processor Information (PIROM) System Management (SMBus) Scratch EEPROM Machine Check Architecture (MCA)
Intel® Xeonprocessor designed high-performance enterprise e-Business server applications. Based Intel® NetBurstmicro-architecture, binary compatible with previous Intel IA-32 Architecture processors introduces Hyper-Threading technology multi-processing server platforms. Intel Xeon processor scalable four more processors multiprocessor system providing exceptional performance enterprise server applications running advanced operating systems such Windows 2000 Server*, Linux*, Netware* UNIX*. Intel Xeon processor extends power Intel® Pentium® Xeonprocessor with features designed make this processor right choice powerful enterprise server, mission-critical applications. Advanced features simplify system management meet needs robust environment, resulting maximized system time, convenient system management, optimal configuration.
Order Number: 290740-002 March 2002
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® Xeon processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Intel, Pentium, Pentium Xeon, Intel Xeon Intel NetBurst trademark registered trademarks Intel Corporation subsidiaries United States other countries. Copyright Intel Corporation, 2002 Other names brands claimed property others.
Contents
Contents
Introduction
Terminology.12 1.1.1 Processor Packaging Terminology.12 References State Data System GTLREF Power Ground Pins Decoupling Guidelines 2.3.1 Decoupling 2.3.2 System AGTL+ Decoupling.16 System Clock (BCLK[1:0]) Processor Clocking 2.4.1 Phase Lock Loop (PLL) Power Filter.17 2.4.2 System Core Frequency Ratios 2.4.3 Mixing Processors Voltage Identification 2.5.1 Mixing Processors Different Voltages Reserved Unused Pins.21 System Signal Groups Asynchronous GTL+ Signals.23 Test Access Port (TAP) Connection.23 Maximum Ratings.23 Processor Specifications.24 AGTL+ System Specifications System Specifications Processor Timing Waveforms System Clock (BCLK) Signal Quality Specifications Measurement Guidelines System Signal Quality Specifications Measurement Guidelines.42 3.2.1 Ringback Guidelines 3.2.2 Overshoot/Undershoot Guidelines 3.2.3 Overshoot/Undershoot Magnitude 3.2.4 Overshoot/Undershoot Pulse Duration.46 3.2.5 Activity Factor 3.2.6 Reading Overshoot/Undershoot Specification Tables.46 3.2.7 Determining System Meets Overshoot/Undershoot Specifications Processor Mechanical Specifications.53 Package Load Specifications Processor Insertion Specifications Processor Mass Specifications Processor Materials.57
Electrical Specifications
2.10 2.11 2.12 2.13 2.14
System Signal Quality Specifications
Mechanical Specifications.51
Contents
Processor Markings Processor Pin-Out Diagrams Processor Assignments 5.1.1 Listing Name 5.1.2 Listing Number Signal Definitions Thermal Specifications. Thermal Analysis. 6.2.1 Measurements Thermal Specifications. 6.2.1.1 Processor Case Temperature Measurement Power-On Configuration Options Clock Control Power States. 7.2.1 Normal State-State 7.2.2 AutoHALT Powerdown State-State 7.2.3 Stop-Grant State-State 7.2.4 HALT/Grant Snoop State-State 7.2.5 Sleep State-State 7.2.6 Response During Power States Thermal Monitor 7.3.1 Thermal Diode. System Management (SMBus) Interface 7.4.1 Processor Information (PIR) 7.4.2 Scratch EEPROM 7.4.3 Scratch EEPROM Supported SMBus Transactions. 7.4.4 SMBus Thermal Sensor 7.4.5 Thermal Sensor Supported SMBus Transactions 7.4.6 SMBus Thermal Sensor Registers 7.4.6.1 Thermal Reference Registers 7.4.6.2 Thermal Limit Registers 7.4.6.3 Status Register. 7.4.6.4 Configuration Register. 7.4.6.5 Conversion Rate Registers 7.4.7 SMBus Thermal Sensor Alert Interrupt 7.4.8 SMBus Device Addressing. Introduction Mechanical Specifications. 8.2.1 Boxed Processor Heatsink Dimensions 8.2.2 Boxed Processor Heatsink Weight. 8.2.3 Boxed Processor Retention Mechanism Heatsink Supports. Boxed Processor Requirements 8.3.1 Intel® XeonProcessor Thermal Specifications. 8.4.1 Boxed Processor Cooling Requirements
Listing Signal Definitions.
Thermal Specifications
Features
Boxed Processor Specifications
Contents
Debug Tools Specifications .113
Debug Port System Requirements.113 Target System Implementation .114 9.2.1 System Implementation.114 Logic Analyzer Interface (LAI) .114 9.3.1 Mechanical Considerations .114 9.3.2 Electrical Considerations.114 Processor Core Frequency Determination .115
10.0
Appendix .115
10.1
Contents
Figures
Typical VCCIOPLL, VCCA VSSA Power Distribution Phase Lock Loop (PLL) Filter Requirements Electrical Test Circuit Clock Waveform. Differential Clock Waveform. System Common Clock Valid Delay Timing Waveform System Source Synchronous (Address) Timing Waveform System Source Synchronous (Data) Timing Waveform System Reset Configuration Timing Waveform Power-On Reset Configuration Timing Waveform Valid Delay Timing Waveform. Test Reset (TRST#), Async GTL+ Input, PROCHOT# Timing Waveform THERMTRIP# Power Down Waveform SMBus Timing Waveform SMBus Valid Delay Timing Waveform BCLK[1:0] Signal Integrity Waveform. Low-to-High Receiver Ringback Tolerance AGTL+ Async GTL+ Signals High-to-Low Receiver Ringback Tolerance AGTL+ Async GTL+ Signals Low-to-High Receiver Ringback Tolerance Signals. High-to-Low Receiver Ringback Tolerance Signals. Maximum Acceptable Overshoot/Undershoot Waveform Processor Assembly Drawing (Including Socket) Processor View Component Placement Detail. Processor Package Drawing Processor View Component Height Keep-in Processor Cross Section View Side Component Keep-in Processor Detail. Processor Flatness Tilt Drawing Processor Top-Side Markings. Processor Bottom-Side Markings. Processor Pin-out Diagram View. Processor Pin-out Diagram Bottom View Processor with Thermal Mechanical Components Exploded View. Locations Case Temperature (TCASE) Thermocouple Placement Stop Clock State Machine. Logical Schematic SMBus Circuitry Mechanical Representation Boxed Processor Passive Heatsink Multiple View Space Requirements Boxed Processors Boxed Processor Heatsink Airflow Direction. Timing Diagram Clock Ratio Signals. Example Schematic Clock Ratio Sharing
Tables
Intel® XeonProcessor Features Core Frequency System Multiplier Configuration.19 Voltage Identification Definition System Signal Groups Processor Absolute Maximum Ratings Voltage Current Specifications System Differential BCLK Specifications AGTL+ Signal Group Specifications Signal Group Specifications Asynchronous GTL+ Signal Groups Specifications SMBus Signal Group Specifications AGTL+ Voltage Definitions.29 System Differential Clock Specifications.30 System Common Clock Specifications System Source Synchronous Specifications.31 Asynchronous GTL+ Specifications System Specifications (Reset Conditions) Signal Group Specifications SMBus Signal Group Specifications.33 BCLK Signal Quality Specifications.41 Ringback Specifications AGTL+ Asynchronous GTL+ Signal Groups.42 Ringback Specifications Signal Group Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Asynchronous GTL+ Signal Groups Overshoot/Undershoot Tolerance Dimensions Processor Package.54 Package Dynamic Static Load Specifications Processor Mass.57 Processor Material Properties Listing Name Listing Number Signal Definitions.79 Power Thermal Specifications.89 Power-On Configuration Option Pins Processor Information Format Read Byte SMBus Packet Write Byte SMBus Packet Write Byte SMBus Packet .100 Read Byte SMBus Packet .100 Send Byte SMBus Packet .100 Receive Byte SMBus Packet.101 SMBus Packet .101 SMBus Thermal Sensor Command Byte Assignments.101 Thermal Reference Register Values .102
SMBus Thermal Sensor Status Register SMBus Thermal Sensor Configuration Register SMBus Thermal Sensor Conversion Rate Registers Thermal Sensor SMBus Addressing Memory Device SMBus Addressing
Contents
Revision History
Date Release March 2002 Revision -001 Description This first release this datasheet.
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Intel® XeonProcessor
Introduction
Intel® Xeonprocessor based Intel® NetBurstmicroarchitecture that operates significantly higher clock speeds delivers performance levels that significantly higher than previous generations IA-32 processors. While based Intel NetBurst micro-architecture, still maintains tradition compatibility with IA-32 software. Intel Xeon processor also introduces groundbreaking feature multi-processing servers called Hyper-Threading technology that enables each processor system process multiple software threads simultaneously enabling higher performance level multi-threaded server software. Intel NetBurst microarchitecture features include much higher clock speeds, Rapid Execution Engine, system bus, Integrated Three-Level Cache architecture. Intel NetBurst microarchitecture doubles pipeline depth from previous generation processors, allowing processor reach much higher core frequencies. Rapid Execution Engine allows integer ALUs processor twice core frequency, which allows integer instructions execute half processor's clock cycle. system quad-pumped running system clock making second data transfer rates possible. Integrated Three-Level cache architecture designed balanced with Intel NetBurst microarchitecture provide fast access large instruction data sets commonly found large enterprise server applications. This cache architecture includes unique Level 1Execution Trace Cache that stores decoded micro-op instructions, which remove decoder from main execution path, Level Advanced Transfer Cache 256KB operating full processor speed Integrated Level Cache 512KB providing fast, on-chip access large server data sets. Another feature Intel Xeon processor that industry first general purpose multi-processing, Intel's Hyper-Threading Technology. This technology allows Intel Xeon processor appear logical processors operating system applications allowing each physical processor support software threads simultaneously without increasing processor's execution resources. result increased utilization those resources improved performance multi-threaded server software. Hyper-Threading technology compliments multiprocessing providing greater headroom multi-threaded server software. Intel NetBurst microarchitecture also improved some features introduced previous generations, including Advanced Dynamic Execution, enhanced floating point multimedia unit, Streaming SIMD Extensions (SSE2). Advanced Dynamic Execution improves speculative execution branch prediction internal processor. floating point multimedia units have been improved making registers bits wide adding separate register data movement. Finally, SSE2 adds instructions double-precision floating point, SIMD integer, memory management. Intel Xeon processor intended high performance multi-processing enterprise server systems with four processors which then connected clusters provide 32-way greater configurations. Intel Xeon processor will available speeds 1.40, 1.50 1.60GHz with options Kbyte Mbyte integrated level-3 (L3) cache. These processors also include manageability features, such EEPROM Processor Information which accessed through System Management (SMBus) interface contain information relevant particular processor system which installed. addition, enhancements have been made Machine Check Architecture.
Intel® XeonProcessor
Table
Intel® XeonProcessor Features
Processors Intel® XeonProcessor Advanced Transfer Cache Integrated Level Cache Manageability Features Intel® NetBurstMicro-Architecture Intel® HyperThreading Technology
result integrating caches into processor silicon, return (Pin-Grid Array) style processor packaging possible. Intel Xeon processor packaged 603-pin micro-PGA package utilizes surface mount socket with pins. heatsinks, heatsink retention mechanisms sockets required (versus previous processors Intel® Pentium® Xeonprocessor family). Heatsinks retention mechanisms have been designed with manufacturability high priority. Hence, mechanical assembly completed from motherboard. processors scalable system protocol, referred "system bus" this document. processor system utilizes split-transaction, deferred reply protocol similar that processor family system bus, compatible with processor family system bus. system uses Source-Synchronous Transfer (SST) address data transfer improve performance. Whereas processor family transfers data once clock, Intel Xeon processor transfers data four times clock data transfer rate). Along with data bus, address delivers addresses times clock referred `double-clocked' address bus. addition, Request Phase completes clock cycle. Working together, data address provide data bandwidth Gbytes/second (3200 Mbytes/sec). Finally, system also introduces transactions that used deliver interrupts. Signals system Assisted GTL+ (AGTL+) level voltages which fully described appropriate platform design guide (refer Section 1.2).
Terminology
symbol after signal name refers active signal, indicating signal asserted state when driven level. example, when RESET# low, reset been requested. Conversely, when high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). "System bus" refers interface between processor, system core logic (a.k.a. chipset components), other agents. system multiprocessing interface processors, memory, I/O. this document, "system bus" used generic term Intel Xeon processor scalable system bus.
1.1.1
Processor Packaging Terminology
Commonly used terms explained here clarification:
Intel® XeonProcessor
603-pin socket -The connector which mates processor motherboard. 603-pin
socket surface mount technology (SMT), zero insertion force (ZIF) socket utilizing solder ball attachment platform. Socket Design Guidelines details regarding this socket.
FC-BGA (Flip Chip Ball Grid Array) Package -Microprocessor package using "flip chip"
design, where processor attached substrate face-down, within ball grid array package. This package then mounted onto interposer interface with platform.
Intel® Xeonprocessor -The entire product including processor core OLGA
FC-BGA package, integrated heat spreader (IHS), interposer. this document, terms "Intel Xeon processor "the processor" Intel Xeon processor
Integrated Heat Spreader (IHS) -The surface used attach heatsink other thermal
solution Intel Xeon processor Section specific details.
Interposer -The structure which processor core package pins mounted. -Original Equipment Manufacturer. OLGA (Organic Land Grid Array) Package -Microprocessor package using "flip chip"
design, where processor attached substrate face-down better signal integrity, more efficient heat removal lower inductance, within organic land grid array package.
Processor core -The processor's execution engine. timing signal integrity
specifications pads processor core.
Processor Information (PIR)-A memory device located processor
accessible System Management (SMBus) which contains information regarding processor's features. This device shared with scratch EEPROM, programmed during manufacturing write-protected. Section details PIR.
Retention mechanism -The support pieces that mounted through motherboard
chassis wall provide added support retention processor heatsinks.
Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)-A
memory device located processor addressable SMBus which used store information useful system management. Section details Scratch EEPROM.
SMBus-System Management Bus. two-wire interface through which simple system
power management related devices communicate with rest system. based principals operation two-wire serial from Phillips Semiconductor*.
Intel® XeonProcessor
References
Material concepts available following documents beneficial when reading this document:
Document AP-485, Intel Processor Identification CPUID Instruction IA-32 Intel Architecture Software Developer's Manual Volume Basic Architecture Volume Instruction Reference Manual Volume III: System Programming Guide Intel® XeonProcessor Platform Design Guide Intel® NetBurstMicro-Architecture BIOS Writer's Guide Intel Xeon Intel Xeon
Intel Order Number 241618
245470 245471 245472 250397 Note Note 298348 249672 Note 249678, Note 249206 249205 Note Note 249673 Note Note Note Note Note Note Note 249679 www.sbs-forum.org/smbus Note
Processor Family Thermal Design Guidelines Processor Thermal Design Guidelines
Socket Design Guidelines Intel Xeon Intel Xeon
Processor Preliminary Specification Update Processor Specification Update
CK00 Clock Synthesizer/Driver Design Guidelines DC-DC Converter Design Guidelines DC-DC Converter Design Guidelines Dual Intel Xeon Intel Xeon
Processor Voltage Regulator Down (VRD) Design Guidelines
Processor Thermal Solution Functional Specification
Intel® XeonProcessor Signal Integrity Model (IBIS format) Intel Xeon Intel Xeon Intel Xeon
Processor Overshoot Checker Tool Processor Enabled Components ProE* Files Processor Enabled Components IGES Files
Intel® XeonProcessor FloTherm* Model Intel Xeon Intel Xeon
Processor FloTherm* Model Processor Core Boundary Scan Descriptor Language (BSDL) Model
ITP700 Debug Port Design Guide System Management Specification, Wired Management Design Guide NOTES: This collateral available publicly
State Data
data contained within this document subject change. best information that Intel able provide publication date this document.
Intel® XeonProcessor
Electrical Specifications
System GTLREF
Most processor system signals Assisted Gunning Transceiver Logic (AGTL+) signalling technology. This signalling technology provides improved noise margins reduced ringing through voltage swings controlled edge rates. Unlike Intel® Pentium® Xeonprocessor family, termination voltage level Intel® Xeonprocessor AGTL+ signals VCC, operating voltage processor core. family processors utilize fixed 1.5V termination voltage known termination voltage that determined processor core allows better voltage scaling Intel® NetBurstmicro-architecture system bus. Because speed improvements data address busses, signal integrity platform design methods become more critical than with previous processor families. Design guidelines processor system detailed appropriate platform design guidelines (refer Section 1.2). AGTL+ inputs require reference voltage (GTLREF) which used receivers determine signal logical logical GTLREF must generated system board (See Table GTLREF specifications). Termination resistors provided processor silicon terminated core voltage (VCC). on-die termination resistors selectable feature enabled disabled ODTEN pin. agents, on-die termination enabled control reflections transmission line. middle agents, on-die termination must disabled. Intel chipsets will also provide on-die termination, thus eliminating need terminate system board most AGTL+ signals. Note: Some AGTL+ signals include on-die termination must terminated system board. Table details regarding these signals. AGTL+ depends incident wave switching. Therefore timing calculations AGTL+ signals based flight time opposed capacitive deratings. Analog signal simulation system bus, including trace lengths, highly recommended when designing system. Intel® XeonProcessor Signal Integrity Models, available http://developer.intel.com
Power Ground Pins
clean on-chip power distribution, Intel Xeon processor have (power) (ground) inputs. power pins must connected VCC, while pins must connected system ground plane. processor pins must supplied voltage determined (Voltage pins.
Decoupling Guidelines
large number transistors high internal clock speeds, processor capable generating large instantaneous current swings between full power states. This cause voltages power planes below their minimum values bulk decoupling adequate. Larger bulk storage (CBULK), such electrolytic capacitors, supply current during longer lasting changes current demand component, such coming idle condition. Similarly, they storage well current when entering idle condition from running condition.
Intel® XeonProcessor
Care must taken board design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations reduced lifetime component. further information guidelines, refer appropriate platform design guidelines.
2.3.1
Decoupling
Regulator solutions need provide bulk capacitance with Effective Series Resistance (ESR) maintain interconnect resistance from regulator voltage regulator pins) 603pin socket. Bulk decoupling provided voltage regulation module (VRM) meet needs large current swings. power delivery path must capable delivering enough current while maintaining required tolerances (defined Table further information regarding power delivery, decoupling, layout guidelines, refer appropriate platform design guidelines.
2.3.2
System AGTL+ Decoupling
processor integrates portion required high frequency decoupling capacitance processor package. However, additional high frequency capacitance must added system board properly decouple return currents from system bus. Bulk decoupling must also provided system board proper AGTL+ operation. Decoupling guidelines described appropriate platform design guidelines.
System Clock (BCLK[1:0]) Processor Clocking
BCLK[1:0] directly controls system interface speed well core frequency processor. previous generation processors, Intel Xeon processor core frequency multiple BCLK[1:0] frequency. processor ratio multiplier will have maximum ratio during manufacturing. Platforms will ratio-setting pins, previous generation Pentium Xeon processors, configure processor maximum ratio, lower. This feature provided ensure that multiprocessing systems, which typically fully populated with processors time purchase, upgraded later date have processors same core frequency. Clock multiplying within processor provided internal PLL, which requires constant frequency BCLK[1:0] input with exceptions spread spectrum clocking. Processor specifications BCLK[1:0] inputs provided Table Table respectively. These specifications must while also meeting signal integrity requirements outlined Chapter 3.0. Unlike previous processors, Intel Xeon processors utilize differential clocks. Details regarding BCLK[1:0] driver specifications provided CK00 Clock Synthesizer/Driver Design Guidelines document. BCLK[1:0] inputs directly control operating speed system interface. processor core frequency must configured during Reset using A20M#, IGNNE#, LINT[1]/NMI, LINT[0]/INTR pins (see Table value these pins during Reset determines multiplier that Phase Lock Loop (PLL) will internal core clock. Production units processor limited their maximum bus-to-core ratio only maximum lower ratios supported. ratio higher than maximum chosen, processor will default maximum ratio. maximum ratio each processor equal core frequency divided frequency marked processor.
Intel® XeonProcessor
2.4.1
Phase Lock Loop (PLL) Power Filter
VCCA VCCIOPLL power sources required clock generators processor silicon. Since these PLLs analog nature, they require quiet power supplies minimum jitter. Jitter detrimental system: degrades external timings well internal core timings (i.e. maximum frequency). prevent this degradation, these supplies must pass filtered from VCC. typical filter topology shown Figure low-pass requirements, with input output measured across capacitor Figure follows:
gain pass band attenuation pass band (see drop next requirements) attenuation from attenuation from core frequency
filter requirements illustrated Figure recommendations implementing filter refer appropriate platform design guidelines.
Figure Typical VCCIOPLL, VCCA VSSA Power Distribution
VCCA Processor Core
VSSA VCCIOPLL
Intel® XeonProcessor
Figure Phase Lock Loop (PLL) Filter Requirements
-0.5 forbidden zone
forbidden zone
passband
fpeak
fcore
high frequency band
NOTES: Diagram scale. specifications frequencies beyond fcore (core frequency). fpeak, existent, should less than 0.05 MHz.
2.4.2
System Core Frequency Ratios
frequency multipliers supported shown Table Other combinations will validated supported Intel. given processor, only ratios which result core frequency equal less than frequency marked processor supported.
Intel® XeonProcessor
Table Core Frequency System Multiplier Configuration
Multiplier System Busto-Core Frequency 1/23 1/10 1/11 1/12 1/13 1/14 1/15 1/16 1/17 1/18 1/19 1/20 1/21 1/22 1/24 Core Frequency 2.30 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.40 LINT[1]/ A20M# IGNNE# LINT[0]/ INTR Notes
NOTES: These multipliers supported stepping processors. Refer Intel® XeonProcessor Specification Update processor stepping details.
2.4.3
Mixing Processors
Mixing processors operating different internal clock frequencies supported been validated Intel. operating systems support multiple processors with mixed frequencies. Intel does support validate operation processors with different cache sizes. Intel only supports validates multi-processor configurations where processors operate with same system bus, core frequencies, settings, have same internal cache sizes. Mixing processors different steppings same model CPUID instruction) supported. Details CPUID provided IA32 Architecture Software Developer's Manual Intel Processor Identification CPUID Instruction application note.
Voltage Identification
specification Intel Xeon processor different from that previous generations supported DC-DC Convertor Design Guidelines. voltage pins maximum voltage allowed processor. minimum voltage provided Table changes with frequency. This allows processors running higher frequency have relaxed minimum voltage specification. specifications have been such that voltage regulator work with supported frequencies. processor uses five voltage identification pins, VID[4:0], support automatic selection power supply voltages. Table specifies voltage level corresponding state VID[4:0]. this table refers high voltage refers voltage level. definition
Intel® XeonProcessor
provided Table related previous processors voltage regulators. processor socket empty (VID[4:0] 11111), voltage regulation circuit cannot supply voltage that requested, must disable itself.
Table Voltage Identification Definition
Processor Pins VID4 VID3 VID2 VID1 VID0 VCC_MAX output 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
2.5.1
Mixing Processors Different Voltages
Mixing processors operating different settings (voltages) supported will validated Intel.
Intel® XeonProcessor
Reserved Unused Pins
Reserved pins must remain unconnected. Connection these pins VCC, VSS, other signal (including each other) result component malfunction incompatibility with future Intel Xeon processor Chapter listing processor location Reserved pins. reliable operation, always connect unused inputs bidirectional signals appropriate signal level. system level design, on-die termination provided processor allow agents terminated within processor silicon. this context, agent refers agent that resides either daisy-chained system interface while middle agent agent between agents. agents, most unused AGTL+ inputs should left connects, AGTL+ termination provided processor silicon. However, Table details AGTL+ signals that include on-die termination. middle agents, ondie termination must disabled, platform must ensure that unused AGTL+ input signals which connect agents connected pull-up resistor. Unused active high inputs, should connected through resistor ground (VSS). Unused outputs left unconnected, however this interfere with some functions, complicate debug probing, prevent boundary scan testing. resistor must used when tying bidirectional signals power ground. When tying signal power ground, resistor will also allow system testability. unused AGTL+ input signals, pull-up resistors same value on-die termination resistors (RTT). Table TAP, Asynchronous GTL+ inputs, Asynchronous GTL+ outputs include on-die termination. Inputs utilized outputs must terminated system board. Unused outputs terminated system board left unconnected. Note that leaving unused outputs unterminated interfere with some functions, complicate debug probing, prevent boundary scan testing. Signal termination recommendations these signal types discussed platform design guidelines ITP700 Debug Port Design Guide (see Section 1.2). each processor, TESTHI[6:0] pins must connected pull-up resistor between value. TESTHI[3:0] TESTHI[6:5] tied together each processor pulled with single resistor desired. However, utilization boundary scan test will functional these pins connected together. TESTHI4 must always pulled independently from other TESTHI pins. TESTHI pins must connected between system agents.
System Signal Groups
order simplify following discussion, system signals have been combined into groups buffer type. AGTL+ input signals have differential input buffers, which GTLREF reference level. this document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. With implementation source synchronous data comes need specify sets timing parameters. common clock signals whose timings specified with respect rising edge BCLK0 (ADS#, HIT#, HITM#, etc.) second source synchronous signals which relative their respective strobe lines (data address) well rising edge BCLK0. Asynchronous signals still present (A20M#, IGNNE#, etc.) become active time during clock cycle. Table identifies which signals common clock, source synchronous asynchronous.
Intel® XeonProcessor
Table System Signal Groups
Signal Group AGTL+ Common Clock Input Type Synchronous BCLK[1:0] Signals BPRI#, BR[3:1]#2, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY# ADS#, AP[1:0]#, BINIT#7, BNR#7, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7
AGTL+ Common Clock
Synchronous BCLK[1:0]
Signals REQ[4:0]#,A[16:3]# A[35:17]# AGTL+ Source Synchronous Synchronous assoc. strobe
Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
AGTL+ Strobes Asynchronous GTL+ Input Asynchronous GTL+ Output System Clock Input Output
Synchronous BCLK[1:0] Asynchronous Asynchronous Clock Synchronous Synchronous Synchronous SM_CLK
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#5, IGNNE#5, INIT#6, LINT0/INTR5, LINT1/NMI5, PWRGOOD, SMI#6, SLP#, STPCLK# FERR#, IERR#, THERMTRIP#, PROCHOT# BCLK1, BCLK0 TCK, TDI, TMS, TRST# SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT, SM_CLK, SM_ALERT#, SM_WP COMP[1:0], GTLREF, OTDEN, Reserved, SKTOCC#, TESTHI[6:0],VID[4:0], VCC, SM_VCC, VCCA, VSSA, VCCIOPLL, VSS, VCCSENSE, VSSSENSE
SMBus Interface
Power/Other
Power/Other
NOTES: Refer Section signal descriptions. These AGTL+ signals terminated processor. Refer ITP700 Debug Port Design Guide platform design guidelines termination recommendations.They must terminated agents platform. These signal groups terminated processor. Refer Section 2.6, ITP700 Debug Port Design Guide, platform design guidelines termination recommendations. This signal group terminated processor. Refer Section platform design guidelines termination recommendations. value these pins during active-to-inactive edge RESET# determines multiplier that Phase Lock Loop (PLL) will internal core clock. value these pins during active-to-inactive edge RESET# determine processor configuration options. Section details. These signals driven simultaneously multiple agents (wired-OR). These signals terminated processor's on-die termination. However, some signals this group include termination processor interposer. Section details.
Intel® XeonProcessor
Asynchronous GTL+ Signals
Intel Xeon processor does utilize CMOS voltage levels signals that connect processor. result, legacy input signals such A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# utilize GTL+ input buffers. Legacy output FERR# other non-AGTL+ signals IERR#, THERMTRIP# PROCHOT# utilize GTL+ output buffers. these asynchronous GTL+ signals follow same requirements AGTL+ signals, however outputs driven high (during electrical low-to-high transition) processor (the major difference between GTL+ AGTL+). Asynchronous GTL+ signals have setup hold time specifications relation BCLK[1:0]. However, asynchronous GTL+ signals required asserted least BCLKs order processor recognize them. Table Table specifications asynchronous GTL+ signal group. Section additional timing requirements entering leaving power states.
Test Access Port (TAP) Connection
voltage levels supported other components Test Access Port (TAP) logic, recommended that Intel Xeon processor first chain followed other components within system. translation buffer should used connect rest chain unless other components capable accepting input appropriate voltage. Similar considerations must made TCK, TMS, TRST#. copies each signal required with each driving different voltage level. Refer Chapter more detailed information. Table Table specifications signal group.
2.10
Maximum Ratings
Table lists processor's maximum environmental stress ratings. Functional operation absolute maximum minimum neither implied guaranteed. processor should receive clock while subjected these conditions. Functional operating parameters listed tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from electrostatic discharge, should always take precautions avoid high static voltages electric fields.
Table Processor Absolute Maximum Ratings
Symbol TSTORAGE VinAGTL+ VinGTL+ VinSMBus IVID Parameter Processor storage temperature processor supply voltage with respect AGTL+ buffer input voltage with respect Async GTL+ buffer input voltage with respect SMBus buffer input voltage with respect current -0.5 -0.3 -0.3 -0.3 Unit Notes
Intel® XeonProcessor
NOTE: Please contact Intel storage requirements excess year. This rating applies processor.
2.11
Processor Specifications
processor specifications this section defined processor core (pads) unless noted otherwise. Section Intel Xeon processor listings Section signal definitions. voltage current specifications versions processor detailed Table specifications AGTL+ signals listed Table system clock signal group SMBus interface signal group detailed Table Table respectively. Previously, legacy signals (CMOS) Test Access Port (TAP) signals processor used low-voltage CMOS buffer types. However, these interfaces follow specifications similar GTL+. specifications signal group listed Table asynchronous GTL+Table Table through Table list specifications processor valid only while meeting specifications case temperature (TCASE specified Chapter 6.0), clock frequency, input voltages. Care should taken read notes associated with each parameter.
Intel® XeonProcessor
Table Voltage Current Specifications
Symbol Parameter processor core with cache Core Freq processor core with 512KB cache processor max. SMBus supply voltage processor core with cache VCC_MID VCC_SMBus freq. freq. processor core with 512KB Cache SMBus power supply power pins GTLREF pins Stop-Grant/Sleep 1M/512KB active 1M/512KB ICC_SMBus ICC_PLL ICC_GTLREF ISGnt ISLP ITCC freq. freq freq freq 3.135 1.550 1.545 1.540 1.550 1.545 1.540 (VCC_MAX VCC_MIN) 3.30 3.465 22.5 1.70 1.70 1.70 1.70 1.70 1.70 Unit Notes
freq
NOTES: Unless otherwise noted, specifications this table apply processors. These specifications based final characterized data. variable voltage source should exist systems event that different voltage required. Section Table more information. voltage specification requirements measured across vias platform VCC_SENSE VSS_SENSE pins close socket with bandwidth oscilloscope, maximum probe capacitance, minimum impedance. maximum length ground wire probe should less than Ensure external noise from system coupled scope probe. processor should subjected static combination wherein exceeds VCC_MID 0.200 (1-ICC/ICC_MAX) [V]. Moreover, should never exceed VCC_MAX (VID). Failure adhere this specification shorten processor lifetime. Maximum current defined VCC_MID. current specified also AutoHALT State. instantaneous current processor will draw while thermal control circuit active indicated assertion PROCHOT#. This specification applies power pins VCCA VCCIOPLL. Section 2.4.1 details. This parameter based design characterization tested. This specification applies each GTLREF pin.
Table System Differential BCLK Specifications (Page
Symbol Parameter Input Voltage Unit Figure Notes
Intel® XeonProcessor
Table System Differential BCLK Specifications (Page
Symbol VCROSS VRBM Parameter Input High Voltage Crossing Voltage Overshoot Undershoot Ringback Margin Threshold Region 0.660 0.45 0.200 VCROSS 0.100 0.710 0.300 0.55 0.300 0.300 VCROSS 0.100 Unit Figure Notes
NOTES:. Unless otherwise noted, specifications this table apply processor frequencies cache sizes. Crossing Voltage defined absolute voltage where rising edge BCLK0 equal falling edge BCLK1. voltages observed processor. Overshoot defined absolute value maximum voltage allowed above level. Undershoot defined absolute value maximum voltage allowed below level. Ringback Margin defined absolute voltage difference between maximum Rising Edge Ringback maximum Falling Edge Ringback. Threshold Region defined region centered about crossing voltage which differential receiver switches. includes input threshold hysteresis. referred these specifications refers instantaneous VCC.
Intel® XeonProcessor
Table AGTL+ Signal Group Specifications
Symbol Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Output Current Input Leakage Current Output Leakage Current Buffer Resistance -0.150 GTLREF 0.100 -0.150 GTLREF 0.100 GTLREF 0.100 RON_MAX/ (RON_MAX 0.50 RTT_MIN) (0.50 RTT_MIN RON_MIN) Unit Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. defined maximum voltage level receiving agent that will interpreted logical value. defined minimum voltage level receiving agent that will interpreted logical high value. experience excursions above VCC. However, input signal drivers must comply with signal quality specifications Chapter 3.0. Refer Intel Xeon Processor Signal Integrity Models characteristics. referred these specifications refers instantaneous VCC.
Table Signal Group Specifications
Symbol VHYS VTVOH Parameter Input Hysteresis Input High Threshold Voltage Input High Threshold Voltage Output High Voltage Output Current Input Leakage Current Output Leakage Current Buffer Resistance 6.25 (VCC VHYS_MIN) (VCC VHYS_MAX) (VCC VHYS_MAX) (VCC VHYS_MIN) Unit Notes
13.25
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. outputs open drain. signal group must meet system signal quality specifications Chapter 3.0. Refer Intel® XeonProcessor Signal Integrity Models characteristics. referred these specifications refers instantaneous VCC. maximum output current based maximum current handling capability buffer specified into test load. VOL_MAX guaranteed when driving into test load depicted Figure VHYS represents amount hysteresis, nominally centered about VCC, inputs.
Intel® XeonProcessor
Table Asynchronous GTL+ Signal Groups Specifications
Symbol Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Output Current Input Leakage Current Output Leakage Current -0.150 GTLREF (0.1 VCC/1.3) -0.150 GTLREF (0.1 VCC/1.3) 0.400 Unit Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. Parameter will measured (for with system inputs). outputs open-drain. experience excursions above VCC. However, input signal drivers must comply with signal quality specifications Chapter 3.0. referred these specifications refers instantaneous VCC. maximum output current asynchronous GTL+ signals specified into test load shown Figure
Table SMBus Signal Group Specifications
Symbol CSMB Parameter Input Voltage Input High Voltage Output Voltage Output Current Input Leakage Current Output Leakage Current SMBus Capacitance -0.30 0.70 SM_VCC 0.30 SM_VCC 3.465 0.400 Unit Notes 1,2,
15.0
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. These parameters based design characterization tested. specifications SMBus signal group measured processor pins. Platform designers need this value calculate maximum loading SMBus determine maximum rise fall times SMBus signals.
2.12
AGTL+ System Specifications
Routing topologies dependent number processors supported chipset used design. Please refer appropriate platform design guidelines. most cases, termination resistors required these integrated into processor silicon, Table details which AGTL+ signals include on-die termination.The termination resistors enabled disabled through ODTEN pin. enable termination, this should pulled through resistor disable termination, this should pulled down through resistor. processor's on-die termination must enabled agent only. Please refer Table termination resistor values.
Intel® XeonProcessor
Valid high levels determined input buffers comparing with reference voltage called GTLREF (known VREF previous documentation). Table lists GTLREF specifications. AGTL+ reference voltage (GTLREF) should generated system board using high precision voltage divider circuits. important that system board impedance held specified tolerance, that intrinsic trace capacitance AGTL+ signal group traces known well-controlled. more details platform design appropriate platform design guidelines.
Table AGTL+ Voltage Definitions
Symbol GTLREF COMP[1:0] Parameter Reference Voltage Termination Resistance COMP Resistance 42.77 43.2 43.63 Units Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. tolerances this specification have been stated generically enable system designer calculate minimum values across range VCC. GTLREF generated from baseboard voltage divider resistors. Refer appropriate platform design guidelines implementation details. on-die termination resistance measured AGTL+ output driver. Refer Intel Xeon Processor Signal Integrity Models characteristics. COMP resistors provided baseboard with resistors. appropriate platform design guidelines implementation details. referred these specifications refers instantaneous VCC.
2.13
System Specifications
processor system timings specified this section defined processor core (pads). Chapter Intel Xeon processor listing signal definitions. Table through Table list specifications associated with processor system bus. AGTL+ timings referenced GTLREF both logic levels unless otherwise specified. timings specified this section should used conjunction with buffer models provided Intel. These buffer models, which include package information, available Intel Xeon processor IBIS format. AGTL+ layout guidelines also available appropriate platform design guidelines.
Note:
Care should taken read notes associated with particular timing parameter.
Intel® XeonProcessor
Table System Differential Clock Specifications
Parameter System Frequency BCLK[1:0] Period BCLK[1:0] Period Stability BCLK[1:0] Pulse High Time BCLK[1:0] Pulse Time BCLK[1:0] Rise Time BCLK[1:0] Fall Time 10.00 3.94 3.94 100.0 10.20 6.12 6.12 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. Intel Xeon processor core clock frequency derived from BCLK. clock Intel Xeon processor core clock ratio determined during initialization described Section 2.4. Table shows supported ratios Intel Xeon processor Also refer Chapter 10.0. period specified here average period. given period vary from this specification governed period stability specification (T2). clock jitter specification, refer CK00 Clock Synthesizer/Driver Design Guidelines. this context, period stability defined worst case timing difference between successive crossover voltages. other words, largest absolute difference between adjacent clock periods must less than period stability. Slew rate measured between points clock swing VH).
Table System Common Clock Specifications
Parameter T10: Common Clock Output Valid Delay T11: Common Clock Input Setup Time T12: Common Clock Input Hold Time T13: RESET# Pulse Width 0.20 0.65 0.40 1.00 1.45 10.00 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. 100% tested. Specified design characterization. common clock timings AGTL+ signals referenced Crossing Voltage (VCROSS) BCLK[1:0] rising edge BCLK0. common clock AGTL+ signal timings referenced GTLREF processor core. Valid delay timings these signals specified into test circuit described Figure with GTLREF Specification minimum swing defined between AGTL+ VIL_MAX VIH_MIN. This assumes edge rate V/ns. RESET# asserted (active) asynchronously, must deasserted synchronously. This should measured after BCLK[1:0] become stable. Maximum specification applies only while PWRGOOD asserted.
Intel® XeonProcessor
Table System Source Synchronous Specifications
Parameter T20: Source Sync. Output Valid Delay (first data/address only) T21: TVBD Source Sync. Data Output Valid Before Data Strobe T22: TVAD Source Sync. Data Output Valid After Data Strobe T23: TVBA Source Sync. Address Output Valid Before Address Strobe T24: TVAA Source Sync. Address Output Valid After Address Strobe T25: TSUSS Source Sync. Input Setup Time T26: THSS Source Sync. Input Hold Time T27: TSUCC Source Sync. Input Setup Time BCLK T28: TFASS First Address Strobe Second Address Strobe T29: TFDSS: First Data Strobe Subsequent Strobes T30: Data Strobe (DSTBN#) Output Valid Delay T31: Address Strobe Output Valid Delay 8.80 2.27 0.20 0.85 0.85 1.88 1.88 0.21 0.21 0.65 10.20 4.23 1.30 Unit BCLKs BCLKs Figure
1,2,
Notes
NOTE: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. 100% tested. Specified design characterization. source synchronous timings referenced their associated strobe GTLREF. Source synchronous data signals referenced falling edge their associated data strobe. Source synchronous address signals referenced rising falling edge their associated address strobe. source synchronous AGTL+ signal timings referenced GTLREF processor core. Unless otherwise noted, these specifications apply both data address timings. Valid delay timings these signals specified into test circuit described Figure with GTLREF Specification minimum swing defined between AGTL+ VIL_MAX VIH_MIN. This assumes edge rate V/ns 4.0V/ns. source synchronous signals must meet specified setup time BCLK well setup time each respective strobe. This specification represents minimum time data address will valid before strobe. Refer appropriate platform design guidelines more information definitions these specifications. This specification represents minimum time data address will valid after strobe. Refer appropriate platform design guidelines more information definitions these specifications. rising edge ADSTB# must come approximately BCLK period after falling edge ADSTB#. this timing parameter, second, third, last data strobes respectively. second data strobe (falling edge DSTBn#) must come approximately BCLK period (2.5 after first falling edge DSTBp#. third data strobe (falling edge DSTBp#) must come approximately BCLK period after first falling edge DSTBp#. last data strobe (falling edge DSTBn#) must come approximately BCLK period (7.5 after first falling edge DSTBp#. This specification applies only DSTBN[3:0]# measured second falling edge strobe. This specification reflects typical value, minimum maximum.
Intel® XeonProcessor
Table Asynchronous GTL+ Specifications
Parameter T35: Async GTL+ input pulse width, except PWRGOOD T36: PWRGOOD RESET# de-assertion time T37: PWRGOOD inactive pulse width T38: PROCHOT# pulse width T39: THERMTRIP# power down sequence Unit BCLKs BCLKs Figure
Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. timings Asynchronous GTL+ signals referenced BCLK0 rising edge Crossing Voltage (VCROSS). Asynchronous GTL+ signal timings referenced GTLREF. These signals driven asynchronously. .Refer Section additional timing requirements entering leaving power states. Refer PWRGOOD signal definition Section more detail information behavior signal. Length assertion PROCHOT# does equal internal clock modulation time. Time allocated after assertion PROCHOT# processor complete current instruction execution.
Table System Specifications (Reset Conditions)
Parameter T45: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#) Setup Time T46: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#, A20M#, IGNNE#, LINT[1:0]) Hold Time T47: Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time T48: Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time NOTES: Before de-assertion RESET# After clock that de-asserts RESET#. After assertion RESET#. Unit BCLKs Figure Notes
BCLKs
BCLKs
Table Signal Group Specifications (Page
Parameter T55: Period T56: Rise Time T57: Fall Time T58: TMS, Rise Time T59: TMS, Fall Time T61: TDI, Setup Time T62: TDI, Hold Time 60.0 Unit Figure Notes 1,2,3,9
Intel® XeonProcessor
Table Signal Group Specifications (Page
Parameter T63: Clock Output Delay T64: TRST# Assert Time Unit TTCK Figure Notes 1,2,3,9
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. 100% tested. Specified design characterization. timings signals referenced signal GTLREF processor pins. signal timings (TMS, TDI, etc) referenced GTLREF processor pins. Rise fall times measured from points signal swing. Referenced rising edge TCK. Referenced falling edge TCK. TRST# must held asserted periods guarantee that recognized processor. Specification minimum swing defined between VT+. This assumes minimum edge rate 0.5V/ns. recommended that asserted while TRST# being deasserted.
Table SMBus Signal Group Specifications
Parameter T70: SM_CLK Frequency T71: SM_CLK Period T72: SM_CLK High Time T73: SM_CLK Time T74: SMBus Rise Time T75: SMBus Fall Time T76: SMBus Output Valid Delay T77: SMBus Input Setup Time T78: SMBus Input Hold Time T79: Free Time T80: Hold Time after Repeated Start Condition T81: Repeated Start Condition Setup Time T82: Stop Condition Setup Time 0.02 0.02 Unit Figure Notes 1,2,3
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. These parameters based design characterization tested. timings SMBus signals referenced VIL_MAX VIL_MIN measured processor pins. Refer Figure Minimum time allowed between request cycles. Rise time measured from (VIL_MAX 0.15V) (VIH_MIN 0.15V). Fall time measured from (0.9 SM_VCC) (VIL_MAX 0.15V). parameters specified Table Following write transaction, internal write cycle time 10ms must allowed before starting next transaction.
Intel® XeonProcessor
2.14
Processor Timing Waveforms
following figures used conjunction with timing tables, Table through Table
Note:
Figure through Figure following apply: common clock timings AGTL+ signals referenced Crossing Voltage (VCROSS) BCLK[1:0] rising edge BCLK0. common clock AGTL+ signal timings referenced GTLREF processor core (pads). source synchronous timings AGTL+ signals referenced their associated strobe (address data) GTLREF. Source synchronous data signals referenced falling edge their associated data strobe. Source synchronous address signals referenced rising falling edge their associated address strobe. source synchronous AGTL+ signal timings referenced GTLREF processor core (pads). timings AGTL+ strobe signals referenced BCLK[1:0] VCROSS. AGTL+ strobe signal timings referenced GTLREF processor core (pads). timings signals referenced signal processor pins. signal timings (TMS, TDI, etc) referenced processor core (pads). timings SMBus signals referenced SM_CLK signal SM_VCC processor pins. SMBus signal timings (SM_DAT, SM_ALERT#, etc) referenced VIL_MAX VIL_MIN processor pins.
Figure Electrical Test Circuit
mils, ohms, ps/in 2.4nH
Rload
1.2pF Timings specified this point Rload ohms
Intel® XeonProcessor
Figure Clock Waveform
T56, (Rise Time) T57, (Fall Time) (Period)
rise fall times, measured between points. referenced Vcc.
Figure Differential Clock Waveform
Overshoot BCLK1 Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 Undershoot
(BCLK[1:0] period) BCLK[1:0] Period stability (not shown) (BCLK[1:0] pulse high time) (BCLK[1:0] pulse time) BCLK[1:0] rise time through threshold region BCLK[1:0] fall time through threshold region
Intel® XeonProcessor
Figure System Common Clock Valid Delay Timing Waveform
BCLK1 BCLK0
Common Clock Signal driver) Common Clock Signal receiver)
valid valid
valid
T10: Common Clock Output Valid Delay T11: Common Clock Input Setup T12: Common Clock Input Hold Time
Figure System Source Synchronous (Address) Timing Waveform
BCLK1 BCLK0 ADSTB# driver)
valid valid
driver)
ADSTB# receiver)
receiver)
valid
valid
T23: Source Sync. Address Output Valid Before Address Strobe T24: Source Sync. Address Output Valid After Address Strobe T27: Source Sync. Input Setup BCLK T26: Source Sync. Input Hold Time T25: Source Sync. Input Setup Time T28: First Address Strobe Second Address Strobe T20: Source Sync. Output Valid Delay T31: Address Strobe Output Valid Delay
Intel® XeonProcessor
Figure System Source Synchronous (Data) Timing Waveform
BCLK1 BCLK0 DSTBp# driver)
DSTBn# driver)
driver)
DSTBp# receiver)
DSTBn# receiver)
receiver)
T11: Source Sync. Data Output Valid Delay Before Data Strobe T12: Source Sync. Data Output Valid Delay After Data Strobe T17: Source Sync. Setup Time BCLK T30: Source Sync. Data Strobe (DSTBN#) Output Valid Delay T15: Source Sync. Input Setup Time T16: Source Sync. Input Hold Time T29: First Data Strobe Subsequent Strobes T20: Source Sync. Data Output Valid Delay
Intel® XeonProcessor
Figure System Reset Configuration Timing Waveform
BCLK RESET# Configuration (A20M#, IGNNE# LINT[1:0]) Configuration (A[35:3], SMI#, INIT#, BR[3:0]#) PWRGOOD (AGTL+ Input Pulse Width, Minimum) (RESET# Pulse Width) (Reset Configuration Signals Setup Time) (Reset Configuration Signals Hold Time) (Reset Configuration Signals Delay Time) (Reset Configuration Signals Setup Time) Safe Valid Valid
Figure Power-On Reset Configuration Timing Waveform
BCLK
core, VCC, VREF PWRGOOD RESET#
Configuration (A20M#, IGNNE#, LINT[1:0]) (PWRGOOD Inactive Pulse Width)
Valid Ratio
TaTa (PWRGOOD Inactive Pulse Width) T20a (PWERGOOD Inactive Pulse Width) (RESET# Pulse Width) TcTc (Reset Configuration SignalsSignals (A20M#, IGNNE#, LINT[1:0]) Hold Time) Time) T22, (Reset Configuration (A20M#, (A20M#, IGNNE#, LINT[0:1]) Hold (Reset Configuration Signals IGNNE#, LINT[0:1]) Hold Time) (PWRGOOD RESET# Delay Time)
PCD-765b
Intel® XeonProcessor
Figure Valid Delay Timing Waveform
(Valid Time) (Setup Time) (Hold Time)
Figure Test Reset (TRST#), Async GTL+ Input, PROCHOT# Timing Waveform
(TRST# Pulse Width), (PROCHOT# Pulse Width), GTLREF
Figure THERMTRIP# Power Down Waveform
THERMTRIP#
seconds Note: THERMTRIP# undefined when RESET# active
Intel® XeonProcessor
Figure SMBus Timing Waveform
HD;STA
HD;STA
HD;DAT
HIGH
SU;DAT
SU;STA
SU;STO
Data START START
STOP
STOP
HIGH
HD;STA HD;DAT
SU;STA SU;STD
SU;DAT
Figure SMBus Valid Delay Timing Waveform
SM_CLK
DATA VALID SM_DAT
DATA OUTPUT
Intel® XeonProcessor
System Signal Quality Specifications
Source synchronous data transfer requires clean reception data signals their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, excessive voltage swing will adversely affect system timings. Ringback signal non-monotinicity cannot tolerated since these phenomena inadvertently advance receiver state machines. Excessive signal swings (overshoot undershoot) detrimental silicon gate oxide integrity, cause device failure absolute voltage limits exceeded. Additionally, overshoot undershoot cause timing degradation build inter-symbol interference (ISI) effects. these reasons, crucial that designer work towards solution that provides acceptable signal quality across systematic variations encountered volume manufacturing. This section documents signal quality metrics used derive topology routing guidelines through simulation specifications specified processor core (pad measurements). overshoot/undershoot checker tool, packaged with buffer models, utilized determine pass/fail signal quality conditions found through simulation analysis with Intel®XeonProcessor Signal Integrity Models (IBIS format). This tool takes into account specifications contained this section. Specifications signal quality measurements processor core only only observable through simulation. same true system timing specifications Section 2.13. Therefore, proper simulation processor system only means verify proper timing signal quality metrics.
System Clock (BCLK) Signal Quality Specifications Measurement Guidelines
Table describes signal quality specifications processor pads processor system clock (BCLK) signals. Figure describes signal quality waveform system clock processor pads.
Table BCLK Signal Quality Specifications
Parameter Unit Figure Notes1
BCLK[1:0] Overshoot BCLK[1:0] Undershoot BCLK[1:0] Ringback Margin BCLK[1:0] Threshold Region
0.20
0.30 0.30 0.10
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Intel® XeonProcessor
Figure BCLK[1:0] Signal Integrity Waveform
Overshoot BCLK1 Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 Undershoot
System Signal Quality Specifications Measurement Guidelines
Ringback Guidelines
Many scenarios have been simulated generate system layout guidelines which available appropriate platform design guidelines. Table provides signal quality specifications AGTL+ asynchronous GTL+ signal groups. Table demonstrates signal quality specifications signal group. These specifications simulating signal quality processor core pads Maximum allowable overshoot undershoot specifications given duration time detailed Table through Table System ringback tolerance AGTL+ asynchronous GTL+ signal groups shown Figure (low-to-high transitions) Figure (high-to-low transitions). signal group includes hysteresis input buffers thus relaxed ringback requirements when compared other buffer types. Figure shows system ringback tolerance low-to-high transitions Figure high-to-low transitions. hysteresis values found Table page
3.2.1
Table Ringback Specifications AGTL+ Asynchronous GTL+ Signal Groups
Signal Group Transition Maximum Ringback (with Input Diodes Present) Unit Figure Notes
AGTL+, Async GTL+ AGTL+, Async GTL+
High High
GTLREF 0.100 GTLREF 0.100
1,2,3,4,5,6,7 1,2,3,4,5,6,7
NOTES: signal integrity specifications measured processor core (pads). Unless otherwise noted, specifications this table apply Intel® Xeonprocessor frequencies cache sizes. Specifications edge rate V/ns. values specified design characterization.
Intel® XeonProcessor
Please Section 3.2.3 maximum allowable overshoot. Ringback between GTLREF GTLREF supported. Intel recommends simulations exceed ringback value GTLREF allow margin other sources system noise.
Figure Low-to-High Receiver Ringback Tolerance AGTL+ Async GTL+ Signals
+100 GTLREF -100
Noise Margin
Figure High-to-Low Receiver Ringback Tolerance AGTL+ Async GTL+ Signals
+100 GTLREF -100
Noise Margin
Intel® XeonProcessor
Table Ringback Specifications Signal Group
Signal Group Transition Maximum Ringback (with input diodes present) Units Figure Notes
High High
Vt+(max) Vt-(max) Vt-(min) Vt+(min)
NOTES: signal integrity specifications measured processor core (pads). Unless otherwise noted, specifications this table apply Intel® Xeonprocessor frequencies cache sizes. Specifications edge rate V/ns. values specified design characterization. Please Section 3.2.3 maximum allowable overshoot.
Figure Low-to-High Receiver Ringback Tolerance Signals
Threshold Region switch receiver logic
(max) (min) (max)
Allowable Ringback
Intel® XeonProcessor
Figure High-to-Low Receiver Ringback Tolerance Signals
Allowable Ringback
(min) (max) (min)
Threshold Region switch receiver logic
3.2.2
Overshoot/Undershoot Guidelines
Overshoot undershoot) absolute value maximum voltage above below VSS. overshoot/undershoot specifications limit transitions beyond fast signal edge rates. processor damaged repeated overshoot undershoot events input, output, buffer charge large enough (i.e., over/undershoot great enough). Determining impact overshoot/undershoot condition requires knowledge magnitude, pulse direction, activity factor (AF). Permanent damage processor likely result excessive overshoot/undershoot. When performing simulations determine impact overshoot undershoot, diodes must properly characterized. protection diodes voltage clamps will provide overshoot undershoot protection. diodes modelled within Intel buffer models clamp undershoot overshoot will yield correct simulation results. other buffer models being used characterize processor system bus, care must taken ensure that models clamp extreme voltage levels. Intel buffer models also contain capacitance characterization. Therefore, removing diodes from signal integrity model will impact results yield excessive overshoot/undershoot.
3.2.3
Overshoot/Undershoot Magnitude
Magnitude describes maximum potential difference between signal voltage reference level. Intel Xeon processor both referenced VSS. important note that overshoot undershoot conditions separate their impact must determined independently.
Intel® XeonProcessor
Overshoot/undershoot magnitude levels must observe absolute maximum specifications listed Table through Table These specifications must violated time regardless activity system state. Within these specifications threshold levels that define different allowed pulse duration. Provided that magnitude overshoot/undershoot within absolute maximum specifications (2.3V overshoot -0.65V undershoot), pulse magnitude, duration activity factor must used determine overshoot/undershoot pulse within specifications.
3.2.4
Overshoot/Undershoot Pulse Duration
Pulse duration describes total time overshoot/undershoot event exceeds overshoot/ undershoot reference voltage (VCC). total time could encompass several oscillations above reference voltage. Multiple overshoot/undershoot pulses within single overshoot/undershoot event need measured determine total pulse duration. Note Oscillations below reference voltage subtracted from total overshoot/ undershoot pulse duration.
3.2.5
Activity Factor
Activity Factor (AF) describes frequency overshoot undershoot) occurrence relative clock. Since highest frequency assertion common clock signal every other clock, indicates that specific overshoot undershoot) waveform occurs every other clock cycle. Thus, 0.01 indicates that specific overshoot undershoot) waveform occurs time every clock cycles. source synchronous signals (address, data, associated strobes), activity factor reference strobe edge. highest frequency assertion source synchronous signal every active edge associated strobe. indictees that specific overshoot undershoot) waveform occurs every strobe cycle. specifications provided Table through Table show maximum pulse duration allowed given overshoot/undershoot magnitude specific activity factor. Each table entry independent others, meaning that pulse duration reflects existence overshoot/ undershoot events that magnitude ONLY. platform with overshoot/undershoot that just meets pulse duration specific magnitude where means that there other overshoot/undershoot events, even lesser magnitude (note that then event occurs times other events occur). Note Activity factor common clock AGTL+ signals referenced BCLK[1:0] frequency. Note Activity factor source synchronous (2X) signals referenced ADSTB[1:0]#. Note Activity factor source synchronous (4X) signals referenced DSTBP[3:0]# DSTBN[3:0]#.
3.2.6
Reading Overshoot/Undershoot Specification Tables
overshoot/undershoot specification processor simple single value. Instead, many factors needed determine what over/undershoot specification addition magnitude overshoot, following parameters must also known: width overshoot activity factor (AF). determine allowed overshoot particular overshoot event, following must done:
Intel® XeonProcessor
Determine signal group that particular signal falls into. AGTL+ signals operating source synchronous domain, Table AGTL+ signals operating source synchronous domain, Table signal AGTL+ signal operating common clock domain, Table Finally, other signals reside domain (asynchronous GTL+, TAP, etc.) referenced Table Determine magnitude overshoot undershoot (relative VSS). Determine activity factor (how often does this overshoot occur?). Next, from appropriate specification table, determine maximum pulse duration nanoseconds) allowed. Compare specified maximum pulse duration signal being measured. pulse duration measured less than pulse duration shown table, then signal meets specifications. Undershoot events must analyzed separately from overshoot events they mutually exclusive.
3.2.7
Determining System Meets Overshoot/Undershoot Specifications
overshoot/undershoot specifications listed following tables specify allowable overshoot/undershoot single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their parameters (duration, magnitude). While each overshoot meet overshoot specification, when total impact overshoot events, system fail. guideline ensure system passes overshoot undershoot specifications shown below. Results from simulation also evaluated utilizing Intel® XeonProcessor Overshoot Checker Tool through time-voltage data files. Ensure signal ever exceeds -0.25V only overshoot/undershoot event magnitude occurs, ensure meets over/undershoot specifications following tables multiple overshoots and/or multiple undershoots occur, measure worst case pulse duration each magnitude compare results against specifications. these worst case overshoot undershoot events meet specifications (measured time specifications) table (where AF=1), then system passes. following notes apply Table through Table NOTES: Absolute Maximum Overshoot magnitude 2.3V must never exceeded. Absolute Maximum Overshoot measured referenced VSS, Pulse Duration overshoot measured relative VCC. Absolute Maximum Undershoot Pulse Duration undershoot measured relative VSS. Ringback below cannot subtracted from overshoots/undershoots. Lesser undershoot does allocate overshoot with longer duration greater magnitude. OEM's strongly encouraged follow Intel layout guidelines. values specified design characterization.
Intel® XeonProcessor
Table Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot Absolute Maximum Undershoot Pulse Duration (ns) Pulse Duration (ns) Pulse Duration (ns) 0.01 Notes 1,2,3
2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75
-0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10
0.07 0.12 0.23 0.42 0.74 1.38 2.50 4.50 5.00 5.00 5.00 5.00
0.65 1.22 2.25 4.15 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00
5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00 5.00
NOTES: These specifications measured processor pad. Assumes BCLK period referenced associated source synchronous strobes.
Table Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot Absolute Maximum Undershoot Pulse Duration (ns) Pulse Duration (ns) Pulse Duration (ns) 0.01 Notes 1,2,3
2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75
-0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10
0.13 0.24 0.45 0.83 1.48 2.76 5.00 5.00 10.0 10.0 10.0 10.0
1.30 2.44 4.50 8.30 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0
NOTES: These specifications measured processor pad. Assumes BCLK period referenced associated source synchronous strobes.
Intel® XeonProcessor
Table Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot Absolute Maximum Undershoot Pulse Duration (ns) Pulse Duration (ns) Pulse Duration (ns) 0.01 Notes 1,2,3
2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75
-0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10
0.26 0.49 0.90 1.66 2.96 5.52 10.0 18.0 20.0 20.0 20.0 20.0
2.60 4.88 9.00 16.60 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0
20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0
NOTES: These specifications measured processor pad. BCLK period referenced BCLK[1:0].
Table Asynchronous GTL+ Signal Groups Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot Absolute Maximum Undershoot Pulse Duration (ns) Pulse Duration (ns) Pulse Duration (ns) 0.01 Notes
2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75
-0.65 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10
0.78 1.46 2.70 4.98 8.88 16.56 30.0 54.0 60.0 60.0 60.0 60.0
7.80 14.64 27.0 49.8 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0
60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0 60.0
NOTES: These specifications measured processor pad. These signals assumed time domain.
Intel® XeonProcessor
Figure Maximum Acceptable Overshoot/Undershoot Waveform
Maximum Absolute Overshoot VMAX
Time-dependent Overshoot
GTLREF VMIN Maximum Absolute Undershoot Time-dependent Undershoot
Intel® XeonProcessor
Mechanical Specifications
Intel® Xeonprocessor uses Grid Array (PGA) package technology. Components package include integrated heat spreader (IHS), organic land grid array (OLGA) package flip chip ball grid array (FC-BGA) package containing processor pinned interposer. Mechanical specifications processor given this section. Section terminology listing. Figure provides basic processor assembly drawing better understand components which make entire processor. addition package components, Intel Xeon also includes several passive components, EEPROM, thermal sensor. processor utilizes surface mount zero-insertion force (ZIF) socket installation into system board. Socket Design Guidelines further details socket.
Note:
Figure through Figure following notes apply: Unless otherwise specified, following drawings dimensioned millimeters. dimensions tested, guaranteed design characterization. Figures drawings labelled "Reference Dimensions" provided informational purposes only. Reference Dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference Dimensions checked part processor manufacturing process. Unless noted such, dimensions parentheses without tolerances Reference Dimensions. Drawings scale.
Intel® XeonProcessor
Figure Processor Assembly Drawing (Including Socket)
Note:
This drawing scale reference only. assembly applies Intel Xeon processor package. 603-pin socket supplied reference only. Integrated Heat Spreader (IHS) Thermal Interface Material (TIM) between processor Processor Flip Chip interconnect OLGA (Organic Land Grid Array) package FC-BGA (Flip Chip Ball Grid Array) package OLGA package FC-BGA package solder joints Processor interposer 603-pin socket 603-pin socket solder joints
Intel® XeonProcessor
Processor Mechanical Specifications
Figure Processor View Component Placement Detail
EEPROM
Temperature Sensor
Figure Processor Package Drawing
Intel® XeonProcessor
Table Dimensions Processor Package
Symbol 53.190 42.400 38.400 1.365 5.268 1.458 4.530 18.821 13.741 17.831 14.503 19.101 1.700 Millimeters Nominal 53.340 42.500 38.500 2.000 5.420 1.610 5.030 19.050 13.970 1.270 18.085 14.630 19.355 2.000 Notes 53.490 42.600 38.600 2.635 5.572 1.762 5.530 19.279 14.199 Nominal 18.339 14.757 19.609 2.300
Diameter
Figure details keep-in zone components mounted side processor interposer. components include EEPROM, thermal sensor, resistors capacitors.
Figure Processor View Component Height Keep-in
Intel® XeonProcessor
Figure details keep specification pin-side components. processor contain side capacitors mounted processor package. capacitors will exposed within opening interposer cavity. This keep-in specification applies both packages.
Figure Processor Cross Section View Side Component Keep-in
OLGA FC-BGA Interposer 1.270mm 13.411mm Component Keepin Socket must allow clearance shoulders mate flush with this surface Component Keepin
Figure Processor Detail
Note:
plating consists micrometers over micrometer 0.254 Diametric true position, pin.
Intel® XeonProcessor
Figure details flatness tilt specifications Intel Xeon processor Tilt measured with reference datum bottom processor interposer.
Figure Processor Flatness Tilt Drawing
Package Load Specifications
Table provides dynamic static load specifications processor IHS. These mechanical load limits should exceeded during heat sink assembly, mechanical stress testing, standard drop shipping conditions. heat sink attach solutions must induce continuous stress onto processor with exception uniform load maintain heat sink-toprocessor thermal interface. recommended portion processor interposer mechanical reference load bearing surface thermal solutions.
Table Package Dynamic Static Load Specifications
Parameter Unit Notes
Static Dynamic
NOTES: This specification applies uniform compressive load. This maximum static force that applied heatsink clip maintain heatsink processor interface. These parameters based design characterization tested. Dynamic loading specifications defined assuming maximum duration 11ms.
Intel® XeonProcessor
Processor Insertion Specifications
processor inserted removed times from 603-pin socket meeting 603-Pin Socket Design Guidelines document. Note that this specification based design characterization tested.
Processor Mass Specifications
Table specifies processors mass. This includes components which make entire processor product.
Table Processor Mass
Processor Mass (grams)
Intel Xeon Intel Xeon
processor with MByte cache processor with KByte cache
37.51 37.51
Processor Materials
processor assembled from several components. basic material properties described Table
Table Processor Material Properties
Component Material Notes
Integrated Heat Spreader OLGA package, FC-BGA package Interposer Interposer pins
Nickel plated copper Resin Gold over nickel
Processor Markings
following section details processor top-side bottom-side laser markings engineering samples production units. provided identification processor.
Intel® XeonProcessor
Figure Processor Top-Side Markings
Intel® Confidential i(m) ©'02
Matrix Dynamic Laser Mark Area
ATPO Mark characters) D0096109 0032 Serial Number Mark digits)
Figure Processor Bottom-Side Markings
Processor
Prod(SSPEC) Mark Group Line Group Line Group Line Group Line Group Line Group Line Group Line {Intel Brand} I(m)©'02 XXXXXXXX YYYY 1600MP/1ML3/400/1.7V SXXXX Costa Rica XXXXXXXX-YYYY Legal mark ATPO mark Serial number mark Product Code* Sspec, Assy site FPO-SN mark Description
Exampl show 1.60GHz Intel® Xeon processor
NOTE:
Approximate character size laser markings are: height 1.27mm (0.050"), width 0.81 1.27mm (0.032 0.050"). characters will upper case.
Intel® XeonProcessor
Processor Pin-Out Diagrams
This section provides views processor grid. Figure Figure detail coordinates processor pins. Both processors share same out.
Figure Processor Pin-out Diagram View
COMMON CLOCK
ADDRESS
COMMON CLOCK
Async JTAG
Vcc/Vss
Intel Xeon PROCESSOR
View
Vcc/Vss
CLOCKS
Signal Power Ground
DATA
SM_VCC GTLREF Reserved/No Connect
SMBus
Intel® XeonProcessor
Figure Processor Pin-out Diagram Bottom View
Async JTAG
COMMON CLOCK
ADDRESS
COMMON CLOCK
Vcc/Vss
Intel Xeon PROCESSOR
Bottom View
Vcc/Vss
SMBus
DATA
Signal Power Ground SM_VCC GTLREF Reserved/No Connect
CLOCKS
interposer Materials
Intel® XeonProcessor
Listing Signal Definitions
Processor Assignments
Section contains system signal groups Table Intel® Xeonprocessor This section provides sorted list Table Table Table listing processor pins ordered alphabetically name. Table listing processor pins ordered number.
Note:
Note that "N/C" connect) indicates associated connected processor silicon, however these pins utilized future processors intended 603-pin socket. "Reserved" pins must never utilized platform, they remain unconnected.
5.1.1
Listing Name
Table Listing Name
Direction Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type
A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27#
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
A28# A29# A30# A31# A32# A33# A34# A35# A20M# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI#
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Common Source Sync Source Sync Common Common Common Common Common Common Common Common Common Common Common
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
BR0# BR1# BR2# BR3# COMP0 COMP1 D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30#
AD16 AA27 AA25 AD27 AA24 AB26 AB25 AB23 AA22 AA21 AB20 AB22 AB19 AA19 AE26 AC26 AD25 AE25 AC24 AD24 AE23 AC23 AA18 AC20 AC21 AE22 AE20 AD21 AD19
Common Common Reserved Reserved Power/Other Power/Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Input/Output Input Reserved Reserved Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DBI0# DBI1#
AB17 AB16 AA16 AC17 AE13 AD18 AB15 AD13 AD14 AD11 AC12 AE10 AC11 AD10 AA13 AA14 AC14 AB12 AB13 AA11 AA10 AB10 AC27 AD22
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Common Common Source Sync Source Sync
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
DBI2# DBI3# DP0# DP1# DP2# DP3# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FERR# GTLREF GTLREF GTLREF GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# MCERR# ODTEN PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4#
AE12 AC18 AE19 AC15 AE17
Source Sync Source Sync Common Common Common Common Common Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Power/Other Power/Other Power/Other Power/Other Common Common Async GTL+ Async GTL+ Async GTL+ Async GTL+ Async GTL+ Common Common Power/Other Async GTL+ Async GTL+ Source Sync Source Sync Source Sync Source Sync Source Sync
Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
A301
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
B302
C301
D302
E312
H302
J312
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
Reserved Reserved Reserved Reserved Reserved
L301
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved RESET# RS0# RS1# RS2# RSP# SKTOCC# SLP# SM_ALERT# SM_CLK SM_DAT SM_EP_A0 SM_EP_A1 SM_EP_A2 SM_TS_A0 SM_TS_A1 SM_VCC SM_VCC SM_WP SMI# STPCLK#
AA311 AB12 AB30 AB31 AC302 AC31 AD301 AD31 AE15 AE16 AD28 AC28 AC29 AA29 AB29 AB28 AA28 AE28 AE29 AD29
Reserved Reserved Reserved Reserved Reserved Reserved Common Common Common Common Common Power/Other Async GTL+ SMBus SMBus SMBus SMBus SMBus SMBus SMBus SMBus Power/Other Power/Other SMBus Async GTL+ Async GTL+
Reserved Reserved Reserved Reserved Reserved Reserved Input Input Input Input Input Output Input Output Input Input/Output Input Input Input Input Input
M311
R302
T312
V301
W302
Input Input Input Input Input Output
Y312
AA30
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 THERMTRIP# TRDY# TRST#
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Async GTL+ Common Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Input Input Input Input Input Input Input Output Input Input Input
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
AA12 AA20 AA26
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
VCCA VCCIOPLL VCCSENSE VID0 VID1 VID2 VID3 VID4
AB14 AB18 AB24 AC10 AC16 AC22 AD12 AD20 AD26 AE14 AE18 AE24
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Output Output Output Output Output Output
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Intel® XeonProcessor
Table Listing Name
Name Signal Buffer Type Direction
Table Listing Name
Name Signal Buffer Type Direction
AA15 AA17 AA23 AB11 AB21 AB27
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
VSSA VSSSENSE
AC13 AC19 AC25 AD15 AD17 AD23 AE11 AE21 AE27
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output
NOTES: These pins connected enable platform forward compatible with future processors. These pins connected enable platform forward compatible with future processors.
Intel® XeonProcessor
5.1.2
Listing Number
Table contains listing Intel Xeon processor pins order number.
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
Reserved SKTOCC# Reserved VtSS A32# A33# A26# A20# A14# A10# Reserved Reserved LOCK# HITM# Reserved Reserved VID4
Reserved Power/Other Power/Other Reserved Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Reserved Reserved Common Power/Other Source Sync Source Sync Power/Other Source Sync Common Power/Other Reserved Power/Other Power/Other Power/Other Reserved Power/Other Power/Other
Reserved
OTDEN A31# A27# A21# A22# A13# A12# A11# REQ0# REQ1# REQ4# LINT0 PROCHOT# VCCSENSE VID3 Reserved RSP#
Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Common Power/Other Common Common Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Common
Input
Output Reserved
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output
Reserved Reserved Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input Output
Input/Output Input/Output
Output
Input Reserved
Reserved
Output
Reserved Input
Output
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
A35# A34# A30# A23# A16# A15# REQ3# REQ2# DEFER# IGNNE# SMI# VID2 STPCLK# INIT# MCERR# AP1# BR3# A29#
Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Common Common Power/Other Common Power/Other Async GTL+ Async GTL+ Power/Other Power/Other Power/Other Power/Other Async GTL+ Power/Other Async GTL+ Common Power/Other Common Common Power/Other Source Sync Input/Output Input/Output Reserved Input Input/Output Output Input Input Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
D302
A25# A18# A17# ADS# BR0# RS1# BPRI# Reserved VSSSENSE VID1 BPM5# IERR# BPM2# BPM4# AP0# BR2# A28# A24# COMP1 DRDY#
Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Common Common Power/Other Common Common Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Common Power/Other Common Common Power/Other Common Common Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Common
Input/Output
Input/Output Input/Output Input/Output
Input/Output Input/Output
Input Input
Reserved Output
Output Input/Output Output
Input/Output Input/Output
Input/Output Reserved
Input/Output Input/Output
Input
Input/Output
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
TRDY# RS0# HIT# FERR# VID0 BPM3# BPM0# BPM1# GTLREF BINIT# BR1# ADSTB1# A19# ADSTB0# DBSY# BNR# RS2# GTLREF TRST#
Common Power/Other Common Common Power/Other Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Common Common Power/Other Common Power/Other Power/Other Common Common Power/Other Source Sync Source Sync Power/Other Source Sync Common Power/Other Common Common Power/Other Power/Other
Input
THERMTRIP# A20M# LINT1
Power/Other Async GTL+ Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Output Input
Input Input/Output
Input Output
F302
Output
Output
Input/Output Input/Output
Input/Output Input
Input/Output Input
Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
H311
L301
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
P301
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
N311
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
T301 T312
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
V312 W302
Reserved BCLK1 TESTHI0 TESTHI1 TESTHI2 GTLREF GTLREF Reserved BCLK0 TESTHI3 RESET# D62# DSTBP3# DSTBN3# DSTBP2# DSTBN2# DSTBP1# DSTBN1#
Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Common Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync
Reserved
Input Input Input Input Input Input
Reserved Input
Input
Input Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
DSTBP0# DSTBN0# Reserved Reserved SM_TS_A1 Reserved VSSA TESTHI4 D61# D54# D53# D48# D49# D33# D24# D15# D11# D10#
Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Reserved Reserved SMBus Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input Reserved Input/Output Reserved Reserved Input Input/Output Input/Output Input/Output Input/Output
AA25 AA26 AA27 AA28 AA29 AA302 AA31
SM_TS_A0 SM_EP_A0 Reserved VCCA D63# PWRGOOD DBI3# D55# D51# D52# D37# D32# D31# D14# D12# D13# SM_EP_A2 SM_EP_A1
Source Sync Power/Other Source Sync SMBus SMBus Power/Other Reserved Power/Other Power/Other Source Sync Async GTL+ Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other SMBus SMBus
Input/Output
Input/Output Input Input
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30
Reserved Input
AA11 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24
Input
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input Input
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
AB312 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30
Reserved D60# D59# D56# D47# D43# D41# D50# DP2# D34# DP0# D25# D26# D23# D20# D17# DBI0# SM_CLK SM_DAT Reserved VCCIOPLL TESTHI5
Reserved Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Common Power/Other Source Sync Common Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync SMBus SMBus Reserved Power/Other Power/Other Power/Other Power/Other
Reserved
AD10
D57# D46# D45# D40# D38# D39# COMP0 D36# D30# D29# DBI1# D21# D18# SM_ALERT# SM_WP Reserved TESTHI6 SLP# D58# D44# D42# DBI2#
Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync SMBus SMBus Power/Other Power/Other Reserved Power/Other Async GTL+ Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Input/Output Input/Output Input/Output Reserved Input Input Input/Output Input/Output Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Input/Output Input/Output
AD11 AD12 AD13
Input/Output Input/Output
AD14 AD15 AD16
Input/Output Input/Output
AD17 AD18 AD19
Input/Output Input/Output
AD20 AD21 AD22
Input/Output Input/Output
AD23 AD24 AD25
Input/Output Input/Output
AD26 AD27 AD28
Input/Output Input/Output
AD29 AD30
AD312 Input/Output Input/Output Input Output Reserved AE10 Input Input AE11 AE12
AC31
Intel® XeonProcessor
Table Listing Number
Name Signal Buffer Type Direction
Table Listing Number
Name Signal Buffer Type Direction
AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23
D35# Reserved Reserved DP3# DP1# D28# D27# D22#
Source Sync Power/Other Reserved Reserved Common Power/Other Common Source Sync Power/Other Source Sync Source Sync
Input/Output
AE24 AE25
D19# D16# SM_VCC SM_VCC
Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Input/Output Input/Output
Reserved Reserved Input/Output
AE26 AE27 AE28 AE29
Input/Output Input/Output
NOTES: These pins connected enable platform forward compatible with future processors. These pins connected enable platform forward compatible with future processors.
Input/Output Input/Output
Intel® XeonProcessor
Signal Definitions
Table Signal Definitions (Page
Name Type Description
A[35:3]#
A[35:3]# (Address) define 236-byte physical memory address space. sub-phase address phase, these pins transmit address transaction. sub-phase these pins transmit transaction type information. These signals must connect appropriate pins agents Intel Xeon processor system bus. A[35:3]# protected parity signals AP[1:0]#. A[35:3]# source synchronous signals latched into receiving buffers ADSTB[1:0]#. active-to-inactive transition RESET#, processors sample subset A[35:3]# pins determine their power-on configuration. Section 7.1. A20M# (Address-20 Mask) asserted, processor masks physical address (A20#) before looking line internal cache before driving read/write transaction bus. Asserting A20M# emulates 8086 processor's address wraparound 1-Mbyte boundary. Assertion A20M# only supported real mode. A20M# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding write transaction This signal also sampled deassertion RESET# core-to-system frequency ratio. Section Chapter 10.0 more details. ADS# (Address Strobe) asserted indicate validity transaction address A[35:3]# pins. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction. This signal must connect appropriate pins processor system agents. Address strobes used latch A[35:3]# REQ[4:0]# their rising falling edge. AP[1:0]# (Address Parity) driven request initiator along with ADS#, A[35:3]#, transaction type REQ[4:0]# pins. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connect appropriate pins Intel Xeon processor system agents. following table defines coverage model these signals.
A20M#
ADS#
ADSTB[1:0]#
AP[1:0]#
Request Signals
Subphase
Subphase
A[35:24]# A[23:3]# REQ[4:0]#
AP0# AP1# AP1#
AP1# AP0# AP0#
BCLK[1:0]
differential pair BCLK (Bus Clock) determines frequency. processor system agents must receive these signals drive their outputs latch their inputs. external timing parameters specified with respect rising edge BCLK0 crossing falling edge BCLK1.
Intel® XeonProcessor
Table Signal Definitions (Page
Name Type Description
BINIT#
BINIT# (Bus Initialization) observed driven processor system agents used, must connect appropriate pins such agents. BINIT# driver enabled during power configuration, BINIT# asserted signal condition that prevents reliable future information. BINIT# observation enabled during power-on configuration (see Section 7.1) BINIT# sampled asserted, symmetric agents reset their LOCK# activit
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