DSP56305 SINGLE CHIP CHANNEL CODEC DIGITAL SIGNAL PROCESSOR

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DSP56305 SINGLE CHIP CHANNEL CODEC DIGITAL SIGNAL PROCESSOR

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DSP56305
SINGLE CHIP CHANNEL CODEC DIGITAL SIGNAL PROCESSOR
Motorola designed DSP56305 deliver high performance required support Global System Mobile (GSM) communications applications that digital signal processing perform channel equalization, channel coding, speech coding. combining three dedicated on-chip hardware co-processors (filter, Viterbi, cyclic code) with DSP56300 core, DSP56305 performs complex signal processing required single Radio Frequency (RF) carrier chip, satisfying demand high integration cost. DSP56300 core includes on-chip PLL, Data ALU, instruction cache, on-chip debugging modules, on-chip program data memory, channels, external memory expansion port. addition co-processors, DSP56305 provides types serial ports, PCI/Universal 32-bit Host Interface, timers (see Figure DSP56305 provides industry-leading performance rate MIPS
Memory Expansion Area
Program Memory* Timer Host ESSI FCOP VCOP CCOP *default PM_EB Memory* 3.75 *default XM_EB YM_EB Memory
PIO_EB
Peripheral Expansion Area
Address Generation Unit Channel Unit
External Address Switch Address External Interface Cache Control Control
24-Bit DSP56300 Core
Internal Data Switch EXTAL XTAL Clock Generator RESET PINIT/NMI Program Interrupt Controller Program Decode Controller MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Program Address Generator Data 56-bit 56-bit Accumulators 56-bit Barrel Shifter
External Data Switch
Data
Power Mngmnt JTAG OnCE
AA0812
Figure DSP56305 Block Diagram
This document contains information product. Specifications information herein subject change without notice.
©1996 MOTOROLA, INC.
DSP56305 DSP56305 Features
DSP56305 FEATURES
High performance DSP56300 core Million Instructions Second (MIPS) with clock Object code compatible with DSP56000 core Highly parallel instruction Fully pipelined 24-bit parallel Multiplier-Accumulator (MAC) 56-bit parallel barrel shifter 24-bit 16-bit arithmetic support under software control Position independent code support Addressing modes optimized applications On-chip instruction cache controller On-chip memory-expandable hardware stack Nested hardware loops Fast auto-return interrupts On-chip concurrent six-channel Direct Memory Access (DMA) controller On-chip Phase Lock Loop (PLL) clock generator On-Chip Emulation (OnCETM) module JTAG Test Access Port (TAP) Address Tracing mode reflects internal accesses external port 252-pin PBGA package Pin-compatible 252-pin PBGA package with DSP56301
On-chip memories Program RAM, instruction cache, data RAM, data sizes programmable:
Instruction Cache disabled enabled disabled enabled Switch Mode disabled disabled enabled enabled Program Size 6656 24-bit 5632 24-bit 7680 24-bit 6656 24-bit Instruction Cache Size 1024 24-bit 1024 24-bit Data Size 3840 24-bit 3840 24-bit 2816 24-bit 2816 24-bit Data Size 2048 24-bit 2048 24-bit 2048 24-bit 2048 24-bit
6144 24-bit Program 3072 24-bit data 24-bit bootstrap
DSP56305P/D
DSP56305 DSP56305 Features
Off-chip memory expansion Data memory expansion 24-bit word memory spaces Program memory expansion 24-bit word memory space External memory expansion port Chip select logic provides glueless interface SRAMs SSRAMs On-chip DRAM controller provides glueless interface DRAMs
On-chip peripherals Rev. 2.1-compliant 32-bit parallel PCI/Universal Host Interface (HI32) with glueless interface other DSP563xx buses interface requires only 74LS45-style buffer Enhanced Synchronous Serial Interfaces (ESSI) Serial Communications Interface (SCI) with baud rate generator Triple timer module forty-two programmable General Purpose Input/Output pins (GPIO), depending which peripherals enabled
On-chip co-processors Filter Co-Processor (FCOP) implements wide variety convolution correlation filtering algorithms. applications, FCOP cross-correlates between received training sequence known midamble sequence estimate channel impulse response, then performs match filtering received data symbols using coefficients derived from that estimated channel. Viterbi Co-Processor (VCOP) implements Maximum Likelihood Sequential Estimation (MLSE) algorithm channel decoding equalization (uplink) channel convolution coding (downlink). VCOP supports constraint lengths with number states respectively; code rates 1/2, 1/3, 1/4, 1/6; trace-back Trellis depth Cyclic-code Co-Processor (CCOP) executes cyclic code calculations data ciphering deciphering, well parity code generation check. CCOP fully programmable dedicated specific algorithm, well suited A5.1 A5.2 data ciphering algorithms. CCOP generate mask sequences data ciphering, supports Fire encode decode burst error correction, well generation Cyclic Redundancy Code (CRC) syndrome polynomial degree
Reduced power dissipation Very power CMOS design Wait Stop power standby modes Fully-static logic, operation frequency down Optimized power management circuitry
DSP56305P/D
PRODUCT DOCUMENTATION
three documents listed Table required complete description DSP56305 necessary design with part properly. Documentation available from local Motorola distributor, Motorola semiconductor sales office, Motorola Literature Distribution Center, Motorola home page Internet, which will have latest information (see address below). Table DSP56301 Documentation
Topic DSP56300 Family Manual DSP56305 User's Manual DSP56305 Technical Data Description Detailed description DSP56300 family architecture, 24-bit core, instruction Detailed description DSP56305 memory, peripherals, interfaces DSP56305 package descriptions, electrical timing specifications Order Number DSP56300FM/AD DSP56305UM/AD DSP56305/D
Mfax OnCE trademarks Motorola, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/ Affirmative Action Employer.
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USA/Europe/Locations Listed: Motorola Literature Distribution P.O. 20912 Phoenix, Arizona 85036 (800) 441-2447 (602) 303-5454 MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 Asia/Pacific: Motorola Semiconductors H.K. Ltd. Ping Industrial Park Ting Road N.T., Hong Kong 852-2662928 Technical Resource Center: (800) 521-6274 Helpline dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Japan: Nippon Motorola Ltd. Tatsumi-SPD-JLDC Seibu-Butsuryu-Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan 03-3521-8315

DSP56305 SINGLE CHIP CHANNEL CODEC DIGITAL SIGNAL PROCESSOR

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