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M512x : Mega I / O Controller with PnP

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Acer Laboratories Inc.
M512x : Mega I / O Controller with PnP
-Preliminary, Confidential, Proprietary-
M512x : Mega I / O Controller with Plug & Play
FEATURES n n n
Supports Windows 95 Plug and Play Supports 2 serial / 1 parallel / FDC / RTC / KB and PS / 2 mouse functions Supports 22 General Purpose I / O pins Enhanced ESD / LATCH up to over 4KV / 300 mA Supports SPP, PS / 2, EPP, ECP and 1284 compliance Supports 5 GPIO Alternative function pins for Remote Control Supports IR via UART1, UART2 and two additional IR pins Supports Fast Gate A20 and RC functions Supports KBC and RTC enable / disable functions Single-chip Notebook / Desktop solution
Various modes of Parallel Port Supports ECP / EPP / PS / 2 / SPP and 1284 Compliance - IBM PC / XT, PC / AT and PS / 2 compatible Bi-directional parallel port - Enhanced Parallel Port (EPP) compatible - Microsoft and Hewlett Packard Extended Capabilities Port (ECP) compatible
Supports Windows 95 Plug-and-Play Supports 2 Serial / 1 Parallel / FDC / RTC / KB / PS / 2 Mouse functions Supports 22 General Purpose I / O pins - 3 GPIO ports (Ports 1, 2, 3) - 5 GPIO-ALT function pins for Remote Control (Pins 30-34) - 2 General Purpose chip select pins (Pins 24-25) - Supports I C Control Pins
Serial ports - Two high performance 16550 compatible UARTs with send / receive 16-byte FIFOs - Serial Infra Red (SIR) for wireless communications - MIDI (Musical Instrument Digital Interface) compatible
2.88 MB Floppy Disk Controller - Software compatible with 82077 and supports 16-byte data FIFOs - High performance internal data separator - Supports standard 1 Mbps / 500 Kbps / 300 Kbps / 250 Kbps data rate - Supports 3 modes of 3.5" FDD (720K / 1.2M / 1.44MB) - Swappable drives A and B n n n n n n n n
High performance Power Management for FDC, UART and Parallel Port Supports XD-To-SD Bus Buffer and Control Pins Supports Enable / Disable KBC and RTC Supports Fast Gate A20 and RC function Supports External KBC programming pin functions Supports additional IrDA and ASK IR Pins Supports Phoenix KBC (M5123), AMI KBC(M5125) 160-pin PQFP package
Supports FDC through Parallel Port pins Supports AT PS / 2 KB and PS / 2 Mouse Built-in Keyboard Controller and Real Time Clock
07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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Acer Laboratories Inc.
M512x : Mega I / O Controller with PnP
Table of Contents :
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07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
M512x : Mega I / O Controller with PnP
-Preliminary, Confidential, Proprietary-
Section 1 : Introduction
Features and Functions
1.2 M512x Block Diagrams
The following figures show the overall block diagram of the M512x.
07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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M512x : Mega I / O Controller with PnP
ISA Bus interface
SD0-SD7 IORJ IOWJ AEN SA0-SA15 DACK0J-DACK3J DRQ0-DRQ3 TC IRQ1, IRQ3-12, IRQ14-15 MR RDATAJ WGATEJ WDATAJ HDSELJ DIRJ STEPJ DSKCHGJ DRV0-1 PDIR MOT0-1 WPJ TRK0J DENSEL INDEXJ ROMOEJ ROMCSJ RD0-7 CIO 10-17, 20-25, 30-34
SIN1, SOUT1 RTS1J DTR1J CTS1J DSR1J DCD1J RI1J SIN2, SOUT2 RTS2J DTR2J CTS2J DSR2J DCD2J RI2J AUTOFDJ INITJ SLCTINJ STROBEJ BUSY ACKJ PE SLCT ERRORJ IOCHRDY PD0-PD7 XTAL1, 2 VBAT PWG KDAT, KCLK MDAT, MCLK
Serial port 1
Serial port 2
M512x
Floppy disk interface
Printer port interface
BIOS Buffer Common I / O
Figure 1-1
M512x Block Diagram
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07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
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M512x : Mega I / O Controller with PnP
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1.3 Register Overview
Table 1-1 I / O Address Decode Block Name Floppy Disk Serial Port COM1 Serial Port COM2 Parallel port SPP EPP ECP ECP+EPP+SPP KBC RTC Logical Device 0 4 5 3 Function IR support IR support
Address Range Base + (0-5) and + (7) Base + (0-7) Base + (0-7) Base + (0-3) Base + (0-7) Base + (0-3), + (400-402) Base + (0-7), + (400-402) 0x60, 0x64 0x70, 0x71
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M512x : Mega I / O Controller with PnP
Section 2 : Pin Description
2.1 Pinout Diagram
ALi M512x
Figure 2-1. M512x Pin Diagram
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M512x : Mega I / O Controller with PnP
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2.2 Pin Description
Table 2-1 lists the functions of all M512x pins. A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4V nominal). Table 2-1 M512x Pin Description Table Type I / O Description Data bus. These signals are used by the host microprocessor to transmit data to and from the M512x. These pins are in high impedance state when not in the output mode. I / O Read. This active low signal is issued by the host microprocessor to indicate a read operation. I / O Write. This active low signal is issued by the host microprocessor to indicate a write operation. Address Enable. This active high signal indicates DMA operations on the host data bus. I / O Address. These bits determine the I / O address to be accessed during IORJ and IOWJ cycles. DMA Acknowledge. An active low input signal acknowledging the request for a DMA data transfer. This input enables the DMA read or write internally. DMA request. This active high output is the DMA request for byte transfers of data to the host. This signal is cleared on the last byte of the data transfer by the DACKJ signal going low. Terminal Count. This signal indicates to the M512x that data transfer is complete. TC is only accepted when DACKJ is low. TC is active high in AT mode and active low in PS / 2 mode. Interrupt Requests.
Name Number HOST Processor Interface SD0-SD7 70-72
IORJ IOWJ AEN SA0-SA15 DACK0JDACK3J DRQ0DRQ3 TC
IRQ1, IRQ3-12, IRQ14-15 MR
Floppy Disk Interface RDATAJ 17 WGATEJ 12
WDATAJ
HDSELJ DIRJ
STEPJ DSKCHGJ
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M512x : Mega I / O Controller with PnP
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07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
M512x : Mega I / O Controller with PnP
-Preliminary, Confidential, Proprietary-
07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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M512x : Mega I / O Controller with PnP
Table 2-1 M512x Pin Description Table (continued) Name Number Type Description Printer Port Interface AUTOFDJ 143 O Autofeed Output. This active low output causes the printer to automatically feed one line after each line is printed. This signal is the complement of bit 1 of the Printer Control Register. INITJ 141 O Initiate Output. This active low signal is bit 2 of the printer control register. This signal is used to initialize the printer. SLCTINJ 140 O Printer select input. This active low signal selects the printer. This is the complement of bit 3 of the Printer Control Register. STROBEJ 144 O Strobe Output. This active low pulse is used to strobe the printer data into the printer. This output signal is the complement of bit 0 of the Printer Control Register. BUSY 128 IS Busy. This signal indicates the status of the printer. A high indicates the printer is busy and not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. ACKJ 129 IS Acknowledge. This active low signal from the printer indicates it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the ACKJ input. PE 127 IS Paper End. This signal indicates that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. SLCT 126 IS Printer Selected Status. This active high signal from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. ERRORJ 142 I Error. This active low signal indicates an error condition at the printer. PD0-PD7 138-131 I / O Port Data. This bi-directional parallel data bus is used to transfer information between CPU and peripherals. IOCHRDY 90 OD IOCHRDY. In EPP mode, this pin is pulled low to extend the read / write command. Real-Time Clock XTAL1 122 ICLK 32Khz Crystal Input. XTAL2 124 OCLK 32Khz Crystal Output. VBAT 121 P Battery Voltage. PWG 120 IS Power Good Input. Keyboard Controller KDAT 91 I / O Keyboard Data. KCLK 92 I / O Keyboard Clock. MDAT 93 I / O Mouse Data. MCLK 94 I / O Mouse Clock.
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Acer Laboratories Inc.
M512x : Mega I / O Controller with PnP
-Preliminary, Confidential, Proprietary-
07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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M512x : Mega I / O Controller with PnP
Table 2-1 M512x Pin Description Table (continued) Name Number Type Description Miscellaneous X24TAL1 35 ICLK Clock 1. This is an external connection for a parallel resonant 24 MHz crystal. A CMOS compatible oscillator is required if crystal is not used. X24TAL2 36 OCLK Clock 2. This is a 24 MHz crystal. If an external clock is used, this pin should not be connected. This pin should not be used to drive any other drivers. X14CLKI 22 I Clock 14 In. This is a 14.318 MHz clock source in. XCLKO1 37 O Clock 14 out. This is a 14.318 MHz clock out. XCLKO2 38 O Clock 14 out. This is the second 14.318 MHz clock out. Power Pins Vcc 21, 60, 101, P Power. +5 Volt supply pin. 125, 139 Vss 1, 8, 40, 71, 95, P Ground pins. 123, 130
Type Description : I IS ICLK OCLK O4 OD24 Input TTL compatible. Input with Schmitt Trigger. CLK input. CLK output. Output with 4 mA sink @ 0.4 V, source 4 mA @ 2.4 V. Open drain outputs, sinks 24 mA @ 0.4 V.
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Acer Laboratories Inc.
M512x : Mega I / O Controller with PnP
-Preliminary, Confidential, Proprietary-
07-02-1997 Document Number: 512xDS02.doc Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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M512x : Mega I / O Controller with PnP
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
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M512x : Mega I / O Controller with PnP
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Pin No. 3 5 6 18 147 157 150 160 142 13 14 141 90 68 69 67 66 65 64 63 62 61 59 58 57 56 55 54 91 92 94 93 19 20 4 7 80 138 137 136
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M512x : Mega I / O Controller with PnP
Pin No. 73 74 75 76 77 78 79 145 155 140 126 146 156 10 144 89 15 121 21 60 101 125 139 1 8 40 71 95 123 130 11 16 12 22 35 36 122 124 37 38
Pin Name SD1 SD2 SD3 SD4 SD5 SD6 SD7 SIN1 SIN2 SLCTINJ SLCT SOUT1 SOUT2 STEPJ STROBJ TC TRK0J VBAT Vcc Vcc Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss WDATAJ WPROTJ WGATEJ X14CLKI X24TAL1 X24TAL2 X32TAL1 X32TAL2 XCLKO1 XCLKO2
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M512x : Mega I / O Controller with PnP
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Section 3 : Configuration Description and Power Management Features
3.1 Configuration Port
CHIP LEVEL REGISTERS Index name Index 0x02h Bit 0 Hard reset, Soft reset default values 0x00, 0x00 1 : Soft reset the configuration registers. This bit is automatically cleared after write. This register is write only.
Index 0x03h Bit 1-0
0x03, N / A Set CIO1, CIO2, and CIO3 selection register address. 00 : 0xE0 01 : 0xE2 10 : 0xE4 11 : 0xEA 0 : Disable access 1 : Enable access to CIO1, CIO2, and CIO3.
Index 0x07h Bit 3-0
Bit 7-4
0x23, 0x23 ALi defined Read only.
device
identification.
Index 0x21h
0x51, 0x51 ALi defined Read only.
device
identification.
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M512x : Mega I / O Controller with PnP
Index 0x22h Bit 0
0x00, 0x00 Direct powerdown FDC (Note 3) 0 : disable 1 : enable read as 0. Direct powerdown Parallel Port (Note 3) 0 : disable 1 : enable Direct powerdown UART1 (Note 3) 0 : disable 1 : enable Direct powerdown UART2 (Note 3) 0 : disable 1 : enable 1: Turn off the oscillator. read as 0.
Index 0x2Dh
Reserved for test purposes only
Bit 2-1 Bit 3
LOGICAL DEVICE 0 REGISTERS (FDC) Index 0x30h Bit 0 0x00, 0x00 FDC (Note 4) 0 : disable 1 : enable read as 0.
Bit 7-1
Index 0x60h
Bit 7-2
Index 0x23h Bit 2-0 Bit 3
0x00, N / A read as 0. Auto powerdown Parallel Port. 0 : disable 1 : enable Auto powerdown UART1. 0 : disable 1 : enable Auto powerdown UART2. 0 : disable 1 : enable read as 0
Index 0x61h
Bit 2-0
Bit 7-6
Index 0x24h Bit 5-0 Bit 6
0x00, N / A read as 0. 0 : pin26 functions as PDIR 1 : pin26 functions as SDRV. 0 : IRQ8 is active high 1 : IRQ8 is active low.(Note 1)
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M512x : Mega I / O Controller with PnP
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Index 0x70h Bit 3-0
0x06, 0x06 Select IRQ channel used by FDC. 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15 read as 0.
Index 0xF1h Bit 1-0
0x00, N / A External Floppy Select. 0x : internal FDC 10 : external FDC 11 : Drive A internal, Drive B external Density Select. 0x : Normal 10 : force to 1 11 : force to 0 Media ID1-0 polarity. 0 : normal 1 : inverted Boot Floppy. 00 : FDD 0 01 : FDD 1 10 : FDD 2 11 : FDD 3
Bit 3-2
Bit 5-4
Bit 7-6
Bit 7-4
Index 0x74h Bit 2-0
0x02, 0x02 Select DMA channel used by FDC 000 : DMA0 001 : DMA1 010 : DMA2 011 : DMA3 100 : None read as 0.
Index 0xF2h Bit 1-0 Bit 3-2 Bit 5-4 Bit 7-6
0xFF, N / A Floppy Drive A type. Floppy Drive B type. Floppy Drive C type. Floppy Drive D type.
Bit 7-3
Index 0xF4h Index 0xF0h Bit 0 0x08, N / A Bit 1-0 0 : Normal mode 1 : Enhanced OS2 mode Bit 2, 7-5 Bit 1 0 : Burst DMA mode. 1 : Non-burst DMA mode read as 0. 0 : PS2 mode 1 : AT mode 0 : No swap. 1 : Swap Drive 0 and Drive 1 Bit 4-3
0x00, N / A DRVDEN1-0 signal definition (refer to Table 3-4). read as 0. Data Rate Table Select (refer to Table 3-3).
Bit 2, 7-5 Bit 3
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M512x : Mega I / O Controller with PnP
Bit 7-1 Index 0x60h
Bit 1-0
Note : An 8-byte boundary is required if EPP is available Index 0x70h Bit 3-0 0x05, 0x05 Select IRQ channel used by Parallel Port. 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15 read as 0. 0x04, 0x04 Select DMA channel used by Parallel Port. 000 : DMA0 001 : DMA1 010 : DMA2 011 : DMA3 100 : None read as 0.
Bit 7-3
Bit 7-4 Index 0x74h Bit 2-0
Bit 7-3
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M512x : Mega I / O Controller with PnP
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LOGICAL DEVICE 4 REGISTERS (UART1) Index 0x30h Bit 0 0x00, 0x00 UART1 (Note 4) 0 : disable 1 : enable read as 0. Index 0xF0h Bit 0 0x00, N / A MIDI support 0 : disable 1 : enable High speed mode 0 : disable 1 : enable 0 : Normal 1 : 8Mhz clock source for UART1 read as 0. 0x00, N / A IR receive polarity. 0 : active high 1 : active low IR transmit polarity. 0 : active high 1 : active low 0 : Full duplex in IR 1 : Half duplex in IR IR mode. 00 : Normal 01 : IrDA 10 : ASK IR 11 : Normal read as 0. 0x0C, N / A Baud Rate output on RI1. 0 : disable 1 : enable IR half-duplex Tx-to-Rx time- out timer. 0 : disable 1 : enable IR half-duplex Rx-to-Tx time-out timer. 0 : disable 1 : enable IR half-duplex time-out time control. 00: 41-bit time for TR, 39-bit time for RX. 01: 42-bit time for TR, 39-bit time for RX 1x: 40-bit time for TR and RX read as 0.
Bit 7-1
Index 0x60h
Bit 7-2
Bit 7-3 Index 0xF1h
Index 0x61h
Bit 2-0
Bit 1 Index 0x70h Bit 3-0 0x04, 0x04 Bit 2 Select IRQ used by UART1. 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15 read as 0. Bit 4-3 Bit 4-3
Bit 7-5 Index 0xF2h Bit 0
Bit 2 Bit 7-4
Bit 7-5
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M512x : Mega I / O Controller with PnP
LOGICAL DEVICE 5 REGISTERS (UART2) Index 0x30h Bit 0 0x00, 0x00 UART2 (Note 4) 0 : disable 1 : enable read as 0. Index 0xF0h Bit 0 0x00, N / A MIDI support 0 : disable 1 : enable High speed mode 0 : disable 1 : enable 1 : 8 Mhz clock source for UART2 0 : Normal read as 0.
Bit 7-1
Index 0x60h
Bit 7-2
Index 0xF1h Bit 0
0x02, N / A IR receive polarity. 0 : active high 1 : active low IR transmit polarity. 0: active high 1: active low 1 : Half duplex in IR 0 : Full duplex in IR. IR mode. 00 : Normal 01 : IrDA 10 : ASK IR 11 : Normal read as 0. IR input source. 0 : use TX2 and RX2 1 : use IRRX2 and IRTX2
Bit 2-0
Index 0x70h Bit 3-0
0x03, 0x03 Select IRQ channel used by UART2. 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15 read as 0. Bit 1
Bit 4-3
Bit 7-4
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M512x : Mega I / O Controller with PnP
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Index 0xF2h Bit 0
0x0C, N / A Baud Rate output on RI2 0 : disable 1 : enable IR half-duplex Tx-to-Rx time-out timer. 0 : disable 1 : enable
LOGICAL DEVICE 7 REGISTERS (KEYBOARD) Index 0x30h Bit 0 0x00, 0x00 Keyboard controller. This is a hardware setting bit by RTS2J. (Note 4) 0 : disable 1 : enable read as 0.
Bit 7-1 Bit 2 IR half-duplex Rx-to-Tx time-out timer 0 : disable 1 : enable IR half-duplex time-out time control. 1x : 40-bit time for TR and RX 01 : 42-bit time for TR, 39-bit time for RX 00 : 41-bit time for TR, 39-bit time for RX. read as 0.
Index 0x70h Bit 3-0
0x01, 0x01 Select IRQ channel used by Keyboard. 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15 read as 0. 0x00, 0x00 Select IRQ channel used by PS / 2 Mouse. 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15 read as 0.
Bit 4-3
Bit 7-5
LOGICAL DEVICE 6 REGISTERS (RTC) Index 0x30h Bit 0 0x00, 0x00 0 : Deactivate RTC (Note 4) 1 : Activate RTC. This is a hardware setting bit by DTR1J. read as 0. Bit 7-4 Index 0xF0h Bit 0 0x00, N / A Index 0x72h CMOS RAM 0x80-0x9F 0 : Unlock 1 : Lock CMOS RAM 0xA0-0xBF. 0 : Unlock 1 : Lock CMOS RAM 0xC0-0xDF 0 : Unlock 1 : Lock CMOS RAM 0xE0-0xFF. 0 : Unlock 1 : Lock read as 0. 1: Select upper 128-byte bank of RAM 0: Select lower bank Bit 3-0
Bit 7-1
Bit 6-4 Bit 7
Bit 7-4
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M512x : Mega I / O Controller with PnP
Index 0xF0h Bit 0
0x00, 0x00 0 : KBC clock source is 8Mhz 1 : KBC clock source is 7.16Mhz. Read only. Indicates the type of keyboard 0 : PS2. 1 : AT read as 0.
Index 0xE1h
0x01, N / A CIO11 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted 1 : inverted read as 0. 0 : Normal function. 1 : Input function as IRQIN2 IRQ mapping for IRQIN2 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15
Bit 7-2
Bit 2 LOGICAL DEVICE 8 REGISTERS (Common I / O) Index 0x30h Bit 0 0x00, 0x00 Bit 7-4 Common I / O port. 0 : disable 1 : enable read as 0. Bit 3
Bit 7-1
Index 0xE0h
0x01, N / A CIO10 function definition 1 : input 0 : output Input / Output signal polarity 0 : non-inverted 1 : inverted read as 0. Index 0xE2h 0 : Normal function. 1 : Input function as IRQIN1 Bit 0 IRQ mapping for IRQIN1. 0000 : None 0001 : IRQ1 0010 : N / A 0011 : IRQ3 0100 : IRQ4 0101 : IRQ5 0110 : IRQ6 0111 : IRQ7 1000 : N / A 1001 : IRQ9 1010 : IRQ10 1011 : IRQ11 1100 : IRQ12 1101 : N / A 1110 : IRQ14 1111 : IRQ15
0x01, N / A CIO12 function definition. 0 : output 1 : input Input / Output signal polarity 0 : non-inverted 1 : inverted read as 0. 0 : Normal function 1 : Input function as IRRX2 read as 0.
Bit 7-4
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Index 0xE3h
0x01, N / A CIO13 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0. 0 : Normal function. 1 : Output function as IRTX2
Index 0xE6h
0x01, N / A CIO16 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0. 0 : Normal function 1 : Output function as I2C CLK (Note2).
Bit 2, 7-4 Bit 3
Index 0xE4h
0x01, N / A CIO14 function definition. 0 : output 1 : input Input / Output signal polarity 0 : non-inverted. 1 : inverted read as 0. 0 : Normal function. 1 : Select KBC P21 function 0x01, N / A CIO15 function definition. 0 : output. 1 : input Input / Output signal polarity. 0 : non-inverted 1 : inverted read as 0.
Index 0xE7h
0x01, N / A CIO17 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted 1 : inverted read as 0 0 : Normal function. 1 : Select I2C DAT function (Note2).
Bit 2, 7-4 Bit 3
Index 0xE5h
Index 0xE8
0x01, N / A CIO20 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0.
Bit 2, 7-4 Bit 3
Bit 7-2 0 : Normal function 1 : Select KBC P20 function
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Index 0xE9h
0x01, N / A CIO21 function definition. 0 : output. 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0.
Index 0xEDh
0x01, N / A CIO25 function definition. 0 : output 1 : input. Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0. 0 : Normal function. 1 : Select KEYLOCK function
Bit 7-2
Bit 2, 7-4 Bit 3
Index 0xEAh
0x01, N / A CIO22 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted. read as 0. Index 0xEEh Bit 5-0
Bit 7-6
Bit 7-2
Index 0xEBh
0x01, N / A CIO23 function definition. 0 : output 1 : input. Input / Output signal polarity. 0 : non-inverted 1 : inverted. read as 0
Index 0xEFh Bit 3-0 Bit 7-4
0x00, N / A read as 0. Address line7-4 of CS0J.
Index 0xF5h
0x01, N / A CIO30 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted 1 : inverted. read as 0. 0 : Normal. 1 : Input function as the new KBC clock source
Bit 7-2
Bit 0 Index 0xECh 0x01, N / A CIO24 function definition 0 : output 1 : input Bit 2, 7-4 Bit 1 Input / Output signal polarity 0 : non-inverted 1 : inverted. read as 0. Bit 3
Bit 7-2
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Index 0xF6h
0x01, N / A CIO31 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0. 0 : Normal function. 1 : Output function as CS0J 0x01, N / A CIO32 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted 1 : inverted read as 0.
Index 0xFAh
0x01, N / A CIO35 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0
Bit 2, 7-4 Bit 3
Bit 7-2
Index 0xFBh
0x01, N / A CIO36 function definition 0 : output 1 : input Input / Output signal polarity 0 : non-inverted 1 : inverted read as 0
Index 0xF7h
Bit 7-2
Bit 2, 7-4 Bit 3
Index 0xFCh 0 : Normal function. 1 : Output function as CS1J Bit 0 Index 0xF8h Bit 0 0x01, N / A CIO33 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted. 1 : inverted read as 0.
Bit 2, 7-4 Bit 3
Bit 7-2
Index 0xF9h
0x01, N / A CIO34 function definition. 0 : output 1 : input Input / Output signal polarity. 0 : non-inverted 1 : inverted read as 0.
Bit 7-2
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Index 0xFDh Bit 5-0 Bit 7-6
Bit 3 Index 0xFEh Bit 3-0 Bit 7-4
Index 0xFFh Bit 0
0x00, N / A CS0J assertion on write cycle. 0 : disable 1 : enable
Table 3-2 Pin Name RTS1J 0 1 RTS2J 0 1 DTR1J 0 1 DTR2J 0 1 Table 3-3
Table 3-4
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Drvden Output Mapping for Drive Type Table
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M512x : Mega I / O Controller with PnP 0xF4 1:0 DT1 0 1 0 1 DT0 0 0 1 1 Drvden Signal Definition DRVDEN1 DRATE0 DRATE0 DRATE0 DRATE1 DRVDEN0 DENSEL DRATE1 nDENSEL DRATE0
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3.2.2.1 Powerdown Modes of FDC
The rest of the chip is powered down in two ways: direct powerdown and automatic powerdown. Direct powerdown results in immediate shutdown of the part without regard to the current state of the part. Automatic powerdown results when certain conditions become true within the part. A. Direct Powerdown
3.2 Power Management Features
The M512x contains power management features that makes it ideal for design of notebook and desktop personal computers. These features can be classified into power management of the part and the internal oscillator. The powerdown of the part is done independently of the internal oscillator in the M512x.
3.2.1 Oscillator Power Management
The M512x supports a built-in crystal oscillator that can be programmed to be either powered down or active, independent of the power state of the chip. This capability is implemented by the OSC-OFF bit in the 0x22. When OSCOFF is set high, the internal oscillator is off. When the external oscillator is used, power can be saved by turning off the internal oscillator. If the internal oscillator is used, the oscillator may be powered up (even when the rest of the chip is powered off) allowing the chip to wake up quickly and be in a stable state. It is recommended to keep the internal oscillator on even at the powerdown state. The main reason for this is that the recovery time of the oscillator during wake-up may take tens of milli-seconds under the worst case, which may create problems with any sensitive application software. In a typical application, the internal oscillator should be on unless the system goes into a power saving or standby mode. Such a mode request would be made by a system time-out or by a user. In this case, the system software would take over and must turn on the oscillator sufficiently ahead of awakening the part. In the case of the external oscillators, the power-up characteristics are similar. If the external source remains active during the time the M512x is powered down, then the recovery time effect is minimized.
3.2.2 Part Power Management
This section deals with the power management of the rest of the chip excluding the oscillator. This part shows how powerdown modes and wake up modes are activated.
The command can be used to enable powerdown by setting the AUTOPD bit in the command to high. The command also provides a capability of programming a minimum power-up time via the MIN DLY bit in the command. The minimum power-up time refers to a minimum amount of time the part will remain powered-up after being awakened or reset. An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down provided all the remaining conditions are met. Any software reset will reinitialize the timer. Changing of data rate extends the auto powerdown timer by up to 10 ms, but only if the data rate is changed during the countdown. Disabling the auto powerdown mode cancels the timers and holds the M512x out of auto powerdown.
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3.2.2.2 Powerdown Mode of UART and Printer
UART1, UART2 and printer can enter direct powerdown or auto powerdown respectively by setting their relative powerdown bit in the 0X22 and 0x23. If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened by a software reset, the auto powerdown command (including the minimum delay timer) will again become effective as previously programmed. If the part is awakened via a hardware reset, the auto powerdown is disabled. After reset, the part will go through a normal sequence. The drive status will be initialized. The FIFO mode will be set to default mode on a hardware reset or on a software reset if the LOCK command is not blocking it. Finally, after a delay, the polling interrupt will be issued. B. Wake Up from Auto Powerdown
3.2.2.3 WAKE UP MODES of FDC
This section describes the conditions for awakening the part from both direct and automatic powerdown. Power conservation of battery life is the main reason power management is required. This means that the M512x must be kept in powerdown state as long as possible and should be powered up as late as possible without compromising software transparency. To keep the part in powerdown mode as late as possible implies that the part should wake-up as fast as possible. However, some amount of time is required for the part to exit powerdown state and prepare the internal microcontroller to accept commands. Application software is very sensitive to such a delay and in order to maintain software transparency, the recovery time of the wake-up process must be carefully controlled by the system software. A. Wake Up from DSR Powerdown
If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. If a hardware or software reset is used, then the part goes through the normal reset sequence. If the access is through the selected registers, then the M512x resumes operation as though it was never in powerdown. Besides activating the RESET pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake-up the part: 1. 2. 3. Enabling any one of the motor enable bits in the DOR register (reading the DOR does not wake-up the part) A read from the MSR register A read or write to the FIFO register
Any of these actions will wake-up the part. Once awake, M512x will initiate the auto powerdown time for 10 ms or 0.5 sec. (Depending on the MIN DLY bit the auto powerdown command). The part will powerdown again when all the powerdown conditions stated in the Auto Powerdown section are satisfied.
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Section 4 : Floppy Disk Controller
4.1 Register Overview
The integrated FDC of the M512x part is register- and hardware-level compatible with the industry standard 765A and 82077SL standards. Table 4-1 lists the I / O address Table 4-1 A2 0 0 0 0 1 1 1 1 1 1 A1 0 0 1 1 0 0 0 1 1 1 FDC Controller I / O Address Map A0 0 1 0 1 0 0 1 0 1 1 R / W R R R / W R / W R W R / W R W Register SRA (PS / 2 mode only) SRB (PS / 2 mode only) Digital Output Register DOR Tape Drive Register TDR Main Status Register MSR Data Rate Select Register DSR Data (First In First Out) FIFO reserved Digital Input Register DIR Configuration Control Register CCR map of the FDC controller. Table 4-2 is the summary of FDC register hardware reset.
When this location is accessed, only bit 7 is driving, all other bits are held tristate. Table 4-2
Register DOR(R / W) TDR(R / W) MSR(R) DSR(W) DIR(R) CCR(W) SRA(R) SRB(R)
Summary of FDC Register Hardware Reset and Powerdown State
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4.2 Register Description 4.2.2 Status Register B (SRB)
This section describes the register bits for all the registers that are directly accessible to the CPU. Address 3F1 Read only This register is read-only and monitors the state of several disk interface pins, in PS / 2 modes. The SRB can be accessed at any time during PS / 2 mode. In AT mode, the data bus pins D0-D7 are held in a high impedance state for a read of address 3F1h. PS / 2 mode Bit 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Name 1 1 Drive Sel0 Wdata Toggle Rdata Toggle Wgate MOTEN1 MOTEN0 Reserved : Always read as a logic "1" Reserved : Always read as a logic "1" Drive Select 0 : Reflects the status of the Drive Select bit 0 of DOR (address 3F2 bit 0). This bit is cleared after a hardware reset, it is unaffected by a software reset Write Data Toggle : This bit changes Read Data Toggle : Every inactive edge of the RDATA input causes this bit to change state. state at every inactive edge of the WDATA Write Gate : The WGATE disk interface output (active high) Motor Enable 1 : The MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Motor Enable 0 : The MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.
4.2.1 Status Register A (SRA)
Address 3F0 Read only This register is read-only and monitors the state of the IRQ6 pin and several disk interface pins in PS / 2 modes. The SRA can be accessed any time when it is in PS / 2 mode. In AT mode, the data bus pins D0-D7 are held in a high impedance state for a read of address 3F0h. PS / 2 mode Bit 7 6 5 4 3 2 1 0 Bit 7 Name Int Pending DRV2J STEP TRK0J HDSEL INDXJ WPJ DIR Interrupt Pending : The state of the Floppy Disk Interrupt output (active high). DRV2J : DRV2 disk interface input pin, indicates that a second drive has been installed. Step : Step output disk interface output pin (active high) Track 0 : TRK0 disk interface input (active low)
Bit 2 Bit 3 Head Select : HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. Index : Index disk interface input (active low) Write Protect : Write protect disk interface input. A logic "0" indicates that the disk is write protected. Direction : Head movement direction (active high). A logic "1" indicates inward direction a logic "0" outward. Bit 0
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4.2.3 Digital Output Register (R / W)
D6 D5 D4 D3 D2 D1~D0
Internal 4 Drive Decode - Drives 0 and 1 Swapped Digital Output Register D6 D5 D4 D1 x x 1 0 x 1 x 0 1 x x 1 x x x 1 0 0 0 x D0 0 1 0 1 x Drive Select Outputs DS1J DS0J 0 1 1 0 1 1 1 1 1 1 Motor on Outputs MTR1J MTR0J / D4 / D5 / D4 / D5 / D4 / D5 / D4 / D5 / D4 / D5
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4.2.4 Tape Drive Register (TDR) Address 3F3 R / W This register is included for 82077 software compatibility. The robust data separator used in the M512x does not require its characteristics modified for tape support. The contents of this register are not used internally to the device. The TDR is unaffected by a software reset. Bits 2-7 are tri-stated when read in this mode.
Normal Floppy mode Normal mode. Register 3F3h contains only bits 0 and 1. When this register is read, bits 2- 7 are at high impedance. DB7 Tri-state DB6 Tristate DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tristate DB1 tapesel1 DB0 tapesel0
REG 3F3
Enhanced Floppy mode 2 (OS2) Register 3F3 for Enhanced Floppy mode 2 operation DB7 Media ID1 DB6 Media ID0 DB5 DB4 Drive type ID DB3 DB2 Floppy boot drive DB1 tapesel1 DB0 tapesel0
REG 3F3
For this mode, DRATE0 and DRATE1 pins are inputs and these inputs are gated into bits 6 and 7 of the 3F3 register. These two bits are not affected by any reset. Bit 7 Media ID 1 Read only (pin 19) see table next page Bit 6 Media ID 0 Read only (pin 20) see table next page Bits 5 and 4 Drive Type ID - These bits reflect two of FDC 0XF2 configuration register bits. (please see next page). Bits 3 and 2 Floppy boot Drive. These bits show the value of FDC 0xF1 configuration register bits. Bits 1 and 0 - Tape Drive select (R / W). Same as in Normal and Enhanced Floppy mode 1.
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Media ID1 Drate1 pin 19 0 1
Media ID0 Drate0 pin 20 0 1
Drive type ID Digital Output Register bit 1 bit 0 0 0 0 1 1 1 0 1
Register 3F3 - drive type ID bit 5 bit 4 FDC FDC 0xF2 - bit 1 0xF2 - bit 0 FDC FDC 0xF2 - bit 3 0xF2 - bit 2 FDC FDC 0xF2 - bit 5 0xF2 - bit 4 FDC FDC 0xF2 - bit 7 0xF2 - bit 6
4.2.5 Main Status Register
Address 3F4h Read only
The read-only main status register indicates the current status of the disk controller. It is always available to be read. One of its functions is to control the flow of data to and from the data register. It also indicates when the disk controller is ready to send or receive data. It should be read before each byte is transferred to or from the data register except during a DMA transfer. No delay is required when reading this register after a data transfer.
Table 4-8 Bit D7
Main Status Register Description Description Request for Master: Indicates that the data register is ready to send or receive data from the CPU. This bit is cleared immediately after a byte transfer, and is set again as soon as the M512x is ready for the next byte. Data Direction: Indicates whether the controller is expecting a byte to be written to (0) or read from (1) the data register. Non-DMA Execution: Bit is set only during the execution phase of a command if it is in the non-DMA mode. In other words, if this bit is set, the multiple byte data transfer (in the execution phase) must be monitored by the CPU either through interrupts, or software polling as described in the processor software interface section. Command in Progress: Bit is set after the first byte of the command phase is written. Bit is cleared after the last byte of the result phase is read. If there is no result phase in a command, the bit is cleared after the last byte of the command phase is written. Drives 3~0 Seeking: Set after the last byte of the command phase of a seek or recalibrate command is issued for drives 3~0, respectively. Cleared after reading the first byte in the result phase of the sense interrupt command for this drive.
D3~D0
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4.2.6 Data Rate Select Register (DSR)
Address 3F4 Table 4-9 Bit D7 D6 Write only Datarate Select Register Description Description S / W RESET behaves the same as DOR RESET except that this reset is self clearing. POWERDOWN bit implements direct powerdown. Setting this bit high puts the FDC into the powerdown state regardless of the state of the part. The part is reset internally and then goes into powerdown. No status is saved and any operation in progress is aborted. This powerdown mode does not turn off the internal oscillator. Any hardware or software reset will exit the M512x from this powerdown state. reserved PRECOMP 0-2 adjusts the WRDATA output to the and disk to compensate for magnetic media phenomena known as bit shifting. The data patterns that are susceptible to bit shifting are well understood and the M512x offsets the data pattern as it is written to the disk. The amount of precompensation depends upon the drive and media but in most cases the default value is acceptable. The M512x starts precompensating the data pattern starting on Track 0. The CONFIGURE command can change the starting track for precompensation. Table 4-10 lists the precompensation values that can be selected and Table 4-11 lists the default precompensation values. The default value is selected if the three bits are zeros. DRATE 0-1 select one of the four data rates as listed in Table 4-12. The default value is 250 Kbps upon a chip ("Hardware") reset. Other ("Software") Resets do not affect the DRATE or PRECOMP bits.
D5 D4~D2
D1~D0
Table 4-10 PRECOMP
Precompensation Delay Values Precompensation Delay-
432 bits
DISABLED
0.00ns 41.67ns 83.34ns 125.00ns 166.67ns 208.33ns 250.00ns DEFAULT
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Table 4-11 Data Rate 1 Mbps 500 Kbps 300 Kbps 250 Kbps
Default Precompensation Delay Values Precompensation Delay 41.67ns 125ns 125ns 125ns
Table 4-12 DRATESEL 1 0 0 1 1 0 1 0
Data Rates Data Rate MFM 1 Mbps 500 Kbps 300 Kbps 250 Kbps FM Illegal 250 Kbps 150 Kbps 125 Kbps
4.2.7 Data Register (R / W)
Address 3F5 R / W
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At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the M512x enters the command execution phase, it clears the FIFO of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC.
4.2.8 Configuration Control Register (CCR, PC-AT Modes)
Address 3F7 Write only
Table 4-14 Configuration Control Register Description Bit D7~D2 D1, D0 Description Not used. Data Rate Select: These bits set the datarate and write-precompensation values for the disk controller. After a hardware reset, these bits are set to 1, 0 (250 Kbps). (please refer to table 4-12)
4.2.9 Digital Input Register (DIR, Read)
Address 3F7 Read only
Table 4-15 Digital Input Register Description (PC / AT mode) Bit D7 Description DSKCHG monitors the pin of the same name and reflects the opposite value seen on the disk cable, regardless of the value of / INVERT / . The DSKCHG bit is forced inactive along with all the inputs from the floppy disk drive. All the other bits remain tri-stated. These bits are reserved for use by the hard disk controller, thus during a read of this register, these bits are in high impedance state. Digital Input Register (PS / 2 mode)
D6~D0
Table 4-15b Bit D7
D6~D3 D2~D1
Description DSKCHG monitors the pin of the same name and reflects the opposite value seen on the disk cable. undefined, always read as logic "1". Data rate select. These bits control the data rate of the floppy controller. These bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. High density. This bit is low whenever the 500 kbps or 1 Mbps data rates are selected, and high when 250 kbps and 300 kbps are selected.
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4.3 Result Phase Status Registers
The result phase of a command contains bytes that hold status information. The format of these bytes are described in the following sections. Do not confuse these register bytes with the main status register which is a read-only register that is always available. The result phase status registers are read from the data register only during the result phase.
4.3.1 Status Register 0 (ST0)
D5 D4 D3 D2 D1, D0
4.3.2 Status Register 1 (ST1)
Table 4-17 Bit D7 Status Register 1 Description Description End of Track: This bit is set when the controller has transferred the last byte of the last sector without the TC pin becoming active. The last sector is the end-of-track sector number programmed in the command phase. Not Used: 0 CRC Error: If this bit is set and bit 5 of ST2 is clear, then there was a CRC error in the address field of the correct sector. If bit 5 of ST2 is set, then there was a CRC error in the data field. Over Run: This bit is set when the controller was not serviced by the CPU soon enough during a data transfer in the execution phase. Table 4-18 shows the time values. No Data: This bit is set for any three possible problems: 1. Controller cannot find the sector specified in the command phase during the execution of a read, write, or scan command. An address mark was found even if it is not a blank disk. 2. Controller cannot read any address fields without a CRC error during read ID command. 3. Controller cannot find the starting sector during execution of read a track command. Not Writable: Set if the write protect pin is active when a write or format command is issued. Missing Address Mark: If this bit is set and bit 0 of ST2 is clear then the disk controller cannot detect any address field address mark after two disk revolutions. If bit 0 of ST2 is set, then the disk controller cannot detect the data field address mark.
D6, D3 D5 D4 D2
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Table 4-18
Maximum Time Allowed to Service an Interrupt or Acknowledge a DMA Request in Execution Phase Data Rate 125 250 500 125 Time to Service 62.0 us 30.0 us 14.0 us 6.0 us
4.3.3 Status Register 2 (ST2)
Table 4-19 Bit D7 D6 Status Register 2 Description Description Not Used: 0 Control Mark: This bit is set if the controller tries to read a sector which contained a deleted data address mark during execution of read-data or scan commands. Or, if a read-deleted-data command was executed, a regular address mark is detected. CRC Error in Data Field: This bit is set if the controller detects a CRC error in the data field. Bit 5 of ST1 is also set. Wrong Track: This bit is only set if the desired sector is not found, and the track number recorded on any sector of the current track is different from that stored in the track register. Scan Equal Hit: This bit is only set if the equal condition is satisfied during any scan command. Scan Not Satisfied: This bit is set if the controller cannot find a sector on the track number recorded on any sector on the track which meets the desired condition during scan commands. Bad Track: This bit is only set if the desired sector is not found, and the track number recorded on any sector on the track is different from that stored in the track register and the recorded track number is FF. Missing Address Mark in Data Field: This bit is set if the controller cannot find the data field address mark during read / scan command. Bit 0 of ST1 is also set.
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4.3.4 Status Register 3 (ST3)
Table 4-20 Bit D7 D6 D5 D4 D3 D2 D1, D0 Status Register 3 Description Description Not Used: 0 Write Protect Status: This bit is the complement of the associated FDC interface pin for the drive selected in DCR. Not Used: 1 Track 0 Status: This bit is the complement of the associated FDC interface pin for the drive selected in the DCR. Not Used: 0 Head Select Status: command phase. This bit shows the status of the associated bit in the sense-drive-status
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4.4 Controller Functional Description 4.4.1 Controller Phases
The FDC handles commands in three phases- command, execution and result. Each phase is described below.
4.4.1.2.2 Interrupt Mode
If the non-DMA mode is selected, an interrupt is generated in the execution phase when each byte is ready to be transferred. The Main Status Register should be read to verify that the interrupt is for a data transfer. Bits 5 and 7 of the Main Status Register is set. The interrupt is cleared when the byte is transferred to or from the data register. The CPU should transfer the byte within the allotted time. If the byte is not transferred within the time allotted, an overrun error is indicated in the result phase when the command terminates at the end of the current sector. An interrupt is also generated after the last byte is transferred. This indicates the beginning of the Result Phase.
4.4.1.1 Command Phase
The CPU writes a series of bytes to the data register. These bytes indicate the command desired and the particular parameters required for the command. All the bytes must be written in the order specified in the command description table. The execution phase starts immediately after the last byte in the command phase is written. The Main Status Register controls the flow of command bytes, and must be polled by the software before writing each Command Phase byte to the Data Register. Prior to writing a command byte, the bit 7 must be set and bit 6 must be cleared in the MSR. After the first command byte is written to the Data Register, the bit 4 in MSR is also set and remain set until the last Result Phase byte is read. If there is no Result Phase, it is cleared after the last command byte is written. A new command may be initiated after reading all the result bytes from the previous command.
4.4.1.2.3 Software Polling
If the non-DMA mode is selected and interrupts are not suitable, the CPU can poll the Main Status Register during the execution phase to determine when a byte is ready to be transferred. The bit 7 of the Main Status Register reflects the state of the interrupt pin. Otherwise, the data transfer is similar to the interrupt mode described above.
4.4.1.2 Execution Phase
The disk controller performs the desired command. Some commands require the CPU to read or write data to or from the data register during this phase. Some commands such as Seek control the read / write head movement on the disk drive. Some commands does not involve any action by the uP or disk drive, and consists of an internal operation by the controller. If there is data to be transferred between the uP and the controller, there are three methods that can be used, DMA mode, interrupt mode, and software polling mode. All of these data transfer modes work with the FIFO enabled or disabled.
4.4.1.3 Result Phase
During the Result Phase, the uP reads a series of bytes from the data register. These bytes indicate the status of the command. This status may indicate whether the command executed properly, or contain some control information. The bit 7 and bit 6 in the MSR must both be set before each result byte can be read. After the last result byte is read, the bit 4 in the MSR is cleared, and the controller is ready for the next command.
4.4.1.2.1 DMA Mode
If the DMA mode is selected, a DMA request is generated in the execution phase when each byte is ready to be transferred. To enable DMA operations during the execution phase, the DMA mode bit in the Specify command must be enabled, and the DMA signals must be enabled in the Drive Control Register. The DMA controller responds to the DMA request with a DMA-acknowledge and a read- or writestrobe. The DMA request is cleared by the active edge of the DMA-acknowledge. After the last byte is transferred, an interrupt is generated, indicating the beginning of the result phase. TC is asserted to terminate an operation. Due to internal gating, TC is only recognized when the -DAK input is low.
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Table 4-21
M512x FDC Command Set
READ DATA
Command Phase MT MFM SK IPS 0 0 0 0 1 1 0 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data read from disk drive is transferred to system via DMA or Non-DMA modes. Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector
READ A TRACK
0 0 0 1 0 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data read from disk drive is transferred to system via DMA or Non-DMA modes. Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector Command Phase 0 MFM 0 IPS 0 0
READ DELETED DATA
Command Phase MT MFM SK IPS 0 0 0 1 1 0 0 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data read from disk drive is transferred to system via DMA or Non-DMA modes. Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector
READ ID
Command Phase 0 MFM 0 0 1 0 1 0 0 0 0 0 0 HD DR1 DR0 Execution Phase: Controller reads first ID Field header bytes it can find and reports these bytes to the system in the result bytes Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector
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WRITE DATA
0 0 1 0 1 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data is transferred from the system to the controller via DMA or Non-DMA modes and written to the disk. Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector Command Phase MT MFM 0 IPS 0 0
FORMAT A TRACK
0 1 1 0 1 0 0 HD DR1 DR0 Bytes per Sector Sector per Track Format Gap Data Pattern Execution Phase: System transfers four ID bytes per sector to the floppy controller via DMA or Non-DMA modes. The entire track is formatted. The data block in the Data Field of each sector is filled with the data pattern byte Result Phase Status Register 0 Status Register 1 Status Register 2 Undefined Undefined Undefined Undefined Command Phase 0 MFM 0 0 0 0
SCAN EQUAL
1 0 0 0 1 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data transfer from system to controller is compared to data read from disk Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector Command Phase MT MFM SK IPS 0 0
WRITE DELETED DATA
Command Phase MT MFM 0 IPS 0 0 0 1 0 0 1 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data is transferred from the system to the controller via DMA or Non-DMA modes and written to the disk. Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector
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SCAN HIGH OR EQUAL
Command Phase MT MFM SK IPS 0 0 1 1 1 0 1 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data transfer from system to controller is compared to data read from disk Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector
VERIFY
1 0 1 1 0 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data is read from disk but not transferred to the system. Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector Command Phase MT MFM SK 0 0 0
SCAN LOW OR EQUAL
Command Phase MT MFM SK IPS 0 0 1 0 0 0 1 0 0 HD DR1 DR0 Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Number Data Length Execution Phase: Data transfer from system to controller is compared to data read from disk Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector
DUMPREG
Command Phase 0 0 0 0 1 1 1 0 Execution Phase: Internal registers read Result Phase Present Track Number on Drive 0 Present Track Number on Drive 1 Present Track Number on Drive 2 Present Track Number on Drive 3 Step Rate Time Motor Off Time Motor On Time DMA Sector per Track / End of Track LOCK 0 D3 D2 D1 D0 GAP WG 0 EIS FIFO POLL FIFOTHR PRETRK
PERPENDICULAR MODE
Command Phase 0 0 0 1 0 0 1 OW 0 D3 D2 D1 D0 GAP Execution Phase: Internal registers are written. No Result Phase. 0 WG
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CONFIGURE
Command Phase 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 EIS FIFO POLL FIFOTHR PRETRK Execution Phase: Internal registers are written. No Result Phase 1 0
SENSE INTERRUPT
Command Phase 0 0 0 0 1 0 0 Execution Phase: Status of interrupt is reported Result Phase Status Register 0 Present Track Number 0
SPECIFY RECALIBRATE
Command Phase 0 0 0 0 0 1 1 1 0 0 0 0 0 0 DR1 DR0 Execution Phase: Disk drive head is stepped out to Track 0. No Result Phase Command Phase 0 0 0 0 0 0 1 1 Step Rate Time Motor Off Time Motor On Time DMA Execution Phase: Internal registers are written. No Result Phase
POWERDOWN MODE RELATIVE SEEK
Command Phase 1 DIR 0 0 1 1 1 1 0 0 0 0 0 HD DR1 DR0 Relative Track Number Execution Phase: Disk drive head stepped in or out a programmable number of tracks. No Result Phase Command Phase 0 0 0 1 0 1 1 0 0 0 0 0 0 DLY Execution Phase: Internal registers are written Result Phase 0 0 0 0 0 0 DLY 1 APD
VERSION
Command Phase 0 0 0 0 0 0 0 1 1 1 1 0 0 HD DR1 DR0 New Track Number Execution Phase: Disk drive head is stepped in or out to a desired track. No Result Phase
Command Phase LOCK 0 0 1 0 1 0 Execution Phase: Internal registers are written. Result Phase 0 0 0 LOCK 0 0 0 0
SENSE DRIVE STATUS
Command Phase 0 0 0 0 0 1 0 0 0 0 0 0 0 HD DR1 DR0 Execution Phase: Disk drive status information is detected and reported. Result Phase Status Register 3
INVALID
Command Phase Invalid Codes Result Phase Status Register 0 (80H)
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4.6 Command Description 4.6.1 Read Data
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4.6.2 Read-Deleted-Data
This command is the same as the read-data command except for how it handles a deleted data mark. If a deleted data mark is read, the sector is read normally. If a regular data mark is found and the SK bit is set, the sector is not read, bit 6 of ST2 (control mark) is set, and the next sector is searched for. If a regular data mark is found and the SK bit is not set, the sector is read, bit 6 of ST2 (control mark) is set, and the read terminates with a normal termination.
the disk, the sectors are still read in their physical order. If a header ID comparison fails, bit 2 of ST1 (No data) is set, but the operation continues. If there is a CRC error in the address or data field, the read also continues. The command terminates when it has read the number of sectors programmed in the EOT parameter.
4.6.6 Read ID
This command causes the controller to read the first address field it finds. The result phase contains the header bytes that are read. There is no data transfer during the execution phase of this command. An interrupt is generated when the execution phase is completed.
4.6.3 Write-Data
The write-data command is very similar to the read-data command except that data is transferred from the CPU to the disk rather than the other way around. If the controller detects the write-protect signal, bit 1 of ST1 (not writable) is set and an abnormal termination is indicated.
4.6.7 Format-a-Track
This command formats one track on the disk. After the index hole is detected, data patterns are written on the disk including all gaps, address marks, address fields, and data fields. The exact details of the number of bytes for each field is controlled by the parameters given in the format-atrack command, and the IAF (Index Address Field) bit in the mode command. The data field consists of the fill-byte specified in the command, repeated to fill the entire sector. To allow for floppy formatting, the CPU must supply the four address field bytes (track, head, sector, number of bytes) for each sector formatted during the execution phase. In other words, as the controller formats each sector, it requests four bytes through either DMA requests or interrupts. This allows for non-sequential sector interleaving. Table 4-29 shows some typical values for the programmable gap size. The format command terminates when the index hole is detected a second time, at which point an interrupt is generated. Only the first three status bytes in the result phase are significant.
4.6.4 Write-Deleted-Data
This command is the same as the write-data command except that a deleted-data mark is written at the beginning of the data field instead of the normal data mark.
4.6.5 Read a Track
This command is similar to the read-data command except for the following: the controller starts at the index hole and reads the sectors in their physical order, not their logical order. Even though the controller reads sectors in their physical order, it still compares the header ID bytes with the data programmed in the command phase. The exception to this is the sector number. Internally, this is set to one, then incremented for each successive sector read. Whether or not the programmed address field matches that read from
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Table 4-25A Gap Length for Various Sector Sizes and Disk Types Sector Size (Dec) 128 256 512 1024 2048 4096 256 512 1024 2048 4096 8192 128 128 256 512 1024 2048 256 256 512 1024 2048 4096 128 256 512 256 512 1024 Sector Sector Code EOT Gap (Dec) (Hex) (Hex) 8-inch Drives (360 RPM, 500 kb / s) 00 1A 07 01 0F 0E 02 08 1B 03 04 47 04 02 C8 05 01 C8 01 0F 0E 02 0F 1B 03 08 35 04 04 99 05 02 C8 06 01 C8 5.25-inch Drives (300 RPM, 250 kb / s) 00 12 07 00 10 10 01 08 18 02 04 46 03 02 C8 04 01 C8 01 12 0A 01 10 20 02 08 2A 03 04 80 04 02 C8 05 01 C8 3.5-inch Drives (300 RPM, 250 kb / s) 00 0F 07 01 09 0E 02 05 1B 01 0F 0E 02 09 1B 03 05 35 Format Gap (Hex) 1B 2A 3A 8A FF FF 36 54 74 FF FF FF 09 19 30 87 FF FF 0C 32 50 F0 FF FF 1B 2A 3A 36 54 74
Mode FM
Table 4-25B Format Table for PC-Compatible Diskette Media Media Type 360 K 1.2 M 720 M 1.44 M 2.88 M Sector Size (Dec) 512 512 512 512 512 Sector Code (Hex) 02 02 02 02 02 EOT (Hex) 09 0F 09 12 24 Sector Gap (Hex) 2A 1B 1B 1B 1b Format Gap (Hex) 50 54 50 6C 54
Format gap is the gap length used only for the format command.
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Index pulse Gap0 Sync IAM Gap1 Sync AM 80 of 12 of 50 of 12 of Perpendicular MFM FF 00 3 of F 4E 00 3 of F C2 C A1 E format T R A C K T R A C K
Gap2 Sync 41 of 12 of 4E 00
Gap3 Prog GAP4 ram mable
IBM format
Gap0 Sync IAM Gap1 Sync AM 80 of 12 of 50 of 12 of 4E 00 3 of F 4E 00 3 of F MFM C2 C A1 E
Gap2 Sync 22 of 12 of 4E 00
Gap3 Prog GAP4 ram mable
Index address field
Address field Repeated for each sector
Data field
ISO format
Gap1 Sync AM 32 of 12 of 4E 00 3 of F A1 E
Gap2 Sync 22 of 12 of 4E 00
Gap3 Prog GAP4 ram mabl e
Figure 4-4 IBM, Perpendicular, and ISO Formats Supported by the Format Command
4.6.8 Scan Commands
Status Register Command Scan equal Scan low or equal Scan high or equal
4.6.9 Seek
There are two ways to move the disk drive head to the desired track number. The first method is to enable the implied seek mode. This way, each individual read or write command automatically moves the head to the track specified in the command.
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The second method is by using the seek command. During the execution phase of the seek command, the track number to seek for is