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M512x Mega Controller with
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M512x Mega Controller with Plug Play
FEATURES
Supports Windows Plug Play Supports serial/1 parallel/FDC/RTC/KB PS/2 mouse functions Supports General Purpose pins Enhanced ESD/LATCH over 4KV/300 Supports SPP, PS/2, EPP, 1284 compliance Supports GPIO Alternative function pins Remote Control Supports UART1, UART2 additional pins Supports Fast Gate functions Supports enable/disable functions Single-chip Notebook/Desktop solution
Various modes Parallel Port Supports ECP/ PS/2 1284 Compliance PC/XT, PC/AT PS/2 compatible Bi-directional parallel port Enhanced Parallel Port (EPP) compatible Microsoft Hewlett Packard Extended Capabilities Port (ECP) compatible
Supports Windows Plug-and-Play Supports Serial Parallel PS/2 Mouse functions Supports General Purpose pins GPIO ports (Ports GPIO-ALT function pins Remote Control (Pins 30-34) General Purpose chip select pins (Pins 24-25) Supports Control Pins
Serial ports high performance 16550 compatible UARTs with send/receive 16-byte FIFOs Serial Infra (SIR) wireless communications MIDI (Musical Instrument Digital Interface) compatible
2.88 Floppy Disk Controller Software compatible with 82077 supports 16-byte data FIFOs High performance internal data separator Supports standard Mbps Kbps Kbps Kbps data rate Supports modes 3.5" (720K/1.2M/1.44MB) Swappable drives
High performance Power Management FDC, UART Parallel Port Supports XD-To-SD Buffer Control Pins Supports Enable/Disable Supports Fast Gate function Supports External programming functions Supports additional IrDA Pins Supports Phoenix (M5123), KBC(M5125) 160-pin PQFP package
Supports through Parallel Port pins Supports PS/2 PS/2 Mouse Built-in Keyboard Controller Real Time Clock
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M512x Mega Controller with
Table Contents
Section Introduction Features Function Block Diagram. Register Overview Section Description Pinout Diagram Description Numerical List Alphabetical List Section Configuration Description Power Management Features Configuration Port Power Management Features Section Floppy Disk Controller. Register Overview Register Description Result Phase Status Registers. Processor Software Interface Command Descriptions Command Description Table Section Serial Port Registers Line Control Register Programmable Baud Generator Line Status Register Interrupt Identification Register Interrupt Enable Register FIFO Control Register. Modem Control Register Modem Status Register Scratchpad Register 5.10 Infrared Interface Section Keyboard Controller Real Time Clock Functional Description Keyboard Interface Keyboard Controller. Real Time Clock Section BIOS BIOS Buffer Section Parallel Port Parallel Port Interface XT/AT compatible, Bi-directional modes. Section Common Ports Section Electrical Characteristics 10.1 Absolute Maximum Ratings 10.2 Characteristics. 10.3 Characteristics. 10.4 Test Conditions. Section Packaging Information Section Ordering Information. Section Revision History Worldwide Distributors Sales Offices
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Section Introduction
Features Functions
Acer Labs' M512x chip full-function universal asynchronous receiver/ transmitters (UARTs), keyboard interface, real time clock, floppy disk controller (FDC) with data separator, parallel port, standard XT/AT address decoding on-chip functions, configuration register. offers single-chip solution most common Notebook peripherals. floppy disk controller fully compatible with industry-standard 765A 82077SL architecture. includes more advanced options such high performance data separator, extended track range 4096, high performance power management, implied seek command, scan command, supports both 360K/1.2M/720K/1.44M/2.88M formats. UARTs compatible with either INS8250N-B, NS16450 16550. complete compatibility with AT's parallel port. configuration register one-byte wide programmed hardware software. controlling this register, user assign standard addresses disable major on-chip function (e.g., FDC, either UART, parallel port) independent others. This allows flexibility system configuration when adapter boards contain duplicate functions. M512x provides support Plug-and-Play standard recommended functionality support Windows Through internal configuration registers, each M512x' logic device' address, channel channel programmed. There address location options, options, three channel options each logical device except RTC. KBC' address routable. RTC' address routable well.
M512x Block Diagrams
following figures show overall block diagram M512x.
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M512x Mega Controller with
interface
SD0-SD7 IORJ IOWJ SA0-SA15 DACK0J-DACK3J DRQ0-DRQ3 IRQ1,IRQ3-12,IRQ14-15 RDATAJ WGATEJ WDATAJ HDSELJ DIRJ STEPJ DSKCHGJ DRV0-1 PDIR MOT0-1 TRK0J DENSEL INDEXJ ROMOEJ ROMCSJ RD0-7 10-17,20-25,30-34
SIN1, SOUT1 RTS1J DTR1J CTS1J DSR1J DCD1J RI1J SIN2,SOUT2 RTS2J DTR2J CTS2J DSR2J DCD2J RI2J AUTOFDJ INITJ SLCTINJ STROBEJ BUSY ACKJ SLCT ERRORJ IOCHRDY PD0-PD7 XTAL1,2 VBAT KDAT,KCLK MDAT,MCLK
Serial port
Serial port
M512x
Floppy disk interface
Printer port interface
BIOS Buffer Common
Figure
M512x Block Diagram
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Register Overview
Table Address Decode Block Name Floppy Disk Serial Port COM1 Serial Port COM2 Parallel port ECP+EPP+SPP Logical Device Function support support
Address Range Base (0-5) Base (0-7) Base (0-7) Base (0-3) Base (0-7) Base (0-3), (400-402) Base (0-7), (400-402) 0x60, 0x64 0x70, 0x71
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M512x Mega Controller with
Section Description
Pinout Diagram
DRVDEN0 DRVDEN1 MOT0J DRV1J DRV0J MOT1J DIRJ STEPJ WDATAJ WGATEJ HDSELJ INDEXJ TRK0J WPROTJ RDATAJ DSKCHGJ MID1 MID0 14CLKI CIO30/KBCCLK CIO31/CS0J CIO32/CS1J PDIR/PS2DRV SA[13] SA[14] SA[15] CIO33/ALT_KCLK CIO34/ALT_KDAT CIO35/ALT_MCLK CIO36/ALT_MDAT CIO37/ALT_KBC X24TAL1 X24TAL2 CLK01 CLK02 ROMOEJ
M512x
ROMCSJ CIO25 CIO24 CIO23 CIO22 CIO21 CIO20 CIO17/I2C_DAT CIO16/I2C_CLK CIO15/P20 CIO14/P21 CIO13/IRTX CIO12/IRRX CIO11/IRQIN2 CIO10/IRQIN1 MCLK MDAT KCLK KDAT IOCHRDY DRQ3 DACK3J DRQ2 DACK2J DRQ1 DACK1J DRQ0 DACK0J
Figure 2-1. M512x Diagram
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Description
Table lists functions M512x pins. represents logic nominal) high represents logic (+2.4V nominal). Table M512x Description Table Type Description Data bus. These signals used host microprocessor transmit data from M512x. These pins high impedance state when output mode. Read. This active signal issued host microprocessor indicate read operation. Write. This active signal issued host microprocessor indicate write operation. Address Enable. This active high signal indicates operations host data bus. Address. These bits determine address accessed during IORJ IOWJ cycles. Acknowledge. active input signal acknowledging request data transfer. This input enables read write internally. request. This active high output request byte transfers data host. This signal cleared last byte data transfer DACKJ signal going low. Terminal Count. This signal indicates M512x that data transfer complete. only accepted when DACKJ low. active high mode active PS/2 mode. Interrupt Requests.
Name Number HOST Processor Interface SD0-SD7 70-72
IORJ IOWJ SA0-SA15 DACK0JDACK3J DRQ0DRQ3
41-53, 27-29 81,83,85,87 82,84,86,88
IRQ1, IRQ3-12, IRQ14-15
67,66,65,64, 63,62,61,59, 58,57,56,55,
Reset. This active high signal resets M512x must valid minimum. M512x, falling edge reset latches jumper configuration. jumper select lines must valid prior this edge. Read Disk Data. This data read signal from disk connected here. Each falling edge represents flux transition encoded data. Write Gate. This active-low, high-drive output enables write circuitry selected disk drive. This signal prevents glitches during power-up powerdown. Unstable power prevents writing disk. Write Data. This active output write- precompensated serial data written onto selected disk drive. Each falling edge causes flux change media. Head Select. This active output determines which disk drive head active. Head high (open) Head Direction. This active output determines direction head movement (low step-in, high step-out). During write read modes, this output high. Step. This active signal produces pulse move head during seek operation. Disk Change. This disk interface signal indicates when disk drive door open. This signal read from address xx7h.
Floppy Disk Interface RDATAJ WGATEJ
WDATAJ
HDSELJ DIRJ
STEPJ DSKCHGJ
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Table M512x Description Table (continued) Name Number Type Description Floppy Disk Interface DRV0J, Drive Select Active low, output select drives 0-1. DRV1J PDIR This used indicate direction Parallel port data bus. output/write, input read. PS2DRV Drive PS/2 mode, this input indicates whether second drive connected; this signal should second drive connected. This status reflected read Status Register MID0-1 20,19 Media inputs. floppy enhanced mode, these inputs media inputs. MOT0J, Motor These active-low outputs select motor drives 0-1. MOT1J WPROTJ Write Protected. This active-low Schmitt Trigger input senses from disk drive that disk write-protected. write command ignored. TRK0J Track This Schmitt Trigger input signal senses from disk drive that head positioned over outermost track. INDEXJ Index. This active Schmitt Trigger input senses from disk drive that head positioned over beginning track, marked index hole. DRVDEN Data Rate 0-1. This output reflects bits Data Rate Register. Serial Port Interface SIN1, SIN2 145,155 Receive Data. Receiver serial data input. SOUT1, 146,156 Transmit Data. Transmitter serial data output from Serial Port. SOUT2 RTS1J Request send. Active Request send output Primary Serial port. Handshake output signal notifies modem that UART ready transmit data. This signal programmed writing Modem Control Register (MCR). hardware reset will clear RTSJ signal inactive mode (high). Forced inactive during loop mode operation. CFGPORT Configuration port select. During reset active, this input read latched define configuration register' base address. RTS2J Request send. This active signal Secondary Serial Port. Handshake output signal notifies modem that UART ready transmit data. This signal programmed writing Modem Control Register (MCR). hardware reset will clear RTSJ signal inactive mode (high). Forced inactive during loop mode operation. KBC_EN enable control. During reset active, this input read latched enable after reset. signal overwritten configuration register. DTR1J Data Terminal Ready. This active output primary serial port. Handshake output signal signifies modem that UART ready establish data communication link. This signal programmed writing Modem Control Register (MCR). hardware reset will clear DTRJ signal inactive during loop mode operation. RTC_EN enable control. During reset active, this input read latched enable after reset. This signal overwritten configuration register.
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Table M512x Description Table (continued) Name Number Type Description Serial Port Interface DTR2J Data Terminal Ready. This active output secondary serial port. Handshake output signal notifies modem that UART ready establish data communication link. This signal programmed writing Modem Control Register (MCR). hardware reset will clear DTRJ signal inactive mode (high). Forced inactive during loop mode operation. PS2_ATJ mode mode select. When active, this input read latched define PS-2 mode. CTS1J 149, Clear Send. This active input primary secondary serial ports. CTS2J Handshake signal which notifies UART that modem ready receive data. monitor status CTSJ signal reading Modem Status Register (MSR). CTSJ signal state directly comparative with after last read. Interrupt Enable Register set, interrupt generated when CTSJ changes state. CTSJ signal effect transmitter. Note complement CTSJ. DSR1J 147, Data Ready. This active input primary secondary serial DSR2J ports. Handshake signal which notifies UART that modem ready establish communication link. monitor status DSRJ signal reading bit5 Modem Status Register (MSR). DSRJ signal state change from high after last read will raise Interrupt Enable Register set, interrupt generated when DSRJ changes state. Note: complement DSRJ. DCD1J, 152, Data Carrier Detect. This active input primary secondary serial DCD2J ports. Handshake signal which notifies UART that carrier signal detected modem. monitor status DCDJ signal reading Modem Status Register (MSR). DCDJ signal state rises after last read will raise Interrupt Enable Register set, interrupt generated when DCDJ changes state. Note complement DCDJ. RI1J, RI2J 151, Ring Indicator. This active input primary secondary serial ports. Handshake signal that notifies UART that telephone ring signal detected modem. monitor status signal reading Modem Status Register (MSR). risen signal state after last read will raise Interrupt Enable Register set, interrupt generated when changes state. Note complement RIJ.
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Table M512x Description Table (continued) Name Number Type Description Printer Port Interface AUTOFDJ Autofeed Output. This active output causes printer automatically feed line after each line printed. This signal complement Printer Control Register. INITJ Initiate Output. This active signal printer control register. This signal used initialize printer. SLCTINJ Printer select input. This active signal selects printer. This complement Printer Control Register. STROBEJ Strobe Output. This active pulse used strobe printer data into printer. This output signal complement Printer Control Register. BUSY Busy. This signal indicates status printer. high indicates printer busy ready receive data. Printer Status Register complement BUSY input. ACKJ Acknowledge. This active signal from printer indicates received data ready accept data. Printer Status Register reads ACKJ input. Paper End. This signal indicates that printer paper. Printer Status Register reads input. SLCT Printer Selected Status. This active high signal from printer indicates that power Printer Status Register reads SLCT input. ERRORJ Error. This active signal indicates error condition printer. PD0-PD7 138-131 Port Data. This bi-directional parallel data used transfer information between peripherals. IOCHRDY IOCHRDY. mode, this pulled extend read/write command. Real-Time Clock XTAL1 ICLK 32Khz Crystal Input. XTAL2 OCLK 32Khz Crystal Output. VBAT Battery Voltage. Power Good Input. Keyboard Controller KDAT Keyboard Data. KCLK Keyboard Clock. MDAT Mouse Data. MCLK Mouse Clock.
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Table M512x Description Table (continued) Name Number Type Description BIOS Buffer ROMOEJ Output Enable. ROMCSJ Chip Select. RD0-7 111-118 Bus. Common CIO10-11 96-97 Common pin. CIO12 Common pin. IRRX. CIO13 Common pin. IRTX. CIO14 Common pin. function. CIO15 Common pin. function. CIO16 Common pin. I2C_CLK. CIO17 Common pin. I2C_DAT. CIO20-24 105-109 Common pin. CIO25 Common pin. KEYLOCKJ. CIO30 Common pin. KBC_CLK. CIO31 Common pin. General Chip Select decoder CS0J. CIO32 Common pin. General Chip Select decoder CS1J. CIO33 Common pin. Alternative Keyboard Clock. CIO34 Common pin. Alternative Keyboard Data. CIO35 Common pin. Alternative Mouse Clock. CIO36 Common pin. Alternative Mouse Data. CIO37 Common pin. Alternative select.
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Table M512x Description Table (continued) Name Number Type Description Miscellaneous X24TAL1 ICLK Clock This external connection parallel resonant crystal. CMOS compatible oscillator required crystal used. X24TAL2 OCLK Clock This crystal. external clock used, this should connected. This should used drive other drivers. X14CLKI Clock This 14.318 clock source XCLKO1 Clock out. This 14.318 clock out. XCLKO2 Clock out. This second 14.318 clock out. Power Pins 21,60,101, Power. Volt supply pin. 125,139 1,8,40,71,95, Ground pins. 123,130
Type Description ICLK OCLK OD24 Input compatible. Input with Schmitt Trigger. input. output. Output with sink source Open drain outputs, sinks
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Numerical List Name DRVDEN0 DRVDEN1 MOT0J DRV1J DRV0J MOT1J DIRJ STEPJ WDATAJ WGATEJ HDSELJ INDEXJ TRK0J WPROTJ RDATAJ DSKCHGJ MID1 MID0 X14CLKI CIO30/ KBC_CLK CIO31/CS0J CIO32/CS1J PDIR/PS2DRV SA13 SA14 SA15 CIO33/ ALT_KCLK CIO34/ ALT_KDAT CIO35/ ALT_MCLK CIO36/ ALT_MDAT CIO37/ ALT_KBC X24TAL1 X24TAL2 XCLKO1 XCLKO2 ROMOEJ Type ICLK OCLK Name SA10 SA11 SA12 IRQ15 IRQ14 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ1 IORJ IOWJ Type
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Numerical List (continued) Name DACK0J DRQ0 DACK1J DRQ1 DACK2J DRQ2 DACK3J DRQ3 IOCHRDY KDAT KCLK MDAT MCLK CIO10/IRQIN1 CIO11/IRQIN2 CIO12/IRRX CIO13/IRTX CIO14/GA20 CIO15/KBRCJ CIO16/I2C_CLK CIO17/I2C_DAT CIO20 CIO21 CIO22 CIO23 CIO24 CIO25 ROMCSJ
Type
Name VBAT X32TAL1 X32TAL2 SLCT BUSY ACKJ SLCTINJ INITJ ERRORJ AUTOFDJ STROBJ SIN1 SOUT1 DSR1J RTS1J/ CFG_PORT CTS1J DTR1J/RTC_EN RI1J DCD1J RI2J DCD2J SIN2 SOUT2 DSR2J RTS2J/KBC_EN CTS2J DTR2J/PS2_ATJ
Type ICLK OCLK
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Alphabetical List Name ACKJ AUTOFDJ BUSY CIO10/IRQIN1 CIO11/IRQIN2 CIO12/IRRX CIO13/IRTX CIO14/GA20 CIO15/KBRCJ CIO16/I2C_CLK CIO17/I2C_DAT CIO20 CIO21 CIO22 CIO23 CIO24 CIO25 CIO30/KBC_CLK CIO31/CS0J CIO32/CS1J CIO33/ALT_KCLK CIO34/ALT_KDAT CIO35/ALT_MCLK
CIO36/ALT_MDAT
CIO37/ALT_KBC CTS1J CTS2J DACK0J DACK1J DACK2J DACK3J DCD1J DCD2J DIRJ DRQ0 DRQ1 DRQ2 DRQ3 DRVDEN0
Type
Name DRVDEN1 DRV1J DRV0J DSKCHGJ DSR1J DSR2J DTR1J/RTC_EN DTR2J/PS2_ATJ ERRORJ HDSELJ INDEXJ INITJ IOCHRDY IORJ IOWJ IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 KDAT KCLK MCLK MDAT MID1 MID0 MOT0J MOT1J
Type
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M512x Mega Controller with
Alphabetical List (continued) Name PDIR/PS2DRV RDATAJ RI1J RI2J ROMCSJ ROMOEJ RTS1J/CFG_PORT RTS2J/KBC_EN SA10 SA11 SA12 SA13 SA14 SA15
Type
Name SIN1 SIN2 SLCTINJ SLCT SOUT1 SOUT2 STEPJ STROBJ TRK0J VBAT WDATAJ WPROTJ WGATEJ X14CLKI X24TAL1 X24TAL2 X32TAL1 X32TAL2 XCLKO1 XCLKO2
Type ICLK OCLK ICLK OCLK
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Section Configuration Description Power Management Features
Configuration Port
This configuration based typical Plug-and-Play architecture allows BIOS assign resources POST. assign M512x configuration key, <0x51, 0x23> must written CONFIG PORT enter CONFIGURE mode. Then follow Plug-and-Play procedure configure each device. configuration 0xBB must written CONFIG PORT exit CONFIGURE mode enter mode. Note After exiting CONFIGURE mode, current logic device select cleared. must select logic device before program After hard reset Power reset, M512x mode with logical devices disable except RTC. hardware setting pins control RTC. Then normal configure procedure also suitable RTC. hardware setting listed table 3-2. logical devices configured through standard Configuration Ports INDEX DATA placing M512x into Configuration Mode. BIOS uses these configuration ports initialize logical devices POST. INDEX DATA ports only valid when M512x Configuration Mode. hardware setting CFG_PORT latched select CFG_PORT 3F0h 370h.
CHIP LEVEL REGISTERS Index name Index 0x02h Hard reset, Soft reset default values 0x00, 0x00 Soft reset configuration registers. This automatically cleared after write. This register write only.
Index 0x03h
0x03, CIO1, CIO2, CIO3 selection register address. 0xE0 0xE2 0xE4 0xEA Disable access Enable access CIO1, CIO2, CIO3.
Index 0x07h
0x00, 0x00 Select current logic device. This allows access each logical device' registers. Read
Index 0x20h Port Name CONFIG PORT INDEX PORT DATA PORT CFG_PORT=0 0x3F0 0x3F0 0x3F1 CFG_PORT=1 0x370 0x370 0x371 Type
0x23, 0x23 defined Read only.
device
identification.
Index 0x21h
0x51, 0x51 defined Read only.
device
identification.
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M512x Mega Controller with
Index 0x22h
0x00, 0x00 Direct powerdown (Note disable enable read Direct powerdown Parallel Port (Note disable enable Direct powerdown UART1 (Note disable enable Direct powerdown UART2 (Note disable enable Turn oscillator. read
Index 0x2Dh
0x00,
Reserved test purposes only
LOGICAL DEVICE REGISTERS (FDC) Index 0x30h 0x00, 0x00 (Note disable enable read
Index 0x60h
0x03, 0x03 higher address FDC' base address. read
Index 0x23h
0x00, read Auto powerdown Parallel Port. disable enable Auto powerdown UART1. disable enable Auto powerdown UART2. disable enable read
Index 0x61h
0xF0, 0xF0 lower address FDC' base address.
Index 0x24h
0x00, read pin26 functions PDIR pin26 functions SDRV. IRQ8 active high IRQ8 active low.(Note
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Index 0x70h
0x06, 0x06 Select channel used FDC. 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15 read
Index 0xF1h
0x00, External Floppy Select. internal external Drive internal, Drive external Density Select. Normal force force Media ID[1-0] polarity. normal inverted Boot Floppy.
Index 0x74h
0x02, 0x02 Select channel used DMA0 DMA1 DMA2 DMA3 None read
Index 0xF2h
0xFF, Floppy Drive type. Floppy Drive type. Floppy Drive type. Floppy Drive type.
Index 0xF4h Index 0xF0h 0x08, Normal mode Enhanced mode Burst mode. Non-burst mode read mode mode swap. Swap Drive Drive
0x00, DRVDEN[1-0] signal definition (refer Table 3-4). read Data Rate Table Select (refer Table 3-3).
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M512x Mega Controller with
LOGICAL DEVICE REGISTERS (Parallel Port) Index 0x30h 0x00, 0x00 Activate Parallel Port. (Note disable enable read 0x03, 0x03 higher address Parallel Port' base address. Index 0x61h read 0x78, 0x78 lower address Port' base address. Index 0xF1h 0x05, Non-burst mode. Burst transfer mode time-out interrupt. disable enable operation clock. Mhz. read Parallel Index 0xF0h 0xBC, Compatible mode. ECP+EPP1.9 ECP+EPP FIFO threshold value. Default 0001. interrupt type (not valid when mode). active low. active high.
Index 0x60h
Note 8-byte boundary required available Index 0x70h 0x05, 0x05 Select channel used Parallel Port. 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15 read 0x04, 0x04 Select channel used Parallel Port. DMA0 DMA1 DMA2 DMA3 None read
Index 0x74h
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LOGICAL DEVICE REGISTERS (UART1) Index 0x30h 0x00, 0x00 UART1 (Note disable enable read Index 0xF0h 0x00, MIDI support disable enable High speed mode disable enable Normal 8Mhz clock source UART1 read 0x00, receive polarity. active high active transmit polarity. active high active Full duplex Half duplex mode. Normal IrDA Normal read 0x0C, Baud Rate output RI1. disable enable half-duplex Tx-to-Rx time- timer. disable enable half-duplex Rx-to-Tx time-out timer. disable enable half-duplex time-out time control. 41-bit time 39-bit time 42-bit time 39-bit time 40-bit time read
Index 0x60h
0x03, 0x03 higher address UART1' base address. read
Index 0xF1h
Index 0x61h
0xF8, 0xF8 lower address UART1' base address.
Index 0x70h 0x04, 0x04 Select used UART1. 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15 read
Index 0xF2h
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M512x Mega Controller with
LOGICAL DEVICE REGISTERS (UART2) Index 0x30h 0x00, 0x00 UART2 (Note disable enable read Index 0xF0h 0x00, MIDI support disable enable High speed mode disable enable clock source UART2 Normal read
Index 0x60h
0x02, 0x02 higher address UART2' base address. read
Index 0x61h 0xF8, 0xF8 lower address UART2' base address.
Index 0xF1h
0x02, receive polarity. active high active transmit polarity. active high active Half duplex Full duplex mode. Normal IrDA Normal read input source. IRRX2 IRTX2
Index 0x70h
0x03, 0x03 Select channel used UART2. 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15 read
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M512x Mega Controller with
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Index 0xF2h
0x0C, Baud Rate output disable enable half-duplex Tx-to-Rx time-out timer. disable enable
LOGICAL DEVICE REGISTERS (KEYBOARD) Index 0x30h 0x00, 0x00 Keyboard controller. This hardware setting RTS2J. (Note disable enable read
half-duplex Rx-to-Tx time-out timer disable enable half-duplex time-out time control. 40-bit time 42-bit time 39-bit time 41-bit time 39-bit time read
Index 0x70h
0x01, 0x01 Select channel used Keyboard. 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15 read 0x00, 0x00 Select channel used PS/2 Mouse. 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15 read
LOGICAL DEVICE REGISTERS (RTC) Index 0x30h 0x00, 0x00 Deactivate (Note Activate RTC. This hardware setting DTR1J. read Index 0xF0h 0x00, Index 0x72h CMOS 0x80-0x9F Unlock Lock CMOS 0xA0-0xBF. Unlock Lock CMOS 0xC0-0xDF Unlock Lock CMOS 0xE0-0xFF. Unlock Lock read Select upper 128-byte bank Select lower bank
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M512x Mega Controller with
Index 0xF0h
0x00, 0x00 clock source 8Mhz clock source 7.16Mhz. Read only. Indicates type keyboard PS2. read
Index 0xE1h
0x01, CIO11 function definition. output input Input/Output signal polarity. non-inverted inverted read Normal function. Input function IRQIN2 mapping IRQIN2 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15
LOGICAL DEVICE REGISTERS (Common I/O) Index 0x30h 0x00, 0x00 Common port. disable enable read
Index 0xE0h
0x01, CIO10 function definition input output Input/Output signal polarity non-inverted inverted read Index 0xE2h Normal function. Input function IRQIN1 mapping IRQIN1. 0000 None 0001 IRQ1 0010 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 1110 IRQ14 1111 IRQ15
0x01, CIO12 function definition. output input Input/Output signal polarity non-inverted inverted read Normal function Input function IRRX2 read
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M512x Mega Controller with
-Preliminary, Confidential, Proprietary-
Index 0xE3h
0x01, CIO13 function definition. output input Input/Output signal polarity. non-inverted. inverted read Normal function. Output function IRTX2
Index 0xE6h
0x01, CIO16 function definition. output input Input/Output signal polarity. non-inverted. inverted read Normal function Output function (Note2).
Index 0xE4h
0x01, CIO14 function definition. output input Input/Output signal polarity non-inverted. inverted read Normal function. Select function 0x01, CIO15 function definition. output. input Input/Output signal polarity. non-inverted inverted read
Index 0xE7h
0x01, CIO17 function definition. output input Input/Output signal polarity. non-inverted inverted read Normal function. Select function (Note2).
Index 0xE5h
Index 0xE8
0x01, CIO20 function definition. output input Input/Output signal polarity. non-inverted. inverted read
Normal function Select function
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M512x Mega Controller with
Index 0xE9h
0x01, CIO21 function definition. output. input Input/Output signal polarity. non-inverted. inverted read
Index 0xEDh
0x01, CIO25 function definition. output input. Input/Output signal polarity. non-inverted. inverted read Normal function. Select KEYLOCK function
Index 0xEAh
0x01, CIO22 function definition. output input Input/Output signal polarity. non-inverted. inverted. read Index 0xEEh
0x00, Address line[13-8] CS0J. CS0J decoding range. A[3-0]=0000b A[3-0]=00xxb A[3-0]=0xxxb A[3-0]=xxxxb
Index 0xEBh
0x01, CIO23 function definition. output input. Input/Output signal polarity. non-inverted inverted. read
Index 0xEFh
0x00, read Address line[7-4] CS0J.
Index 0xF5h
0x01, CIO30 function definition. output input Input/Output signal polarity. non-inverted inverted. read Normal. Input function clock source
Index 0xECh 0x01, CIO24 function definition output input Input/Output signal polarity non-inverted inverted. read
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M512x Mega Controller with
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Index 0xF6h
0x01, CIO31 function definition. output input Input/Output signal polarity. non-inverted. inverted read Normal function. Output function CS0J 0x01, CIO32 function definition. output input Input/Output signal polarity. non-inverted inverted read
Index 0xFAh
0x01, CIO35 function definition. output input Input/Output signal polarity. non-inverted. inverted read
Index 0xFBh
0x01, CIO36 function definition output input Input/Output signal polarity non-inverted inverted read
Index 0xF7h
Index 0xFCh Normal function. Output function CS1J Index 0xF8h 0x01, CIO33 function definition. output input Input/Output signal polarity. non-inverted. inverted read
0x01, CIO37 function definition. output. input Input/Output signal polarity non-inverted inverted read Normal function enable secondary signal source. CIO33 functions ALT_KCLK CIO34 functions ALT_KDAT CIO35 functions ALT_MCLK CIO36 functions ALT_MDAT CIO37 input functions switch control traditional secondary signal source. When CIO37 traditional selected. When secondary selected.
Index 0xF9h
0x01, CIO34 function definition. output input Input/Output signal polarity. non-inverted inverted read
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M512x Mega Controller with
Index 0xFDh
0x00, Address line[13-8] CS1J. CS1J decoding range. A[3-0]=0000b A[3-0]=00xxb A[3-0]=0xxxb A[3-0]=xxxxb 0x00, read Address line[7-4] CS1J. Note IRQ8 reserved only. Note access port address device determined CS0J. signals XSD[0] XSD[1] will reflect I2C_CLK I2C_DAT individually. Note During direct powerdown, access ports denied. wake device, setting corresponding required. Note disable function device same behavior direct powerdown function except device remains reset state. CS0J assertion read cycle. disable enable CS1J assertion write cycle. disable enable CS1J assertion read cycle. disable enable
Index 0xFEh
Index 0xFFh
0x00, CS0J assertion write cycle. disable enable
Table Name RTS1J RTS2J DTR1J DTR2J Table
M512x Hardware Setting Configuration Function CFG_PORT 0x3F0 0x370 KBC_EN disable enable RTC_EN disable enable PS2_ATJ (KBC) mode mode Drive Option Densel Drate Drate1 Drate0
Data Rate Register Settings (3F7) 0xF4[4:3]* KB/sec Drate Drate Drate Opt1 Drate Opt0 1000 1000 Note *Drive Table Regular drives 2.88MB 3-mode drive
Table
Page
Drvden Output Mapping Drive Type Table
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M512x Mega Controller with 0xF4 [1:0] Drvden Signal Definition DRVDEN1 DRATE0 DRATE0 DRATE0 DRATE1 DRVDEN0 DENSEL DRATE1 nDENSEL DRATE0
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3.2.2.1 Powerdown Modes
rest chip powered down ways: direct powerdown automatic powerdown. Direct powerdown results immediate shutdown part without regard current state part. Automatic powerdown results when certain conditions become true within part. Direct Powerdown
Power Management Features
M512x contains power management features that makes ideal design notebook desktop personal computers. These features classified into power management part internal oscillator. powerdown part done independently internal oscillator M512x.
3.2.1 Oscillator Power Management
M512x supports built-in crystal oscillator that programmed either powered down active, independent power state chip. This capability implemented OSC-OFF 0x22. When OSCOFF high, internal oscillator off. When external oscillator used, power saved turning internal oscillator. internal oscillator used, oscillator powered (even when rest chip powered off) allowing chip wake quickly stable state. recommended keep internal oscillator even powerdown state. main reason this that recovery time oscillator during wake-up take tens milli-seconds under worst case, which create problems with sensitive application software. typical application, internal oscillator should unless system goes into power saving standby mode. Such mode request would made system time-out user. this case, system software would take over must turn oscillator sufficiently ahead awakening part. case external oscillators, power-up characteristics similar. external source remains active during time M512x powered down, then recovery time effect minimized.
Direct powerdown conducted powerdown register (bit FDC_PWD 0X22. Programming this high will powerdown M512x after part internally reset. current status lost this type powerdown mode used. part exit powerdown from this mode hardware software reset. This type powerdown will override automatic powerdown. part automatic powerdown when powerdown issued, then previous status part will lost, M512x will reset default values. Auto Powerdown
Automatic powerdown conducted "Set Powerdown Mode" command. There four conditions required before part will enter powerdown. these conditions must true part initiate powerdown sequence. These conditions listed follows: motor enable pins ME[0:3] must inactive, part must idle; this indicated (INT high even polling interrupt), head unload timer must have expired, auto powerdown timer must have timed out.
3.2.2 Part Power Management
This section deals with power management rest chip excluding oscillator. This part shows powerdown modes wake modes activated.
command used enable powerdown setting AUTOPD command high. command also provides capability programming minimum power-up time command. minimum power-up time refers minimum amount time part will remain powered-up after being awakened reset. internal timer initiated soon auto powerdown command enabled. part then powered down provided remaining conditions met. software reset will reinitialize timer. Changing data rate extends auto powerdown timer only data rate changed during countdown. Disabling auto powerdown mode cancels timers holds M512x auto powerdown.
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M512x Mega Controller with
3.2.2.2 Powerdown Mode UART Printer
UART1, UART2 printer enter direct powerdown auto powerdown respectively setting their relative powerdown 0X22 0x23. powerdown used when part auto powerdown, powerdown will override auto powerdown. However, when part awakened software reset, auto powerdown command (including minimum delay timer) will again become effective previously programmed. part awakened hardware reset, auto powerdown disabled. After reset, part will through normal sequence. drive status will initialized. FIFO mode will default mode hardware reset software reset LOCK command blocking Finally, after delay, polling interrupt will issued. Wake from Auto Powerdown
3.2.2.3 WAKE MODES
This section describes conditions awakening part from both direct automatic powerdown. Power conservation battery life main reason power management required. This means that M512x must kept powerdown state long possible should powered late possible without compromising software transparency. keep part powerdown mode late possible implies that part should wake-up fast possible. However, some amount time required part exit powerdown state prepare internal microcontroller accept commands. Application software very sensitive such delay order maintain software transparency, recovery time wake-up process must carefully controlled system software. Wake from Powerdown
part enters powerdown state through auto powerdown mode, then part awakened reset appropriate access certain registers. hardware software reset used, then part goes through normal reset sequence. access through selected registers, then M512x resumes operation though never powerdown. Besides activating RESET software reset bits DSR, following register accesses will wake-up part: Enabling motor enable bits register (reading does wake-up part) read from register read write FIFO register
M512x enters powerdown through powerdown bit, must reset exit. form software hardware reset will serve, although recommended. other register access will wake part, including writing DOR's motor enable (ME[0:3]) bits.
these actions will wake-up part. Once awake, M512x will initiate auto powerdown time sec. (Depending auto powerdown command). part will powerdown again when powerdown conditions stated Auto Powerdown section satisfied.
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M512x Mega Controller with
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Section Floppy Disk Controller
Register Overview
integrated M512x part register- hardware-level compatible with industry standard 765A 82077SL standards. Table lists address Table Controller Address Register (PS/2 mode only) (PS/2 mode only) Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (First First Out) FIFO reserved Digital Input Register Configuration Control Register controller. Table summary register hardware reset.
When this location accessed, only driving, other bits held tristate. Table
Register DOR(R/W) TDR(R/W) MSR(R) DSR(W) DIR(R) CCR(W) SRA(R) SRB(R)
Summary Register Hardware Reset Powerdown State
Bits State Reset State Reset State Reset State Reset State Reset State Reset State Reset State Reset State Address
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M512x Mega Controller with
Register Description 4.2.2 Status Register (SRB)
This section describes register bits registers that directly accessible CPU. Address Read only This register read-only monitors state several disk interface pins, PS/2 modes. accessed time during PS/2 mode. mode, data pins D0-D7 held high impedance state read address 3F1h. PS/2 mode Name Drive Sel0 Wdata Toggle Rdata Toggle Wgate MOTEN1 MOTEN0 Reserved Always read logic Reserved Always read logic Drive Select Reflects status Drive Select (address This cleared after hardware reset, unaffected software reset Write Data Toggle This changes Read Data Toggle Every inactive edge RDATA input causes this change state. state every inactive edge WDATA Write Gate WGATE disk interface output (active high) Motor Enable MTR1 disk interface output pin. This after hardware reset unaffected software reset. Motor Enable MTR0 disk interface output pin. This after hardware reset unaffected software reset.
4.2.1 Status Register (SRA)
Address Read only This register read-only monitors state IRQ6 several disk interface pins PS/2 modes. accessed time when PS/2 mode. mode, data pins D0-D7 held high impedance state read address 3F0h. PS/2 mode Name Pending DRV2J STEP TRK0J HDSEL INDXJ Interrupt Pending state Floppy Disk Interrupt output (active high). DRV2J DRV2 disk interface input pin, indicates that second drive been installed. Step Step output disk interface output (active high) Track TRK0 disk interface input (active low)
Head Select HDSEL disk interface input. logic selects side logic selects side Index Index disk interface input (active low) Write Protect Write protect disk interface input. logic indicates that disk write protected. Direction Head movement direction (active high). logic indicates inward direction logic outward.
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M512x Mega Controller with
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4.2.3 Digital Output Register (R/W)
Address Table Digital Output Register Description Description Motor Enable This controls Motor drive MTR3. output high when inactive, when active. This provide information that control MTR1 pins, respectively when configuration register set. Motor Enable Same function except drive motor. Note that this signal brought pin. Motor Enable This controls Motor drive motor. When this MTR1 output high. Motor Enable Same except drive motor. Enable: When this enables DRQ, DAK, pins. zero disables these signals. Reset Controller: This resets controller when enables normal operation when does affect drive control data rate registers which reset only hardware reset. Drive Select: These pins encoded four drive select, gated with motor enable lines, that only drive selected when motor enable active. Internal Drive Decode Normal Digital Output Register Drive Select Outputs DS1J DS0J Motor Outputs MTR1J MTR0J
D1~D0
Table
Table
Internal Drive Decode Drives Swapped Digital Output Register Drive Select Outputs DS1J DS0J Motor Outputs MTR1J MTR0J
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M512x Mega Controller with
4.2.4 Tape Drive Register (TDR) Address This register included 82077 software compatibility. robust data separator used M512x does require characteristics modified tape support. contents this register used internally device. unaffected software reset. Bits tri-stated when read this mode.
Normal Floppy mode Normal mode. Register 3F3h contains only bits When this register read, bits high impedance. Tri-state Tristate Tri-state Tri-state Tri-state Tristate tapesel1 tapesel0
Enhanced Floppy mode (OS2) Register Enhanced Floppy mode operation Media Media Drive type Floppy boot drive tapesel1 tapesel0
this mode, DRATE0 DRATE1 pins inputs these inputs gated into bits register. These bits affected reset. Media Read only (pin table next page Media Read only (pin table next page Bits Drive Type These bits reflect 0XF2 configuration register bits. (please next page). Bits Floppy boot Drive. These bits show value 0xF1 configuration register bits. Bits Tape Drive select (R/W). Same Normal Enhanced Floppy mode
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M512x Mega Controller with
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Media Drate1
Media 0xF1-db5=0
0xF1-db5=1
Media Drate0
Media 0xF1-db4=0
0xF1-db4=1
Drive type Digital Output Register
Register drive type 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2
4.2.5 Main Status Register
Address 3F4h Read only
read-only main status register indicates current status disk controller. always available read. functions control flow data from data register. also indicates when disk controller ready send receive data. should read before each byte transferred from data register except during transfer. delay required when reading this register after data transfer.
Table
Main Status Register Description Description Request Master: Indicates that data register ready send receive data from CPU. This cleared immediately after byte transfer, again soon M512x ready next byte. Data Direction: Indicates whether controller expecting byte written read from data register. Non-DMA Execution: only during execution phase command non-DMA mode. other words, this set, multiple byte data transfer execution phase) must monitored either through interrupts, software polling described processor software interface section. Command Progress: after first byte command phase written. cleared after last byte result phase read. there result phase command, cleared after last byte command phase written. Drives Seeking: after last byte command phase seek recalibrate command issued drives 3~0, respectively. Cleared after reading first byte result phase sense interrupt command this drive.
D3~D0
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M512x Mega Controller with
4.2.6 Data Rate Select Register (DSR)
Address Table Write only Datarate Select Register Description Description RESET behaves same RESET except that this reset self clearing. POWERDOWN implements direct powerdown. Setting this high puts into powerdown state regardless state part. part reset internally then goes into powerdown. status saved operation progress aborted. This powerdown mode does turn internal oscillator. hardware software reset will exit M512x from this powerdown state. reserved PRECOMP adjusts WRDATA output disk compensate magnetic media phenomena known shifting. data patterns that susceptible shifting well understood M512x offsets data pattern written disk. amount precompensation depends upon drive media most cases default value acceptable. M512x starts precompensating data pattern starting Track CONFIGURE command change starting track precompensation. Table 4-10 lists precompensation values that selected Table 4-11 lists default precompensation values. default value selected three bits zeros. DRATE select four data rates listed Table 4-12. default value Kbps upon chip ("Hardware") reset. Other ("Software") Resets affect DRATE PRECOMP bits.
D4~D2
D1~D0
Table 4-10 PRECOMP
Precompensation Delay Values Precompensation Delay-
bits
DISABLED
0.00ns 41.67ns 83.34ns 125.00ns 166.67ns 208.33ns 250.00ns DEFAULT
Page
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M512x Mega Controller with
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Table 4-11 Data Rate Mbps Kbps Kbps Kbps
Default Precompensation Delay Values Precompensation Delay 41.67ns 125ns 125ns 125ns
Table 4-12 DRATESEL
Data Rates Data Rate Mbps Kbps Kbps Kbps Illegal Kbps Kbps Kbps
4.2.7 Data Register (R/W)
Address
This location through which commands, data, status flow between FDC. During command phase, loads controller's commands into this register based status register request master data direction bits. result phase transfers status registers header information same fashion. command parameter information disk data transfers through FIFO. 16-byte FIFO programmable threshold values. Data transfers generated bits Main Status Register. FIFO defaults M5105 compatible mode after "Hardware" reset (Reset "Software" Resets (Reset register) also place M512x into M5105-A3/A4-compatible mode LOCK This maintains PC-AT hardware compatibility. default values changed through CONFIGURE command (enable full FIFO operation with threshold control). advantage FIFO that allows system larger latency without causing disk error. Table 4-13 gives several examples delays with FIFO. data based upon following formula: Threshold# 1/DATA RATE 1.5us DELAY Table 4-13 FIFO Threshold Examples byte bytes bytes bytes FIFO Threshold Examples byte bytes bytes bytes FIFO Service Delay Maximum Delay Servicing Mbps Data Rate 1.5us 6.5us 1.5us 14.5us 1.5us 62.5us 1.5us 118.5us Maximum Delay Servicing Mbps Data Rate 16us 1.5us 14.5us 16us 1.5us 30.5us 16us 1.5us 126.5us 16us 1.5us 238.5us
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M512x Mega Controller with
start command, FIFO action always disabled command parameters must sent based upon settings. M512x enters command execution phase, clears FIFO data ensure that invalid data transferred. overrun underrun will terminate current command transfer data. Disk writes will complete current sector generating pattern valid CRC.
4.2.8 Configuration Control Register (CCR, PC-AT Modes)
Address Write only
Table 4-14 Configuration Control Register Description D7~D2 Description used. Data Rate Select: These bits datarate write-precompensation values disk controller. After hardware reset, these bits (250 Kbps). (please refer table 4-12)
4.2.9 Digital Input Register (DIR, Read)
Address Read only
Table 4-15 Digital Input Register Description (PC/AT mode) Description DSKCHG monitors same name reflects opposite value seen disk cable, regardless value /INVERT/. DSKCHG forced inactive along with inputs from floppy disk drive. other bits remain tri-stated. These bits reserved hard disk controller, thus during read this register, these bits high impedance state. Digital Input Register (PS/2 mode)
D6~D0
Table 4-15b
D6~D3 D2~D1
Description DSKCHG monitors same name reflects opposite value seen disk cable. undefined, always read logic "1". Data rate select. These bits control data rate floppy controller. These bits unaffected software reset, kbps after hardware reset. High density. This whenever kbps Mbps data rates selected, high when kbps kbps selected.
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M512x Mega Controller with
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Result Phase Status Registers
result phase command contains bytes that hold status information. format these bytes described following sections. confuse these register bytes with main status register which read-only register that always available. result phase status registers read from data register only during result phase.
4.3.1 Status Register (ST0)
Table 4-16 D7~D6 Status Register Description Description Interrupt Code Normal termination command. Abnormal termination command. Command executed, successfully completed. Invalid command issue. Command issued recognized valid command. Ready changed state during polling mode. Seek End: This after seek recalibrate command completed controller. Used during sense interrupt command. Equipment Check: This after recalibrate command track signal failed occur. Used during sense interrupt command. Used: Head Number: execution phase. Drive Select: execution phase. Drive selected Drive selected Drive selected Drive selected
4.3.2 Status Register (ST1)
Table 4-17 Status Register Description Description Track: This when controller transferred last byte last sector without becoming active. last sector end-of-track sector number programmed command phase. Used: Error: this clear, then there error address field correct sector. set, then there error data field. Over Run: This when controller serviced soon enough during data transfer execution phase. Table 4-18 shows time values. Data: This three possible problems: Controller cannot find sector specified command phase during execution read, write, scan command. address mark found even blank disk. Controller cannot read address fields without error during read command. Controller cannot find starting sector during execution read track command. Writable: write protect active when write format command issued. Missing Address Mark: this clear then disk controller cannot detect address field address mark after disk revolutions. set, then disk controller cannot detect data field address mark.
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M512x Mega Controller with
Table 4-18
Maximum Time Allowed Service Interrupt Acknowledge Request Execution Phase Data Rate Time Service 62.0 30.0 14.0
4.3.3 Status Register (ST2)
Table 4-19 Status Register Description Description Used: Control Mark: This controller tries read sector which contained deleted data address mark during execution read-data scan commands. read-deleted-data command executed, regular address mark detected. Error Data Field: This controller detects error data field. also set. Wrong Track: This only desired sector found, track number recorded sector current track different from that stored track register. Scan Equal Hit: This only equal condition satisfied during scan command. Scan Satisfied: This controller cannot find sector track number recorded sector track which meets desired condition during scan commands. Track: This only desired sector found, track number recorded sector track different from that stored track register recorded track number Missing Address Mark Data Field: This controller cannot find data field address mark during read/scan command. also set.
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M512x Mega Controller with
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4.3.4 Status Register (ST3)
Table 4-20 Status Register Description Description Used: Write Protect Status: This complement associated interface drive selected DCR. Used: Track Status: This complement associated interface drive selected DCR. Used: Head Select Status: command phase. This shows status associated sense-drive-status
Drive Selected: These bits show status associated bits sense-drive-status command phase. These bits show same status bits Drive selected Drive selected Drive selected Drive selected
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M512x Mega Controller with
Controller Functional Description 4.4.1 Controller Phases
handles commands three phases- command, execution result. Each phase described below.
4.4.1.2.2 Interrupt Mode
non-DMA mode selected, interrupt generated execution phase when each byte ready transferred. Main Status Register should read verify that interrupt data transfer. Bits Main Status Register set. interrupt cleared when byte transferred from data register. should transfer byte within allotted time. byte transferred within time allotted, overrun error indicated result phase when command terminates current sector. interrupt also generated after last byte transferred. This indicates beginning Result Phase.
4.4.1.1 Command Phase
writes series bytes data register. These bytes indicate command desired particular parameters required command. bytes must written order specified command description table. execution phase starts immediately after last byte command phase written. Main Status Register controls flow command bytes, must polled software before writing each Command Phase byte Data Register. Prior writing command byte, must must cleared MSR. After first command byte written Data Register, also remain until last Result Phase byte read. there Result Phase, cleared after last command byte written. command initiated after reading result bytes from previous command.
4.4.1.2.3 Software Polling
non-DMA mode selected interrupts suitable, poll Main Status Register during execution phase determine when byte ready transferred. Main Status Register reflects state interrupt pin. Otherwise, data transfer similar interrupt mode described above.
4.4.1.2 Execution Phase
disk controller performs desired command. Some commands require read write data from data register during this phase. Some commands such Seek control read/write head movement disk drive. Some commands does involve action disk drive, consists internal operation controller. there data transferred between controller, there three methods that used, mode, interrupt mode, software polling mode. these data transfer modes work with FIFO enabled disabled.
4.4.1.3 Result Phase
During Result Phase, reads series bytes from data register. These bytes indicate status command. This status indicate whether command executed properly, contain some control information. must both before each result byte read. After last result byte read, cleared, controller ready next command.
4.4.1.2.1 Mode
mode selected, request generated execution phase when each byte ready transferred. enable operations during execution phase, mode Specify command must enabled, signals must enabled Drive Control Register. controller responds request with DMA-acknowledge read- writestrobe. request cleared active edge DMA-acknowledge. After last byte transferred, interrupt generated, indicating beginning result phase. asserted terminate operation. internal gating, only recognized when -DAK input low.
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M512x Mega Controller with
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Table 4-21
M512x Command
READ DATA
Command Phase Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data read from disk drive transferred system Non-DMA modes. Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector
READ TRACK
Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data read from disk drive transferred system Non-DMA modes. Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector Command Phase
READ DELETED DATA
Command Phase Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data read from disk drive transferred system Non-DMA modes. Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector
READ
Command Phase Execution Phase: Controller reads first Field header bytes find reports these bytes system result bytes Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector
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M512x Mega Controller with
WRITE DATA
Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data transferred from system controller Non-DMA modes written disk. Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector Command Phase
FORMAT TRACK
Bytes Sector Sector Track Format Data Pattern Execution Phase: System transfers four bytes sector floppy controller Non-DMA modes. entire track formatted. data block Data Field each sector filled with data pattern byte Result Phase Status Register Status Register Status Register Undefined Undefined Undefined Undefined Command Phase
SCAN EQUAL
Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data transfer from system controller compared data read from disk Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector Command Phase
WRITE DELETED DATA
Command Phase Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data transferred from system controller Non-DMA modes written disk. Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector
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M512x Mega Controller with
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SCAN HIGH EQUAL
Command Phase Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data transfer from system controller compared data read from disk Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector
VERIFY
Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data read from disk transferred system. Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector Command Phase
SCAN EQUAL
Command Phase Track Number Drive Head Number Sector Number Bytes Sector Track Sector Number Intersector Number Data Length Execution Phase: Data transfer from system controller compared data read from disk Result Phase Status Register Status Register Status Register Track Number Head Number Sector Number Bytes Sector
DUMPREG
Command Phase Execution Phase: Internal registers read Result Phase Present Track Number Drive Present Track Number Drive Present Track Number Drive Present Track Number Drive Step Rate Time Motor Time Motor Time Sector Track/End Track LOCK FIFO POLL FIFOTHR PRETRK
PERPENDICULAR MODE
Command Phase Execution Phase: Internal registers written. Result Phase.
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M512x Mega Controller with
CONFIGURE
Command Phase FIFO POLL FIFOTHR PRETRK Execution Phase: Internal registers written. Result Phase
SENSE INTERRUPT
Command Phase Execution Phase: Status interrupt reported Result Phase Status Register Present Track Number
SPECIFY RECALIBRATE
Command Phase Execution Phase: Disk drive head stepped Track Result Phase Command Phase Step Rate Time Motor Time Motor Time Execution Phase: Internal registers written. Result Phase
POWERDOWN MODE RELATIVE SEEK
Command Phase Relative Track Number Execution Phase: Disk drive head stepped programmable number tracks. Result Phase Command Phase Execution Phase: Internal registers written Result Phase
VERSION
Command Phase Result Phase
SEEK
Command Phase Track Number Execution Phase: Disk drive head stepped desired track. Result Phase
LOCK
Command Phase LOCK Execution Phase: Internal registers written. Result Phase LOCK
SENSE DRIVE STATUS
Command Phase Execution Phase: Disk drive status information detected reported. Result Phase Status Register
INVALID
Command Phase Invalid Codes Result Phase Status Register (80H)
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Command Description 4.6.1 Read Data
read data op-code written data register followed bytes specified command description table. After last byte written, controller starts looking correct sector header. Once controller found, controller sends data CPU. After sector finished, sector number incremented this sector searched for. (multi-track) set, both sides track read. Starting side zero, sectors read until sector number specified track sector number reached. Then, side read starting with sector number one. mode, read-data command continues read until set. This means that controller should programmed transfer correct number bytes. should controlled asserted when enough bytes received. alternative these methods stopping read-data command program track sector number last sector number that read. controller stops reading disk with error message indicating that tried access sector number beyond track. number data bytes sector parameter defined Table 4-27. this zero, data length parameter defines number bytes that controller transfers CPU. data length specified smaller than 128, controller still reads entire byte sector checks CRC, though only number bytes specified data length parameter transferred CPU. Data length parameter should zero. number bytes sector parameter zero, data length parameter meaning should FFh. Table 4-27 Bytes/Sector Code Sector Size Selection Number Bytes Data Field 1024 2048 4096 8192 implied seek mode enabled both mode command this command, seek performed track number specified command phase. controller also waits head-settle-time implied seek enabled. After these conditions met, controller searches specified sector comparing track number, head number, sector number, number bytes/sector given command phase with appropriate bytes read disk address fields. correct sector found, there error address field, (CRC error) abnormal termination indicated. correct sector found, data) abnormal termination indicated. addition this, address field track number (bad track) address field track number different from that specified command phase, (wrong track) set. After finding correct sector, controller reads that data field. deleted data mark found set, sector read, (control mark) set, next sector searched for. deleted data mark found set, sector read, (control mark) set, read terminates with normal termination. error detected data field, both (CRC error) abnormal termination indicated. problems occur read command, read continues from sector next logical order (not physical order) until either error occurs. disk been inserted into disk drive, there many opportunities controller hang. does this waiting certain number disk revolutions. this occurs, controller forced abort command writing byte data register. interrupt generated when execution phase read data command terminates. Table 4-28 shows values that read back result phase. error occurs, result bytes indicate sector being read when error occurred.
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M512x Mega Controller with
Table 4-24 Last
Result Phase Termination Values with Error Information Result Phase Sector Track Head Sector
track sector number from command phase Sector number last operated controller
change value Track number programmed command phase
4.6.2 Read-Deleted-Data
This command same read-data command except handles deleted data mark. deleted data mark read, sector read normally. regular data mark found set, sector read, (control mark) set, next sector searched for. regular data mark found set, sector read, (control mark) set, read terminates with normal termination.
disk, sectors still read their physical order. header comparison fails, data) set, operation continues. there error address data field, read also continues. command terminates when read number sectors programmed parameter.
4.6.6 Read
This command causes controller read first address field finds. result phase contains header bytes that read. There data transfer during execution phase this command. interrupt generated when execution phase completed.
4.6.3 Write-Data
write-data command very similar read-data command except that data transferred from disk rather than other around. controller detects write-protect signal, (not writable) abnormal termination indicated.
4.6.7 Format-a-Track
This command formats track disk. After index hole detected, data patterns written disk including gaps, address marks, address fields, data fields. exact details number bytes each field controlled parameters given format-atrack command, (Index Address Field) mode command. data field consists fill-byte specified command, repeated fill entire sector. allow floppy formatting, must supply four address field bytes (track, head, sector, number bytes) each sector formatted during execution phase. other words, controller formats each sector, requests four bytes through either requests interrupts. This allows non-sequential sector interleaving. Table 4-29 shows some typical values programmable size. format command terminates when index hole detected second time, which point interrupt generated. Only first three status bytes result phase significant.
4.6.4 Write-Deleted-Data
This command same write-data command except that deleted-data mark written beginning data field instead normal data mark.
4.6.5 Read Track
This command similar read-data command except following: controller starts index hole reads sectors their physical order, their logical order. Even though controller reads sectors their physical order, still compares header bytes with data programmed command phase. exception this sector number. Internally, this one, then incremented each successive sector read. Whether programmed address field matches that read from
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Table 4-25A Length Various Sector Sizes Disk Types Sector Size (Dec) 1024 2048 4096 1024 2048 4096 8192 1024 2048 1024 2048 4096 1024 Sector Sector Code (Dec) (Hex) (Hex) 8-inch Drives (360 RPM, kb/s) 5.25-inch Drives (300 RPM, kb/s) 3.5-inch Drives (300 RPM, kb/s) Format* (Hex)
Mode
Table 4-25B Format Table PC-Compatible Diskette Media Media Type 1.44 2.88 Sector Size (Dec) Sector Code (Hex) (Hex) Sector (Hex) Format* (Hex)
Format length used only format command.
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M512x Mega Controller with
Index pulse Gap0 Sync Gap1 Sync Perpendicular format
Gap2 Sync
Data
Gap3 Prog GAP4 mable
format
Gap0 Sync Gap1 Sync
Gap2 Sync
Data
Gap3 Prog GAP4 mable
Index address field
Address field Repeated each sector
Data field
format
Gap1 Sync
Gap2 Sync
Data
Gap3 Prog GAP4 mabl
Figure IBM, Perpendicular, Formats Supported Format Command
4.6.8 Scan Commands
scan commands allow data read from disk compared against data sent from CPU. There three scan commands choose from: Scan equal Scan less than equal Scan greater than equal Disk data data Disk data data Disk data data Table 4-30 Scan Command Termination Values Conditions Disk Disk Disk Disk Disk Disk Disk Disk
Status Register Command Scan equal Scan equal Scan high equal
Each sector interpreted with most significant byte first. wildcard mode enabled from mode command, from either disk used "don't care" byte that always matches equal. each sector read, desired condition been met, next sector read. next sector defined current sector number plus sector step-size specified. scan command continues until scan condition been met, track sector number been reached, asserted. set, sectors with deleted data marks ignored. sectors read skipped, command terminates with (scan equal hit). Table 4-30 shows result phase command.
4.6.9 Seek
There ways move disk drive head desired track number. first method enable implied seek mode. This way, each individual read write command automatically moves head track specified command.
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second method using seek command. During execution phase seek command, track number seek compared with present track number, step pulse produced move head track closer desired track number. This repeated rate specified specify command until head reaches correct track. this point, interrupt generated sense-interrupt command required clear interrupt. During execution phase seek command, only indication software that seek command progress bits (drive busy) main status register. main status register (command progress) set. While internal micro-engine capable multiple seeks more drives same time since drives selected drive-control register software, software should ensure that only drive performs seek command time. other command except sense-interrupt command issued while seek command progress. extended track range mode enabled, write fourth byte command phase indicate four most significant bits desired track number. Otherwise, write only three bytes.
4.6.12 Sense-Interrupt Status
interrupt generated controller when following conditions occur:
Upon entering result phase Read-data command Read-deleted-data command Write-data command Write-deleted-data command Read-a-track command Read-ID command Format command Scan commands During data transfers execution phase while non-DMA mode Internal ready signal changes state (only occurs immediately after hardware software reset). Seek recalibrate command termination
4.6.10 Relative Seek
Relative Seek command steps selected drive given number steps. This command will step read/write head incremental number tracks from current track number, contrasting step desired track number Seek command. Relative Seek parameters defined follows: DIR: Read/Write Head Step Direction Control 0=Step Head Out, 1=Step Head RTN: Relative Track Number. This value will determine many incremental tracks step head from current track number.
interrupt generated reasons above occurs during normal command operations easily recognized CPU. During execution phase nonDMA mode, (execution mode) Upon entering result phase, this Reasons require sense interrupt status command. interrupt cleared reading writing information data register. Interrupts caused reasons identified with sense interrupt status command. This command resets interrupt when command byte written. Table 4-31 shows identify cause interrupt using bits ST0.
4.6.11 Recalibrate
recalibrate command very similar seek command. used step drive head track zero. Step pulses produced until track zero signal from drive becomes true. track zero signal does before step pulses issued, error generated. extended track range mode enabled, error generated until 3,917 pulses issued. Recalibrations more than drive time should issued same reason explained seek command. other command except sense-interrupt command should issued while recalibrate command progress.
Issuing sense-interrupt status command without interrupt pending treated invalid command. extended track range mode enabled, third byte should read result phase which indicates four most significant bits present track number. Otherwise, only bytes should read.
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M512x Mega Controller with
4.6.13 Specify
specify command sets initial values each three internal timers. Table 4-32 shows timer programming values. head-load head-unload timers artifacts UPD765A. These timers determine delay from loading head until read write command started, unloading head sometime after command completed. Since M512x head-load signal software-controlled motor lines drive-control register, these timers only provide some delay from initialization command until actually started. Similar DP8474, extend these timers setting mode command. step-rate time defines time interval between adjacent step pulses during seek, implied-seek, recalibrate command. times stated Table 4-32 affected data rate. These values kb/s (250 Kb/s Mb/s (500 Kb/s FM). kb/s data rate (150 Kb/s FM), these values, multiply 1.6667, Kb/s (125 Kb/s double these values. choice non-DMA operation made non-DMA bit. When this non-DMA mode selected, when this mode selected. This command does generate interrupt.
Table 4-31 Status Register Termination Codes Interrupt Code Seek Cause Internal ready went true Normal seek termination Abnormal seek termination
Table 4-32 Step, Head, Load Unload Timer Definitions (500 kb/s MFM) Timer Step Rate Head Unload Head Load Mode Value Range 1~16 0~240 0~254 Mode Value Range 1~16 0~7680 0~4064 Unit
4.6.14 Sense Drive Status
This two-byte command obtains status disk drive. Status register returned result phase contains drive status. This command does generate interrupt.
4.6.16 Version
Version command used determine floppy controller being used. result phase uniquely identifies floppy controller version. returns value order compatible with 82077. older version compatible with NEC765 controller, value (invalid command) will return.
4.6.15 Verify
VERIFY command used verify data stored disk. This command acts exactly like READ DATA command except that data transferred host. Data read from disk computed checked against previously stored value.
4.6.17 Dumpreg
DUMPREG command designed support system run-time diagnostics application software development debug. command returns important information regarding status many programmed field FDC. This used verify values initialized FDC.
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4.6.18 Configure
Configure command controls some operation modes controller. should issued during initialization after power These bits their default values after hardware reset. EIS: Enable implied seek. When EIS=1, will perform SEEK operation before executing read/write command. default value implied seek). EFIFO: Enable FIFO. When EFIFO=1, FIFO disabled (NEC765A compatible mode). This means data transferred byte byte basis. default value (FIFO disable). POLL: Disable Polling. When POLL=1, polling drives disabled. POLL defaults (polling enable). When enabled, single interrupt generated after reset. FIFOTHR: FIFO threshold execution phase read/write command. This programmable from bytes. FIFOTHR defaults selects byte selects bytes. PRETRK: Precompensation start track number. Programmable from track 255. PRETRK defaults track selects track selects track 255.
4.6.20 Lock
Lock command allows user full control FIFO parameters after software reset. LOCK then EFIFO, FIFOTHR PRETRK bits Configure command affected software reset. After command byte written, result byte must read before continuing next command.
4.6.21 Invalid
invalid command (illegal Opcode byte command phase) received controller, controller responds with Result Phase. controller does generate interrupt during this condition. system reads from indicating invalid command received.
4.6.22 Perpendicular Mode
Perpendicular Mode command designed support Perpendicular Recording disk drives (4Mbytes unformatted capacity). Perpendicular Mode command configures each four logical drives perpendicular conventional disk drive. Configuration four logical disk drives done D3-D0 bits, with control bits. This command should issued during initialization floppy controller. written sets drive conventional mode, sets drive perpendicular mode. Also, offers additional control. When OW=1, changing values D3D0 enabled. When OW=0, internal values D3-D0 unaffected, regardless what written D3-D0. function bits must also qualified setting both they overrides whatever programmed bits. Table below indicates operation based values D3-D0 unaffected software reset, both cleared after software reset. hardware reset resets bits zero.
4.6.19. Powerdown Mode
Powerdown mode command allows automatic power management. command extend battery life portable applications. enable auto powerdown command issued during BIOS power self test (POST). DLY: Minimum powerup timer. This active only enabled. this assigns 10msec timer, assigns 0.5sec timer. timer will re-initialized after command execution finished (idle state) start countdown. When timer expired, will enter powerdown state automatically. APD: Enable auto powerdown. When auto powerdown enabled.
Table Effects bits
Mode GAP2 Length during Format Conventional Bytes Perpendicular Bytes (500kbps) Reserved Bytes (Conventional) Perpendicular Bytes (1Mbps) Portion GAP2 re-written Write Data Command Bytes Bytes Bytes Bytes
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M512x Mega Controller with
Parallel Port Mode
this mode, floppy disk control signals available parallel port pins. When this mode selected, parallel port available. There four modes operation. These modes selected index 0xF1 configuration space. signals multiplexed onto Parallel port pins shown table below. 0xF1[1:0] Parallel port function Printer Printer FDC(drive FDC(drive
signals multiplexed onto Parallel port pins shown table below. Conn Chip mode STBJ ACKJ BUSY SLCT AFDJ ERRJ INITJ SLINJ Type mode DS0J INDEXJ TRK0J RDATAJ DSKCHGJ MTR0J DS1J MTR1J WDATAJ WGATEJ DENSEL HDSELJ DIRJ STEPJ direction
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Section Serial Port Registers
Each serial ports function data input/output interface microcomputer system. system software determines functional configuration UARTs tri-state 8-bit bi-directional data bus. UARTs completely independent perform serialto-parallel conversion data characters received from peripheral device modem, parallel-to-serial conversion data characters received from CPU. read complete status UARTs time during functional operation. Status information reported includes type condition transfer operations performed UART, well error conditions (parity, overrun, framing, break interrupt). UARTs have programmable baud rate generator capable dividing timing reference clock input divisors (216 producing clock driving internal transmitter logic. Provisions also included this clock drive receiver logic. UARTs have complete modem-control capability processor-interrupt system. Interrupts programmed user's requirements, minimizing computing required handle communications link.
Table lists register addresses (AEN equal zero). DLAB divisor latch access bit. Table Register Address Base Serial Port Registers Access (AEN=0) DLAB Abbreviation Register Name Access
Transmit Holding Register Receiver Buffer Register Divisor Latch Divisor Latch Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register
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M512x Mega Controller with
Table
DLAB=0
Register Summary Each UART Channel
Receiver Buffer Register (Read only) Transmitter Holding Register (Write only) Interrupt Enable Register Data (note
Data
Data
Data
Data
Data
Data
Data
DLAB=0
Data
Data
Data
Data
Data
Data
Data
Data
DLAB=0
Enable received data available interrupt (ERDAI) interrupt pending FIFO enable
Interrupt Ident. Register (Read only) FIFO control register (write only) Line control register
Enable Transmitter Holding Register Empty Interrupt (ETHREI) Interrupt
Enable Receiver Line Status Interrupt (ELSI) Interrupt
Enable Modem Status Interrupt (EMSI)
FIFO enable
FIFO enable
RCVR FIFO Reset
Xmit FIFO reset
reserved
reserved
reserved
RCVR Trigger (LSB) Break
RCVR Trigger (MSB) Divisor Latch Access (DLAB)
Word length select (WLS0) Data Terminal ready (DTR) Data ready (DR)
Word Length Select (WLS1) Request send (RTS)
Number Stop Bits (STB)
Parity Enable (PEN)
Even Parity Select (EPS) Loop
Stick Parity
Modem control register Line status register
(Note
Enable (Note Framing Error (FE)
Overrun error (OE)
Parity Error (PE)
Break Interrupt (BI) Clear Send (CTS)
Modem status register Scratch register (note Divisor latch (LS) Divisor latch (MS)
Delta Clear Send (DCTS)
Delta Data Ready (DDSR)
Trailing Edge ring indicator (TERI)
Delta Data Carrier Detect (DDCD)
Transmitte Holding Register (THRE) Data Ready (DSR)
Transmitte Empty (TEMT) note Ring Indicator (RI)
Error RCVR FIFO Data Carrier Detect (DCD)
DLAB=1 DLAB=1
Note
least significant bit. first serially transmitted received. When operating mode, this will time that transmitter shift register empty. This longer associated with When operating mode, this register available.
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M512x Mega Controller with
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Line Control Register (LCR)
system programmer uses this read/write register specify format asynchronous data communications exchange divisor latch access bit. Table Registers Function Divisor latch access (DLAB). access divisor latches baud generator alternate function register during read write operation. access other register. Break control bit. This causes break condition transmitted receiving UART. Serial output (SOUT) forced spacing logic Break disabled This acts only SOUT effect transmitter logic. This enables alert terminal computer communications system. following sequence followed, erroneous extraneous characters transmitted because break Load character response THRE. break after next THRE. Wait transmitter idle, (TEMT clear break when normal transmission restored. During break, transmitter used character timer accurately establish break duration. Stick parity bit. When parity enabled, used conjunction with select, mark space parity. Enable stick parity Disable stick parity Parity select bit. Selects either even number transmitted/checked data word parity bit. number (parity logic mark parity) Even number (parity logic space parity) Parity enable bit. parity used produce even number when data bits parity added. parity generated (transmit data) checked (received data) between last data stop serial data. Parity generated/checked Parity generated/checked Specifies number stop bits transmitted with each serial character. receiver checks first stop only, regardless number stop bits selected. stop stop bits, when 5-bit data length selected stop bits, when 8-bit data length selected Specify number data bits (data length) each transmitted received serial character. following values: bits bits bits bits
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M512x Mega Controller with
Programmable Baud Generator
UART contains independently programmable baud generators. 24-MHz crystal oscillator frequency input divided resulting frequency 1.8462-MHz. This sent each baud generator divided divisor associated UART. output frequency baud generator baud rate, [divisor (frequency input) (baud rate 16)]. output each baud generator drives transmitter receiver sections associated serial channel. 8-bit latches channel store divisor 16-bit binary format. These divisor latches must loaded during initialization ensure proper operation baud generator. Upon loading either divisor latches, 16-bit baud counter loaded. Table provides decimal divisors with crystal frequencies 24-MHz. oscillator input chip should always 24-MHz ensure that timing accurate that UART divisors compatible with existing software. Using divisor zero recommended.
Line Status Register (LSR)
This register provides status information concerning data transfer. intended read Table Line Status Register Function Definition Function 16450 mode, this FIFO, LSR7 when there least parity error, framing error break indication FIFO LSR7 cleared when reads LSR, there subsequent errors FIFO. This changes function depending whether device operating XT/AT mode. When mode, this transmitter empty (TEMT) indicator. whenever transmitter holding register (THR) transmitter shift register (TSR) both empty. reset whenever either contains data character. Transmitter holding register empty (THRE) indicator. indicates that UART ready accept character transmission. also causes UART issue interrupt when THRE interrupt enable high. when character transferred from THRE into TSR. reset whenever loads THRE. Break interrupt (BI) indicator. when received data input held spacing (logic state longer than full word transmission time (that total time start data bits parity stop bits). reset whenever reads contents LSR. Restarting after break received requires logical least 1/2-bit time. Framing error (FE) indicator. This indicates that received character have valid stop bit. whenever stop following last data parity logic (spacing level). indicator reset whenever reads contents LSR. UART tries resynchronize after framing error. this, assumes that next start bit, samples this start twice then takes data. Parity error (PE) indicator. This indicates that received data character does have correct even parity, selected even-parity-select bit. upon detection parity error reset whenever reads contents LSR. Overrun error (OE) indicator. indicates that data read before next data transferred into RBR, thereby destroying previous data. upon detection overrun condition reset whenever reads contents LSR. Receive data ready (DR) indicator. whenever complete incoming character been received transferred into RBR. reset reading data RBR. operations only. Writing this register recommended this operation only used factory testing.
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M512x Mega Controller with
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Table Desired baud rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 230400 460800
Baud rates using 1.8462 Clock MHz/13) Divisor used generate clock 2304 1536 1047 32770 32769 0.001 0.004 0.005 0.030 0.16 0.16 0.16 0.16
Interrupt Identification Register (IIR)
This register keeps record four interrupts prioritized UART reduce software overhead during data transfers. four levels interrupt conditions order priority are: receiver-line-status, received-data-ready, modem-status. When accesses IIR, UART freezes interrupts indicates highest priority pending interrupt CPU. While this access occurring, UART records interrupts, does change current indication until access complete. Table Interrupt Identification Register Function These bits when FIFO control register equals Always '0'. non-FIFO mode, this logic FIFO mode, this along with when timeout interrupt pending. Identifies highest interrupt pending. Used interrupt environment indicate whether interrupt condition pending. yes, contents used pointer appropriate interrupt service routine. Interrupt pending interrupt pending
Note refers Error Difference between desired actual, except where shown otherwise,
07-02-1997 Document Number: 512xDS02.doc Acer Labs: Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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-Preliminary, Confidential, Proprietary-
M512x Mega Controller with
Table FIFO mode only
Interrupt Control Table Interrupt register D2-D1-D0
Interrupt Reset Functions Priority level highest Interrupt type None Receiver line status Interrupt source None Overrun error, Parity error, Framing error Break interrupt Received data available Interrupt Reset control Reading register
line
status
second
second
Received data available Character timeout Indication
third
fourth
Transmitter holding register empty MODEM status
characters have been removed from input RCVR FIFO during last char times there least char during this time. Transmitter Holding Register Empty
Read receiver buffer FIFO drops below trigger level Reading Receiver Buffer Register
Reading Register writing transmitter holding register Reading Modem status register
Clear send data ready
Interrupt Enable Register (IER)
This register enables four types UART interrupts. Each interrupt individually activate UR2IRQA UR1IRQA output signal. Resetting bits disables interrupt system. Similarly, setting bits this register enables selected interrupts. Disabling interrupt prevents from being indicated active from activating interrupt output signal. other system functions operate their normal manner, including setting line status modem status registers. Table Interrupt Enable Register Function Enables received-data-available interrupt Enables THRE interrupt Enables receiver-line-status interrupt Enables modem-status interrupt Always Writing FCR0 enables both XMIT RCVR FIFOs. Resetting FCR0 will clear bytes both FIFOs. When changing from FIFO mode NS16450 mode vice versa, data automatically cleared from FIFOs. This must when other bits written they will programmed. Writing FCR1 clears bytes RCVR FIFO resets counter logic shift register cleared. that written this position selfclearing. Writing FCR2 clears bytes XMIT FIFO resets counter logic shift register cleared. that written this position selfclearing. Setting FCR3 will cause RXRDY TXRDY pins change from mode mode FCR0 FCR4 FCR5 reserved future use. FCR6 FCR7 used trigger level RCVR FIFO interrupt.
FIFO Control Register
This write only register same location (the read only register). This register used enable FIFOs, clear FIFOs, RCVR FIFO trigger level, select type signalling.
Page
07-02-1997 Document Number: 512xDS02.doc Acer Labs: Tung Hsing Street, Taipei 110, Taiwan, Tel: 886-(02) 762-8800 Fax: 762-6060
M512x Mega Controller with
-Preliminary, Confidential, Proprietary-
RCVR FIFO Trigger Level (Bytes)
Modem Control Register (MCR)
This register controls interface with modem data peripheral emulating modem). Table Modem Control Register Function logic This provides local loopback feature UART diagnostic testing. When following occurs: transmitter serial output (SOUT) marking state; receiver serial input (SIN) disconnected; output transmitter shift register looped back into receiver shift register input; four modem control inputs (DSRJ, CTSJ, RIJ, DCDJ) disconnected; DTRJ, RTSJ, OUT1, enable bits respectively. When operating mode, modem control output pins forced their high (inactive) states. diagnostic mode, data that transmitted immediately received. This feature allows processor verify transmit-andreceive data paths serial port. diagnostic mode, receiver transmitter interrupts fully operational. modem status interrupts also operational, interrupt's sources lower four bits instead four modem control inputs. Writing them causes interrupt. interrupts still controlled IER. This enables interrupt when set. local loopback mode, this controls MSR. This OUT1 bit. does have output associated with written read CPU. local loopback mode, this controls MSR. Controls RTSJ output. local loopback mode, this controls MSR. Controls DTRJ output. local loopback mode, this controls MSR. DTRJ output forced DTRJ output forced
07-02-1997 Document Number: 512xDS02.doc Acer Labs: Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
Page Fax: 762-6060
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M512x Mega Controller with
Modem Status Register (MSR)
This register gives current state control lines from modem CPU. bits whenever Table 5-10 Modem Status Register Function Complement DCDJ input. (loopback) this equivalent enable MCR. Complement input. (loopback) this equivalent OUT1 MCR. Complement DSRJ input. (loopback) this equivalent MCR. Complement CTSJ input. (loopback) this equivalent MCR. Delta data carrier detect (DDCD) indicates that DCDJ input chip changed state. Whenever modem status interrupt generated. Trailing edge ring indicator (TERI) detector indicates that input chip changed from high state. Delta data ready (DDSR) indicates that DSRJ input chip changed state since last time read CPU. Delta clear send (DCTS) indicates that CTSJ input chip changed state since last time read CPU. control input from modem changes state, when reads MSR.
Scratchpad Register (SCR)
8-bit read/write register does control UART way. intended scratchpad register used programmer hold data temporarily. programmed this mode. transfer signals will rout SIN1/SIN2 SOUT1/SOUT2. additional pins, IRRX IRTX, also provided.
5.10 Infrared Interface 5.10.1 Sharp-IR Mode
This mode supports bidirectional data communication with remote device using infrared radiation transmission medium. Sharp-IR uses Amplitude Shift (ASK) allows serial communication baud rates 38.4K Baud. format serial data similar UART data format, zero value start bit, followed data bits, optional parity bit, ending with least stop with binary value one. zero signalled sending 500KHz continuous pulse train infrared radiation. signalled absence infrared signal. device operation Sharp-IR mode similar operation UART. main difference that data transfer normally performed half duplex fashion, modem control status signals used. Selection this mode controlled mode bits UART' configuration space. Both UART1 UART2
5.10.2 IrDA Mode
This operation mode similar Sharp-IR. IrDA allows serial communication baud rates 115.2K Baud. data format same Sharp-IR mode except parity needed. zero signalled sending single infrared pulse. signalled sending pulse. width each pulse 3/16ths single time. device operation IrDA mode similar operation UART. main difference that data transfer normally performed half duplex fashion, modem control status signals used. Selection this mode controlled mode bits UART' configuration space. Both UART1 UART2 programmed this mode. transfer signals will rout SIN1/SIN2 SOUT1/SOUT2. additional pins, IRRX IRTX, also provided.
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07-02-1997 Document Number: 512xDS02.doc Acer Labs: Tung Hsing Street, Taipei 110, Taiwan, Tel: 886-(02) 762-8800 Fax: 762-6060
M512x Mega Controller with
-Preliminary, Confidential, Proprietary-
Section Keyboard Controller Real Time Clock Functional Description
Keyboard Interface M512x interface functionally compatible with M8042 style host interface. consists D0-D7 data bus; IORJ, IOWJ Status register, Input Data register, Output Data register. Table below shows interface decodes control signals. addition above signals, host interface includes keyboard mouse IRQ'
Keyboard Controller Universal Keyboard Controller uses M8042 microcontroller cord. This section concentrates M512x enhancements M8042.
KIRQ MIRQ GATE Reset
Address Address 0x70 (R/W) 0x71 (R/W) BLOCK FUNCTION Address Register (70H) Data Register (71H)
M8042
LS05 KDAT KCLK MCLK MDAT
Address 0x60
nIOW
nIOR
Block KDATA KDATA KDCTL
Function (Note Keyboard Data Write (C/D=0) (60h) Keyboard Data Read (60h) Keyboard Command Write (C/D=1) (64h) Keyboard Status Read (64h)
TST1 Keyboard Mouse Interface
0x64
KIRQ Keyboard MIRQ Mouse CIO14 alternate function, used Gate A20. used optionally reset.
KDCTL
Note These registers consist three separate 8-bit registers. Status, Data/Command write Data Read.
07-02-1997 Document Number: 512xDS02.doc Acer Labs: Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
Page Fax: 762-6060
-Preliminary, Confidential, Proprietary-
M512x Mega Controller with
Keyboard Data Write This write only register. When written, status status register cleared zero set. Keyboard Data Read This read only register. enabled ENABLE FLAGS" KIRQ output cleared flag status register cleared. enabled, KIRQ and/or AUXOBF1 must cleared software. Keyboard Command Write This write only register. When written, status status register set. Keyboard Status Read This read only register. Refer description Status Register more information.
Host-to-CPU Communication host system send both commands data Input Data register. differentiates between commands data reading value Status register. When interprets register contents command. When interprets register contents data. During host write operation, reset
KIRQ FLAGS" been executed one: flag gated onto KIRQ. KIRQ signal connected system interrupt signify that M512x written output data register DBB, zero, KIRQ forced low. powerup, after valid reset pulse been delivered device, KIRQ reset KIRQ normally reflects status DBB" ENFLAGS been executed: KIRQ controlled writing P24. Writing zero forces KIRQ low, high forces KIRQ high. MIRQ FLAGS" been executed one: inverted gated onto MIRQ. MIRQ signal connected system interrupt signify that M512x read register. ENFLAGS been executed MIRQ controlled P25. Writing zero forces MIRQ low, high forces MIRQ high. (MIRQ normally selected IRQ12 mouse support.) Gate general purpose routed Common CIO14 software controlled Gate user defined output.
CPU-to-Host Communication heart M512x write Output Data register register DBB. write this register automatically sets (OBF) Status register. table below
Host Interface Flags M8042 Instruction FLAG OBF, and, enabled, KIRQ output signal goes high
Page
07-02-1997 Document Number: 512xDS02.doc Acer Labs: Tung Hsing Street, Taipei 110, Taiwan, Tel: 886-(02) 762-8800 Fax: 762-6060
M512x Mega Controller with
-Preliminary, Confidential, Proprietary-
External Keyboard Mouse Interface Industry-standard PC-AT compatible keyboards employ two-wire, bi-directional interface data transmission. Several sources also supply PS/2 mouse products that employ same type interface. facilitate system expansion, M512x provides four signal pins that used implement this interface directly external keyboard mouse. M512x four high-drive, open-drain output (1), bidirectional port pins that used external serial interfaces, such external keyboard PS/2-type mouse interfaces. They KCLK, KDAT, MCLK MDAT.
Hard Power Down Mode This mode entered executing STOP instruction. oscillator stopped disabling oscillator driver cell. When either RESET driven active data byte written DBBIN register master CPU, mode will exited above). However, oscillator cell will require initialization time, either RESET must held active sufficient time allow oscillator stabilize. Program execution will resume above.
Interrupts M512x provides M8042 interrupts. Timer/Counter Overflow.
inverted output KCLK. KCLK connected TESTO. inverted output KDAT. KDAT connected P70. inverted output MCLK. MCLK connected TEST1. inverted output MDAT. MDAT connected P11. NOTE External pull-ups required.
Memory Configurations M512x provides on-chip bytes on-chip RAM.
Register Definitions Keyboard Power Management Host Data Register keyboard provides support power saving modes: soft power down mode hard power down mode. soft power down mode, clock stopped timer/counter interrupts still active. hard power down mode, clock M8042 stopped. Efforts made reduce power wherever possible. Input Data register and, Output Data register, each bits wide. write this register will load Keyboard Data Read Buffer, flag KIRQ output enabled. read this register will read data from Keyboa
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