24-Bit Variable Bandwidth Converter Chipset CMOS Description

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24-Bit Variable Bandwidth Converter Chipset CMOS Description

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CS5320/21/22
24-Bit Variable Bandwidth Converter Chipset
CMOS
Description
CK5320 CK5321 Chipsets function unique converter intended very high resolution measurement signals below 1500 CK5320 Chipset cost effective commercial grade solution applications which require high dynamic range converter. chipsets perform sampling, conversion, anti-alias filtering. CS5320 CS5321 Delta-Sigma modulation produce highly accurate conversions. modulator oversamples, virtually eliminating need external analog anti-alias filters. CS5322 linearphase digital filter decimates output seven selectable update periods: 0.25 milliseconds. Data output from digital filter 24-bit serial format. ORDERING INFORMATION* Chip Sets Kits CS5320-KL CS5322-KL CK5320-KL1 CS5321-BL CS5322-KL CK5321-KL1 CS5321-BL CS5322-BL CK5321-BL1
Converter Chipset Dynamic Range
Bandwidth Bandwidth
Delta-Sigma
Architecture
Fourth-Order Modulator Variable Oversampling: 4096X Internal Track-and-Hold Amplifier
CS5321
Signal-to-Distortion: Clock Jitter Tolerant Architecture Input Voltage Range: +4.5 Flexible Filter Chip
Hardware Software Selectable Options Seven Selectable Filter Corners Frequencies: 102, 205, 411, 1650
Power Dissipation: <100
Refer Table
CS5320/21
Vdd1 Vss1 Vdd2 Vss2 LPWR OFST MSYNC AINR AIN+ AINMDATA VREF+ VREFAGND DGND DGND CSEL TDATA PWDN USEOR DGND Analog Modulator MFLG MCLK MDATA Digital Filter RESET SYNC
CS5322
CLKIN RSEL SCLK ERROR DRDY ORCAL DECA DECB DECC
Preliminary Product Information
P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved)
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TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS CS5320 CS5321 ANALOG CHARACTERISTICS CS5320 CS5321 SWITCHING CHARACTERISTICS CS5320 CS5321 DIGITAL CHARACTERISTICS CS5320 CS5321 RECOMMENDED OPERATION CONDITIONS CS5320 CS5321 ABSOLUTE MAXIMUM RATINGS CS5322 FILTER CHARACTERISTICS CS5322 POWER SUPPLY CS5322 SWITCHING CHARACTERISTICS CS5322 DIGITAL CHARACTERISTICS CS5322 RECOMMENDED OPERATION CONDITIONS CS5322 ABSOLUTE MAXIMUM RATINGS GENERAL DESCRIPTION 2.1. Analog Input 2.2. OFST Pin. 2.3. Input Range Overrange Conditions 2.4. Voltage Reference 2.5. Clock Source 2.6. Power Mode 2.7. Digital Interface Data Format. 2.8. Performance 2.9. Power Supply Considerations. 2.10. Power Supply Rejection Ratio 2.11. RESET Operation 2.12. Power-down Operation 2.13. SYNC Operation 2.14. Serial Read Operation 2.15. Serial Write Operation 2.16. Offset Calibration Operation 2.17. Status Bits 2.18. Board Layout Considerations CS5320/21 DESCRIPTIONS Power Supplies Analog Inputs Digital Inputs Digital Outputs
Contacting Cirrus Logic Support
complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site
Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Items from Cirrus Logic website disk printed user. However, part printout electronic files copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
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CS5322 DESCRIPTIONS Power Supplies Digital Outputs Digital Inputs ORDERING INFORMATION PARAMETER DEFINITIONS. PACKAGE DIMENSIONS
LIST FIGURES
Figure Rise Fall Times Figure CS5320 CS5321 Interface Timing, HBR=1 Figure CS5322 Filter Response Figure CS5322 Digital Filter Passband Ripple 62.5 Figure CS5322 Digital Filter Passband Ripple Figure CS5322 Digital Filter Passband Ripple Figure CS5322 Digital Filter Passband Ripple Figure CS5322 Digital Filter Passband Ripple 1000 Figure CS5322 Digital Filter Passband Ripple 2000 Figure CS5322 Digital Filter Passband Ripple 4000 Figure CS5322 Impulse Response 62.5 Figure CS5322 Impulse Response 1000 Figure CS5322 Serial Port Timing Figure TDATA Setup/Hold Timing Figure DRDY Timing Figure RESET Timing Figure CS5320/21/CS5322 Interface Timing Figure CS5320/21 Block Diagram Figure CS5322 Block Diagram Figure System Connection Diagram Figure Voltage Reference with filter options Figure 1024 Point Plot with Input, Input, averages Figure 1024 Point Plot with Full Scale Input, Input, averages Figure 1024 Point Plot with Full Scale Input, Input, averages
LIST TABLES
Table Table Table Table Table Output Coding CS5320/21 CS5322 Combination Configuration Data Bits Status Data (from Pin) Bandwidth Selection: Truth Table Detailed Ordering Information
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CHARACTERISTICS SPECIFICATIONS
CS5320 CS5321 ANALOG CHARACTERISTICS (See Note Vss1, Vss2 -5V;
Vdd1, Vdd2 +5V; AGND DGND LPWR MCLK 1.024 MHz; Device connected shown Figure CS5322 used filtering; Logic VD+, Logic unless otherwise specified.) CS5320 Parameter* Symbol TCFS VZSE TCZSE ±100 ±100
ppm/°C
CS5321 Unit
Dynamic Performance Dynamic Range OFST
(Note 4000 2000 1000 62.5 4000 2000 1000 62.5 (Note (Note (Note (Note 5,6) (Note (Note (Note (Note 5,6)
OFST
Signal-to-Distortion
Intermodulation Distortion Accuracy Full Scale Error Full Scale Drift Offset Offset after Calibration Offset Calibration Range Offset Drift
%F.S. µV/°C
Notes: CS5320-KL CS5322-KL guaranteed from CS5322-BL guaranteed from -40o +85o CS5321-BL guaranteed from -55o +85o CS5322 output word rate. Refer "CS5322 FILTER CHARACTERISTICS" page details Filter. Characterized with full scale input signal Characterized with input signals each down from full scale with 1000 Specification parameter over specified temperature range CS5320/21 device only (VREF +4.5 does include effects external components; OFST Drift specifications guaranteed design and/or characterization. offset after calibration specification applies effective offset voltage ±4.5 volt input CS5320/21 modulator, relative output digital codes from CS5322 after ORCAL USEOR have been made active. CS5322 offset calibration performed digitally includes full scale (±4.5 volts into CS5320/21). Calibration offsets greater than full scale will begin subtract from dynamic range. DS454PP1
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CS5320 CS5321 ANALOG CHARACTERISTICS (Continued)
CS5320/21 Parameter* Symbol (Note (Note (Note (Note LPWR Positive Supplies Negative Supplies LPWR Positive Supplies Negative Supplies kHz) (Note IOVR -4.5 1500 +4.5 Unit %F.S.
Input Characteristics Input Signal Frequencies Input Voltage Range Input Overrange Voltage Power Supplies Power Supply Currents
Power Consumption
(Note Normal Operating Mode (Note12) Lower Power Mode (Note
Power Down Power Supply Rejection
Notes: upper bandwidth limit determined CS5322 digital filter. This input voltage range configuration shown Figure System Connection Diagram, applies signal from Refer CS5322 Filter Characteristics values outputs unloaded. logic inputs forced respectively. LPWR CS5321 power dissipation reduced under following conditions: LPWR=1; MCLK=512kHz, HBR=1 LWPR=1; MCLK=1.024MHz, HBR=0 Characterized with mVp-p sine wave applied separately each supply. Refer Parameter Definitions (immediately following descriptions this data sheet). Specifications subject change without notice.
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CS5320 CS5321 SWITCHING CHARACTERISTICS (See Note Vdd1, Vdd2
Vss1, Vss2 Inputs: Logic Logic (Note 15)) Parameter MCLK Frequency MCLK Duty Cycle MCLK Jitter (In-band) Rise Times: Fall Times: Digital Input Digital Output Digital Input Digital Output (Note (Note trisein triseout tfallin tfallout tmss tmsh tmfh tmdv (Note Symbol 0.250 1.024 Units
MSYNC Setup Time MCLK rising MSYNC Hold Time after MCLK rising MCLK rising Valid MFLG MCLK rising Valid MDATA
Notes: Guaranteed design, characterization, test. MCLK removed, modulator will enter power down mode. Excludes MCLK input. MCLK should driven with signal having rise fall times faster.
risein
fallin
riseout
fallout
Figure Rise Fall Times
MCLK
MSYNC MDATA VALID DATA VALID DATA
MFLG
Figure CS5320 CS5321 Interface Timing, HBR=1
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CS5320 CS5321 DIGITAL CHARACTERISTICS (See Note Vdd1 Vdd2
5.0V measurements performed under static conditions) Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Output Voltage IOUT Low-Level Output Voltage IOUT Input Leakage Current Digital Input Capacitance Digital Output Capacitance (Note (Note (Note (Note Symbol ILKG COUT (Vdd)-0.6 (Vdd)-0.3
Units
Notes: Device intended driven with CMOS logic levels. Device intended interfaced CMOS logic. Resistive loads recommended these pins.
CS5320 CS5321 RECOMMENDED OPERATION CONDITIONS (Voltages with
respect Note Parameter Supply: Ambient Operating Temperature Symbol Positive Vdd1,Vdd2 Negative Vss1,Vss2 4.75 -4.75 -5.0 5.25 -5.25 Units
Notes: maximum voltage differential between Positive Supply CS5320/21 Positive Digital Supply CS5322 must less than 0.25V.
CS5320 CS5321 ABSOLUTE MAXIMUM RATINGS (Voltages with respect
Parameter Supply: Input Current, Except Supplies Output Current Total Power (all supplies outputs) Digital Input Voltage Storage Temperature Positive Negative (Note Symbol Vdd1,Vdd2 Vss1,Vss2 Iout VIND Tstg -0.3 +0.3 -0.3 -6.0 (Vdd)+0.3 Units
Notes: Transient currents will cause latch *WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
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CS5322 FILTER CHARACTERISTICS (See Note 5.0V;
CLKIN 1.024 MHz; transfer function shown Figure unless otherwise specified.) Output Word Rate (Hz) 4000 2000 1000 62.5 Passband (Hz) 1500 187.5 93.8 46.9 23.4 Passband Flatness (dB) 0.04 0.08 -3dB Freq. Stopband (Hz) (Hz) (Note 1652.5 824.3 411.9 205.9 102.9 51.5 25.7 2000 1000 62.5 31.25 Group Delay (ms) 7.25 14.5
Notes: -130 Output Word Rates.
-130
Figure CS5322 Filter Response
Figure CS5322 Digital Filter Passband Ripple 62.5
Figure CS5322 Digital Filter Passband Ripple
Figure CS5322 Digital Filter Passband Ripple
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Figure CS5322 Digital Filter Passband Ripple
Figure CS5322 Digital Filter Passband Ripple 1000
Figure CS5322 Digital Filter Passband Ripple 2000
-5,206,250
-5,212,500
Figure CS5322 Digital Filter Passband Ripple 4000
-5,206,250 -5,208,328 -5,212,500
-5,218,750 Digital Output Code -5,225,000 -5,231,250 -5,240,723 -5,237,500
-5,243,750
Digital Output Code
-5,218,750 -5,225,000
-5,231,250
-5,237,500
-5,243,750
-5,250,000
-5,250,000
Time Output Words)
Time Output Words)
Figure CS5322 Impulse Response, 62.5
Figure CS5322 Impulse Response, 1000
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CS5322 POWER SUPPLY (See Note CLKIN 1.024 MHz)
CS5322-K Parameter Power Supply Current: Power Dissipation: (Note (Note PWDN PWDN High CS5322-B Unit
CS5322 SWITCHING CHARACTERISTICS (See Note DGND
Inputs: Logic Logic VD+; (Note Parameter CLKIN Frequency CLKIN Duty Cycle Rise Times: Fall Times: Digital Input Digital Output Digital Input Digital Output trise tfall Symbol 0.512 1.024 Units
Serial Port Read Timing
DRDY Data Valid RSEL Setup Time before Data Valid Read Setup before Active Read Active Data Valid SCLK rising SCLK Pulse Width High SCLK Pulse Width SCLK Period SCLK falling DRDY falling High Output Hi-Z Read Hold Time after Inactive Read Select Setup SCLK falling tddv trss trsc trdv trdd trph trpl trsp trst trch trhc trds twsc twpl twph twsp twws twds twwh twhc twdh
Serial Port Write Timing
Write Setup Before Active SCLK Pulse Width SCLK Pulse Width High SCLK Period Write Setup Time First SCLK falling Data Setup Time First SCLK falling Write Select Hold Time after SCLK falling Write Hold Time after Inactive Data Hold Time after SCLK falling Guaranteed design, characterization and/or test. DS454PP1
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RSEL
DRDY
Hi-Z MSB-1 SCLK
Serial Port Read Timing (R/W RSEL DRDY Does toggle reading status, RSEL
LSB+1 Hi-Z
SCLK MSB-1
Serial Port Write Timing Figure CS5322 Serial Port Timing
LSB+1
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CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter Test Data (TDATA) Timing SYNC Setup Time CLKIN rising SYNC Hold Time after CLKIN rising TDATA Setup Time CLKIN rising after SYNC TDATA Hold Time after CLKIN rising ORCAL Setup Time CLKIN rising ORCAL Hold Time after CLKIN rising DRDY Timing CLKIN rising DRDY falling CLKIN falling DRDY rising CLKIN rising ERROR change RESET Timing RESET Setup Time CLKIN rising RESET Hold Time after CLKIN rising SYNC Setup Time CLKIN rising SYNC Hold Time after CLKIN rising Symbol ttds ttdh Units
CLKIN
SYNC
ORCAL
LSYNC* TDATA VALID VALID
FILTER SAMPLES DATA
Figure TDATA Setup/Hold Timing
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CLKIN
SYNC
LSYNC* DRDY ERROR *Note: overwrite case, DRDY will remain high.
Figure DRDY Timing
CLKIN
RESET
SYNC
Figure RESET Timing
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CS5322 SWITCHING CHARACTERISTICS (continued)
Parameter MCLK Frequency MCLK Duty Cycle Rise Times: Fall Times: Digital Input Digital Output Digital Input Digital Output (Note (Note trise tfall tmss tmsh (Note tmsd (Note Symbol 0.512 1.024 Units
SYNC Setup Time CLKIN rising SYNC Hold Time after CLKIN rising CLKIN edge MCLK edge MCLK rising Valid MDATA MSYNC Delay from MCLK rising
Notes: MCLK removed, modulator will enter power down mode. Excludes MCLK input. MCLK should driven with signal having rise fall times faster. Only rising edge MSYNC relative MCLK used synchronize device. MSYNC return time long remains high least MCLK cycle.
CLKIN
SYNC
LSYNC*
MCLK
MSYNC MDATA FILTER SAMPLES DATA
VALID DATA VALID DATA
MFLG
Internal timing signal generated CS5322
Figure CS5320/21/CS5322 Interface Timing
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CS5322 DIGITAL CHARACTERISTICS (See Note 5.0V
measurements performed under static conditions) Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Input Threshold Low-Level Input Threshold High-Level Output Voltage IOUT -40µA Low-Level Output Voltage IOUT +1.6 Input Leakage Current Digital Input Capacitance Digital Output Capacitance Three-State Leakage Current (Note (Note (Note (Note ILKG COUT Symbol (VD+)-0.3 (VD+)-1.0 (VD+)-0.6 Units
pins except MFLG,
Notes: Device intended driven with CMOS logic levels. Device intended interfaced CMOS logic. Resistive loads recommended these pins.
CS5322 RECOMMENDED OPERATION CONDITIONS
Parameter Supply: Positive Negative Ambient Operating Temperature (Note VDTA Symbol
(Voltages with respect -5.0 5.25 -5.25 Units
4.75 -4.75
Notes: maximum voltage differential between Positive Supply CS5320/21 Positive Digital Supply CS5322 must less than 0.25V.
CS5322 ABSOLUTE MAXIMUM RATINGS (Voltages with respect
Parameter Supply: Positive Negative Input Current, Except Supplies Digital Input Voltage Storage Temperature (Note (Note VDIin VIND Tstg -0.3 -0.3 (VD+)+0.3 -6.0 (VD+)+0.3 Symbol Units
Notes: Transient currents will cause latch *WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
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GENERAL DESCRIPTION
CS5320 CS5321 fourth-order CMOS monolithic analog modulators designed specifically very high resolution measurement signals between 1500 Configuring CS5320 CS5321 with CS5322 filter results high resolution converter system that performs sampling conversion with dynamic range exceeding CS5320 CS5321 fourth-order oversampling architecture achieve high resolution conversion. modulator consists 1-bit converter embedded negative feedback loop. modulator provides oversampled serial stream kbits second (HBR=1) kbits second (HBR=0) operating with clock rate 1.024 MHz. Figure illustrates CS5320/CS5321 Block Diagram. CS5322 monolithic digital Finite Impulse Response (FIR) filter with programmable decimation. CS5322 CS5320/CS5321 intended used together form unique high dynamic range chipset. CS5322 provides digital anti-alias filter CS5320/CS5321 modulator output. CS5322 consists multistage filter, four registers (status, data, offset, configuration), flexible serial input output port, 2-channel input data multiplexer that selects data from CS5320/CS5321 (MDATA) user test data (TDATA). CS5322 decimates (64x 4096x) output seven selectable up-date periods: 0.25 milliseconds. Data output from digital filter 24-bit serial format. Figure illustrates CS5322 Block Diagram.
Vdd1
Vss1
AGND
Vdd2
Vss2
DGND
Digital Osc. Detect AINR AIN+ AINControl
LPWR OFST MFLG
Clock Generation
MCLK MSYNC MDATA
MDATA VREF+ VREF-
Figure CS5320/21 Block Diagram
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CSEL PWDN ORCAL USEOR DECC DECB DECA SCLK CLKIN RESET SYNC MFLG DRDY ERROR MSYNC MCLK
STATUS
TDATA
MDATA
CONFIG CONFIG
DATA
FIR1
FIR2
CONTROL
FIR3
DATA
SELECT
SELECT
RSEL
Figure CS5322 Block Diagram
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Analog Input
CS5320 CS5321 modulators switched capacitor architecture signal voltage reference inputs. signal input uses three pins; AINR, AIN+, AIN-. AIN- acts return AINR AIN+ pins. AINR switched capacitor "rough charge" input AIN+ pin. input impedance rough charge (AINR) 1/fC where times modulator sampling clock rate internal sampling capacitor (about pF). Using 1.024 master clock (HBR yields input impedance about 1/(512 kHz)X(40 about Internal chip rough charge input pre-charges sampling capacitor used AIN+ input, therefore effective input impedance AIN+ orders magnitude above impedance seen AINR pin. analog input structure inside VREF+ very similar AINR includes additional circuitry whose operating current change over temperature from device device. Therefore, gain accuracy important, VREF+ should driven from source impedance. current demand VREF+ will produce voltage drop approximately across source resistor Figure Figure Option with MCLK 1.024 MHz, temperature 25°C. When CS5320/21 modulator operated with reference will accept input signal, modulator loop stability adversely affected high frequency out-of-band signals. Therefore, input signals must band-limited input filter. corner input filter must equal modulator sampling clock divided modulator sampling clock MCLK/4 when MCLK/8 when With MCLK 1.024 MHz, modulator sampling clock which requires input filter with corner kHz. bandlimiting accomplished amplifier stage ahead CS5320/21 modulator with input filter AIN+ AINR input pins. filter AIN+ AINR pins recommended reduce "charge kick" that driving amplifier sees switched capacitor sampling performed. Figure illustrates CS5320/21 CS5322 system connections. input components AINR AIN+ should identical values optimum performance. choosing components capacitor should minimum (C0G dielectric ceramic preferred). minimum board space, components AINR input removed, this will force driving amplifier source full dynamic charging current AINR input. This increase distortion driving amplifier reduce system performance. choosing filter components, increasing minimizing preferred. Increasing reduces instantaneous voltage change pin, require paralleling capacitors maintain smaller size (the recommended ceramic capacitor larger than other similar-valued capacitors with different dielectrics). Larger resistor values will increase voltage drop across resistor recharging current charges switched capacitor input.
OFST
CS5320/21 modulator produce "idle tones" which occur passband when input signal steady state signal within about bipolar zero. CS5320/21 these tones about down from full scale. user force these idle tones "out-of-band" adding offset signal input. Alternately, user circuitry offset voltage such that input signal within bipolar zero when signal present, OFST CS5320/21 activated. When OFST +100 input reDS454PP1
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ferred offset will added internal CS5320/21 guarantee that idle tones present will out-of-band. user should certain that when OFST active (OFST that offset voltage generated user circuitry does negate offset added OFST pin. modulator fourth order delta-sigma therefore conditionally stable. modulator into oscillatory condition analog input overranged. Input signals which exceed either plus minus full scale more than introduce instability modulator. unstable condition detected, modulator will reduced first order system until loop stability achieved. this occurs MFLG will transition from high will result error being CS5322. input signal must reduced within full scale range converter least MCLK cycles modulator recover from this error condition.
Input Range Overrange Conditions
analog input applied AIN+ AINR pins with AIN- connected GND. input fully differential proper operation AIN- must remain potential. analog input span defined voltage applied between VREF+ VREF- input pins. Voltage Reference section this data sheet voltage reference requirements.
Analog Supply
Digital Supply
0.01
Vdd1 GND1
Vdd2
GND11 MSYNC MFLG MCLK Control Logic
DGND SCLK Serial Data Interface RSEL ERROR CSEL
OFST LPWR +4.5V VREF
TANT. VREFVREF+
MSYNC MFLG MCLK MDATA
DRDY
AIN+ AIN14 AINR
MDATA
Signal Source
CS5320/21
MDATA
CS5322
Test Data TDATA PWDN USEOR ORCAL GND8 GND9 Clock Source SYNC CLKIN DECA DECB DECC RESET Digital Supply
0.01
Hardware Control
GND7
GND6 GND5 GND4 GND3
GND2 Vss1
GND10
DGND Unused logic inputs must connected DGND
Analog Supply
Figure System Connection Diagram
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Voltage Reference
CS5320/21 designed operate with voltage reference range volts. voltage reference applied VREF+ with VREF- connected GND. reference will result best performance most references require power supply voltage greater than operation. reference used those applications which must operate from only supplies, will yield slightly lower (1-2 than when using reference. voltage reference should designed yield less than noise band VREF+ CS5320/21. CS5322 filter selection will determine bandwidth over which voltage reference noise will affect CS5320/21/22 dynamic range. reference, LT1019-4.5 voltage reference yields enough noise output filtered with pass filter shown Figure Option filter Figure Option acceptable most spectral measurement applications, buffered version with lower source impedance (Figure Option preferred
dc-measurement applications. dynamic (switched-capacitor) input input impedance +VREF CS5320/21 will change time MCLK changed. Therefore current required from voltage reference will change time MCLK changed. This affect gain accuracy high source impedance filter resistor Figure Figure Option gain error minimized, especially when MCLK changed, voltage reference should have lower output impedance. buffer Figure Option offers lower output impedance will exhibit better system gain stability.
Clock Source
proper operation, CS5320/21 must provided with CMOS-compatible clock MCLK pin. MCLK CS5320/21 usually provided CS5322 filter. MCLK usually 1.024 seven selectable output word rates from CS5322. MCLK frequency high MHz. choice clock frequency affect performance; Performance section data
Option
VREF+
LT1019-4.5
Option
49.9
Tant
VREF+
LT1007
Figure Voltage Reference with filter options
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sheet. clock must have less than jitter maintain data sheet performance from device. CS5320/21 equipped with loss clock detection circuitry which will cause CS5320/21 enter powered-down state MCLK removed reduced very frequency. CS5320/21 modifies sampling clock rate modulator. When modulator sampling clock will MCLK/4; with modulator sampling clock will MCLK/8. chip will exhibit about less performance when changed from logic logic same output word rate from CS5322. proper synchronization bitstream, CS5320/21 must furnished with MSYNC signal prior data conversion. MSYNC signal, generated CS5322, resets MCLK counter-divider CS5320/21 correct phase that bitstream properly sampled CS5322 digital filter. When operated with CS5322 digital filter output codes from CS5320/21/22 will range from approximately decimal -5,242,880 +5,242,879 input CS5320/21 ±4.5 Table illustrates output coding various input signal amplitudes. Note that with signal input defined full scale signal (4.5 with VREF+ CS5320/22 CS5321/22 chipsets does output full scale digital code 8,388,607 scaled lower value allow some overrange capability. Input signals exceed defined full scale still converted properly.
CS5322 Filter Output Code 53FFFF(H) 4FFFFF(H) 000000(H) B00000(H) AC0000(H) Decimal +5505023 +5242879 -5242880 -5505024 Error Flag Possible
Power Mode
CS5320/21 includes power operating mode (LPWR =1). When operated with LPWR CS5320/21 modulator sampling clock must restricted rates less. Operating power mode with modulator sample rates greater than will greatly degrade performance.
Digital Interface Data Format
MCLK signal (normally 1.024 MHz) divided four, eight inside CS5320/21 generate modulator oversampling clock. determines whether clock divider inside CS5320/21 divides four (HBR eight (HBR modulator outputs ones density stream from MDATA MDATA pins proportional analog input signal, rate determined modulator over sampling clock.
Modulator Input Signal (+VREF (+VREF +VREF -VREF (+VREF +5%) (+VREF +5%)
Error Flag Possible
Table Output Coding CS5320/21 CS5322 Combination
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Performance
Figure illustrate spectral performance CS5321/22 CS5320/22 chipsets when operating from 1.024 master clock. 1024 point FFTs were averaged produce plots. Figure illustrates chip with input signal. sample rate kHz. Dynamic range dynamic range calculated test soft-ware reduced somewhat Figures because jitter signal test oscillator. Jitter signal source interpreted signal processing software increased noise. choice master clock frequency will affect performance. CS5320/21 will exhibit best Signal/ Distortion performance with slower modulator sampling clock rates slower sample rates allow more time amplifier settling. lowest offset drift, CS5320/21 should operated with MCLK 1.024 Slower modulator sampling clock rates will exhibit more offset drift. Changing MCLK (HBR changing zero (MCLK 1.024 MHz) will cause drift rate double. Offset drift linear over temperature difficult specify exact drift rate. Offset drift characteristics vary from part part will vary power supply voltages vary. Therefore, CS5320/21 used precision measurement applications where offset drift minimized, power supplies should well regulated. CS5320/21 will exhibit about ppm/°C offset drift with MCLK Gain drift CS5320/21 itself about ppm/°C affected either modulator sample rate power supply variation.
-100 -120 -140 -160 -180
Dynamic Range 122.0 OFST LPWR
Figure 1024 Point Plot with Input, Input, averages
-100 -120 -140 -160 -180
text
116.0 118.4 S/N+D 114.2 OFST LPWR
Figure 1024 Point Plot with Full Scale Input, Input, averages
-100 -120 -140 -160 -180
text
122.7 117.1 S/N+D 116.4 OFST LPWR
Figure 1024 Point Plot with Full Scale Input, Input, averages
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Power Supply Considerations
system connection diagram, Figure illustrates recommended power supply arrangements. There positive power supply pins CS5320/21 negative power supply pins. Power must supplied four pins each supply pins should de-coupled with capacitor nearest ground device. When used with CS5322 digital filter, maximum voltage differential between positive supplies CS5320/21 positive digital supply CS5322 must less than 0.25 Operation beyond this constraint result loss analog performance CS5320/22 CS5321/22 system performance. Many seismic portable data acquisition systems battery powered utilize dc-dc converters generate necessary supply voltages system. minimize effects power supply interference, desirable operate dc-dc converter frequency which rejected digital filter, locked modulator sample clock rate. synchronous dc-dc converter, whose operating frequency derived from 1.024 clock used drive CS5322, will minimize potential "beat frequencies" appearing passband between corner frequency digital filter.
2.11 RESET Operation
RESET puts CS5322 into known initialized state. RESET recognized next CLKIN rising edge after RESET been brought high (RESET=1). internal logic initialized when RESET active. Normal device operation begins second CLKIN rising edge after RESET brought low. CS5322 will remain idle state, performing convolutions, until triggered SYNC event. RESET operation clears memory, sets data output register, offset register, status flags zeroes, sets configuration register state corresponding hardware pins (PWDN, ORCAL, DECC, DECB, DECA, USEOR, CSEL). reset state entered power independent RESET pin. RESET low, first CLKIN will exit power reset state.
2.12 Power-down Operation
PWDN puts CS5322 into powerdown state. power-down state entered first CLKIN rising edge after PWDN brought high. While power-down state, MCLK MSYNC signals CS5320/21 analog modulator held low. loss MCLK signal modulator causes power-down. signals MDATA MFLG pins ignored. serial interface CS5322 remains active allowing read write operations. Information data register, offset register, configuration register, convolution data memory maintained during power-down. internal controller requires clock cycles after PWDN asserted before CLKIN stops. CS5322 exits power-down state first CLKIN rising edge after PWDN brought low. CS5322 then enters idle state until triggered SYNC event.
2.10 Power Supply Rejection Ratio
PSRR CS5320/21 frequency dependent. CS5322 digital filter attenuation will rejection power supply noise frequencies above corner frequency setting CS5322. frequencies between corner frequency digital filter, PSRR nearly constant about
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avoid possible high current states while power down state, following conditions apply: CLKIN must active least clock cycles after PWDN entry. CSEL TDATA must both asserted high. SCLK falling edge, each SCLK rising edge shifts bit. Status reads bits, data reads bits. Both streams supplied first, last. event more SCLK pulses supplied than necessary clock requested information, trailing zeroes will output data reads trailing LSB's status reads. read operation terminated before bits read, internal pointer reset that re-read will give same data first read, with exception. status error flags cleared read will available re-read. status error flags must read before entering power-down state. error occurred before entering powerdown status (ERROR) been read, status bits (ER-ROR, OVERWRITE, MFLG, ACC1 ACC2) cleared status reads. Upon exiting powerdown state entering normal operation, user flagged that error still present. floats when read operation deactivated (R/W=1, CS=1). This enables pins tied together form bi-directional serial data bus. There internal nominal pull-up resistor pin.
2.13 SYNC Operation
SYNC used start convolutions synchronize CS5322 CS5320/21 external sampling source timing reference. SYNC event recognized first CLKIN rising edge after SYNC goes high. SYNC remain high indefinitely. Only sequence SYNC rising followed CLKIN rising generates SYNC event. SYNC event aligns output sample causes filter begin convolutions. first SYNC event causes immediate DRDY provided DRDY low. Subsequent data ready events will occur rate determined decimation rate inputs DECC, DECB, DECA. Multiple SYNC events applied with effect operation they perfectly timed according decimation rate. SYNC event step with decimation rate will cause realignment loss data.
2.15 Serial Write Operation
Serial write used write data configuration register. R/W, SCLK pins control serial write operation. serial write operation activated when goes (CS=0) with (R/W=0). Serial input data sampled falling edge SCLK. input bits stored temporary buffer until either write operation terminated bits have been received. data then parallel loaded into configuration register. fewer than bits input before write termination, other bits indeterminate.
2.14 Serial Read Operation
Serial read used obtain status conversion data. R/W, SCLK, RSEL, pins control read operation. serial read operation activated when goes (CS=0) with high (R/W=1). RSEL selects between conversion data (data register) status information (status register). selected serial stream output (Serial Output Data) pin. read select, SCLK either high low, first appears should latched falling edge SCLK. After first
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Note that write will occur when even SCLK toggled. Failure clock data with appropriate number SCLKs leave configuration register indeterminate condition. serial stream received first, last. order input control data PWDN first, followed ORCAL, USEOR, CSEL, Reserved, DECC, DECB, DECA. configuration data bits defined Table configuration data controls device operation only when software mode, i.e., (H/S Reserved configuration data must always written low. (except when ORCAL CS5322 RESET this toggles ORCAL internally). After ORCAL been toggled, SYNC signal must applied CS5322. filter settles input value output words. output word rate determined state decimation rate control pins, DECC, DECB, DECA. 57th output word, CS5322 issues ORCALD status flag, outputs offset data sample, internally loads offset register. During calibration, offset register value used. USEOR high (USEOR=1), subsequent samples will have offset subtracted from output. state USEOR must remain high complete duration convolution cycle. USEOR (USEOR=0), output word corrected, offset register retains value later use. results last calibration will held offset register until calibration, until CS5322 reset using RESET pin. USEOR does alter offset register value, only usage. restart calibration, ORCAL SYNC must taken least CLKIN cycle. ORCAL must then taken high. calibration will restart next SYNC event. ORCAL remains high state, only single calibration will start first SYNC signal.
2.16 Offset Calibration Operation
offset calibration routine computes offset produced CS5320/21 modulator stores this value offset register. USEOR determines offset register data used correct output words. After power applied chip CS5322 must RESET. begin offset calibration, CS5320/21 analog input must represent offset value. Then software mode (H/S ORCAL must toggled from high. hardware mode ORCAL must toggled least CLKIN cycle, then taken high
Input (MSB) (LSB)
Equivalent Hardware Function PWDN ORCAL USEOR CSEL Reserved DECC DECB DECA
Description Standby mode Self-offset calibration Offset Register Channel Select Factory only Filter selection Filter selection Filter selection
Table Configuration Data Bits
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2.17 Status Bits
Status Register 16-bit register which allows user read flags configuration settings CS5322. Table documents data bits Status Register. ERROR flag, ERROR, OR'ed result OVERWRITE, MFLG, ACC1, ACC2. ERROR active high whenever four error bits fault condition. ERROR output nominal internal pull-up resistor. OVERWRITE when conversion data ready loaded into data register, previous data completely read out. This occur either conditions: read operation progress read operation started, then aborted, completed. These conditions data read attempts. attempt identified first SCLK edge (MSB read) data register read. data register read attempted, CS5322 assumes that data wanted does assert OVERWRITE, data over-written data. OVERWRITE condition, partially read data preserved, data word lost. Status reads have effect OVERWRITE assert operations. OVERWRITE cleared status register read RESET. MFLG error reflects CS5320/21 MFLG signal. high level CS5322 MFLG will MFLG status bit. cleared status register read RESET operation, only MFLG CS5322 returned low. internal nominal pulldown resistor MFLG pin. accumulator error bits, ACC1 ACC2, indicate that underflow overflow occurred FIR1 filter ACC1, FIR2 FIR3 filters ACC2. Both errors cleared status read, provided error conditions longer
Output (MSB)
Function Error OVERWRITE Error MFLG Error ACC1 Error ACC2 Error DRDY 1SYNC ORCALD PWDN ORCAL USEOR CSEL Reserved DECC DECB DECA
Description Detects errors below Overwrite Error Modulator Flag Error Accumulator Error Accumulator Error Data Ready First sample after SYNC Offset calibration done Standby mode Self-offset Calibration Offset Register Channel Select Factory only Bandwidth Selection Status Bandwidth Selection Status Bandwidth Selection Status
Table Status Data (from Pin)
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present. normal operation ACC1 error will only occur when input data stream FIR1 more than bits. ACC2 error cannot occur normal operation. DRDY reflects state DRDY pin. DRDY rising edge indicates that data word been loaded into data register available reading. DRDY will fall after SCLK falling edge that reads data register LSB. nodata read attempt made, DRDY will pulse CLKIN cycle, providing positive edge data availability. OVERWRITE case, DRDY remains high because data loaded normal conversion time. 1SYNC status provides indication filter group delay. goes high second output sample after SYNC valid only that sample. repetitive SYNC operations, SYNC must fourth output word rate slower avoid interfering with 1SYNC operation. With these slower repetitive SYNC's non-periodic SYNC's separated least three output words, 1SYNC will occur second output sample after SYNC. ORCALD indicates that calibration offset register complete offset sample available output register. This flag high only during that sample otherwise low. remaining five status bits (PWDN, ORCAL, USEOR, CSEL, Reserved, DECC, DECB, DECA) provide configuration readback user. These bits echo control source CS5322 such that hardware mode (H/S=1), they follow corresponding input pins. host mode (H/S=0) they follow corresponding configuration bits. brief explanation eight bits follows: PWDN When high, indicates that CS5322 power-down state. ORCAL When high, indicates potential calibration start. USEOR When high, indicates Offset Register used. During calibration, this will read zero indicating offset register being used during calibration. CSEL- When high, TDATA selected filter source. When low, MDATA output signal from CS5320/21 selected input source filter. Reserved Always read low. DECC, DECB, DECA Indicate decimation rate filter defined Table
DECC
DECB
DECA
Output Word Rate (Hz) 62.5 1000 2000 4000 Reserved
Clocks Filter Output 16384 8192 4096 2048 1024
Table Bandwidth Selection: Truth Table
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2.18 Board Layout Considerations
filter capacitors power supplies, AIN+, AINR, should placed very close chip connect nearest ground device. capacitors between VREF+ VREF- should located close chip possible. capacitors AIN+ AINR pins should placed with their leads same axis, side-by-side. these capacitors placed side-by-side their electric fields interact cause increased distortion. chip should surrounded with ground plane. Trace fill should used around analog input components. AN18: Layout Design Rules Data Converters further information.
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CS5320/21 DESCRIPTIONS
Power Supplies Vdd1 Positive Power One, Positive supply voltage. Nominally Volts. Vdd2 Positive Power Two, Positive supply voltage. Nominally Volts. Vss1 Negative Power One, Negative supply voltage. Nominally Volts. Vss2 Negative Power Two, Negative supply voltage. Nominally Volts. GND1 through GND11 Ground, PINS Ground reference. Analog Inputs AIN+ Positive Analog Input, Nominally 4.5V AIN- Negative Analog Input, This tied ground.
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AINR Analog Input Rough, Allows non-linear current bypass main external anti-aliasing filter which allowed happen, would cause harmonic distortion modulator. Please refer System Connection Diagram Analog Input Voltage Reference section data sheet recommended this pin. VREF+ Positive Voltage Reference Input, This accepts external +4.5 voltage reference. VREF- Negative Voltage Reference Input, This tied ground. Digital Inputs MCLK Clock Input, CMOS-compatible clock input this (nominally 1.024 MHz) provides necessary clock operation modulator data output portions converter. MCLK normally supplied CS5322 MSYNC Modulator Sync, transition from high level this input will re-initialize CS5320/21. MSYNC resets divider-counter align MDATA output stream from CS5320/21 with timing inside CS5322. OFST Offset, When high, adds approximately input referred offset guarantee that zero input limit cycles band present. When low, zero offset added. LPWR Power Mode, CS5320/21 power dissipation reduced from nominal value under following conditions: LPWR=1; MCLK kHz, HBR=1; LPWR=1; MCLK 1.024 MHz, HBR=0 High Rate, Selects either MCLK (HBR=1) /8MCLK (HBR=0) modulator sampling clock. Digital Outputs MDATA Modulator Data Output, Data will presented one-bit serial data stream rate (HBR=1) (HBR=0) with MCLK operating 1.024 MHz. MDATA Modulator Data Output, Inverse MDATA output. MFLG Modulator Flag, transition from high level signals that CS5320/21 modulator unstable over-range analog input
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CS5322 DESCRIPTIONS
CHIP SELECT FRAME SYNC SYNC RSEL SCLK
READ/WRITE REGISTER SELECT SERIAL CLOCK SERIAL INPUT DATA SERIAL OUTPUT DATA DATA READY POSITIVE DIGITAL POWER DIGITAL GROUND DECIMATION RATE CONTROL DECIMATION RATE CONTROL DECIMATION RATE CONTROL
CLOCK INPUT CLKIN RESET RESET MODULATOR SYNC MSYNC MODULATOR FLAG MODULATOR CLOCK POSITIVE DIGITAL POWER DIGITAL GROUND MFLG MCLK DGND CS5322
VIEW
DRDY DGND DECA DECB DECC
ERROR ERROR FLAG
MODULATOR DATA MDATA TEST DATA TDATA CHANNEL SELECT HARDWARE/SOFTWARE MODE CSEL
ORCAL OFFSET CALIBRATION
POWER DOWN PWDN
USEOR OFFSET REGISTER
Power Supplies Positive Digital Power, Positive digital supply voltage. Nominally volts. DGND Digital Ground, Digital ground reference. Digital Outputs MCLK Modulator Clock Output, CMOS-compatible clock output (nominally 1.024 MHz) that provides necessary clock operation modulator. MSYNC Modulator Sync, transition from high level this output will re-initialize CS5320/21. ERROR Error Flag, This signal output open pull-up gate with nominal pull-up resistor which error status data (OVERWRITE error, MFLG error, ACC1 error ACC2 error) inputs. When low, notifies host processor that error condition exists. ERROR signal wire OR'd together with other filters' outputs. value internal pull-up resistor DRDY Data Ready, When high, data ready shifted serial port data register.
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Serial Output Data, output coding complement with data bits presented first, last. Data changes rising edge SCLK. internal nominal pull-up resistor included. Digital Inputs MDATA Modulator Data, Data will presented one-bit serial data stream rate KHz; (CLKIN 1.024 MHz). TDATA Test Data, Input user test data. MFLG Modulator Flag, transition from high level signals that CS5320/21 modulator unstable over-range analog input. Status will digital filter indicating error condition. internal nominal pull-down resistor included input pin. RESET Filter Reset, Performs hard reset chip, registers accumulators cleared. signals device locked except CLKIN. error flags Status Register zero Data Register Offset Register zero. configuration register values corresponding input pins. SYNC must applied resume convolutions after RESET deasserts. CLKIN Clock Input, CMOS-Compatible clock input this (nominally 1.024 MHz) provides necessary clock operation modulator filter. SYNC Frame Sync, Conversion synchronization input. This signal synchronizes start filter convolution. More than SYNC signal occur with effect filter performance, providing SYNC signals perfectly timed intervals equal output sample period. CSEL Channel Select, When high, information TDATA presented digital filter. causes data MDATA input presented digital filter. PWDN Powerdown, Powers down filter when taken high. Convolution cycles digital filter MCLK signal stopped. registers maintain their data serial port remains active. SYNC must applied resume convolutions after PWDN deasserts. DECA Decimation Rate Control, Table DECB Decimation Rate Control, Table
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DECC Decimation Rate Control, Table Hardware/Software Mode Select, When high, device pins control device operation; when low, value entered prior configuration write controls device operation. Chip Select, When high, signal activity SID, SCLK pins ignored. DRDY ERROR signals indicate status chip's internal operation. Read/Write, Used conjunction with such that when both signals low, filter inputs data from falling edge SCLK. high, filter outputs data rising edge SCLK. floats allowing tied together, forming bidirectional serial data bus. SCLK Serial Clock, Clock signal generated host processor either input data input pin, output data output pin. write, data must valid falling edge SCLK. Data changes rising edge SCLK. Serial Data Input, Data bits presented first, last. Data latched falling edge SCLK. RSEL Register Select, Selects conversion data when high, status data when low. USEOR Offset Register, offset register value correct output words when high. Output words will offset corrected when low. ORCAL Offset Register Calibrate, Initiates offset calibration cycle when SYNC goes high after ORCAL been toggled from high. offset value output 57th word following SYNC. Subsequent words will have their offset correction controlled USEOR.
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ORDERING INFORMATION
Kits Part Number CK5320-KL1 CK5321-KL1 CK5321-BL1 Part Number CS5320-KL CS5321-BL CS5321-BL Analog Modulator Temperature
Digital Filter Package 28-pin PLCC 28-pin PLCC 28-pin PLCC Part Number CS5322-KL CS5322-KL CS5322-BL Temperature +70o
Package 28-pin PLCC 28-pin PLCC 28-pin PLCC
-55o +85o -55o
Table Detailed Ordering Information
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PARAMETER DEFINITIONS
Dynamic Range ratio full-scale (rms) signal broadband (rms) noise signal. Broadband noise measured with input grounded within bandwidth (See "CS5322 FILTER CHARACTERISTICS" page Units Signal-to-Distortion ratio full-scale (rms) signal harmonics Units Intermodulation Distortion ratio test frequencies which each down from full-scale intermodulation components within bandwidth Units Full Scale Error ratio difference between value voltage reference analog input voltage full scale span (two times voltage reference value). This ratio calculated after effects offset external bias components removed analog input voltage adjusted. Measurement this parameter uses circuitry illustrated System Connection Diagram. Units Full Scale Drift change Full Scale value with temperature. Units %/°C. Offset difference between analog ground analog voltage necessary yield output code from CS5320/22 CS5321/22 000000(H). Measurement this parameter uses circuit configuration illustrated System Connection Diagram. Units Offset Drift change Offset value with temperature. Measurement this parameter uses circuit configuration illustrated System Connection Diagram. Units µV/°C.
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PACKAGE DIMENSIONS
PLCC PACKAGE DRAWING
D2/E2
INCHES 0.165 0.090 0.013 0.485 0.450 0.390 0.485 0.450 0.390 0.040 0.180 0.120 0.021 0.495 0.456 0.430 0.495 0.456 0.430 0.060
MILLIMETERS 4.043 4.572 2.205 3.048 0.319 0.533 11.883 12.573 11.025 11.582 9.555 10.922 11.883 12.573 11.025 11.582 9.555 10.922 0.980 1.524
JEDEC MS-018
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Notes

24-Bit Variable Bandwidth Converter Chipset CMOS Description

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