Fixed Function Multi-Effects Audio Processor Audio Descripti

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Fixed Function Multi-Effects Audio Processor Audio Descripti

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CS4811
Fixed Function Multi-Effects Audio Processor
Audio
Description
CS4811 complete audio effects processing system chip. This device integrates proprietary 24bit audio processing engine, large on-chip memories, high performance 24-bit audio codec. serial control port allows device boot firmware from compact cost serial EEPROM. Other features such single operation simplify system design. There different firmware codes available; guitar effects audio mixers. guitar effects firmware provides host electric guitar effects including spring reverb, delay, chorus, flange tremolo. mixer effects firmware provides suite effects such digital reverb, delay chorus which suitable audio mixers, karaoke acoustic instrument amplifiers. CDB4811GTR CDB4811MXR evaluation boards allow easy evaluation CS4811 device associated firmware. ORDERING INFO CS4811-KM CDB4811GTR-01 CDB4811MXR-01 +70°C 100-pin MQFP Guitar Effects Evaluation Board Mixer Effects Evaluation Board
Processor embedded reverb/effects applications
Proprietary 24-bit Audio Processing Engine On-chip external required) On-chip 24-bit with Dyn. Range On-chip 24-bit with Dyn. Range Automatically boots firmware from external serial EEPROM Firmware CS4811 provided Cirrus Logic.
Firmware available Guitar Effects Mixer
Effects applications Single Supply 100-pin Metric Quad Flat Pack (MQFP)
SPI/I2C
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
CLOCK MANAGER
SERIAL CONTROL PORT (SPI I2C)
ANALOG OUTPUT STAGE
AOUT+
DIGITAL
24-BIT AUDIO PROCESSING ENGINE
DIGITAL FILTER
AIN+ AINADC
AOUT-
VOLTAGE REFERENCE
CMOUT CMFILT+ CMFILT-
PIO0 PIO1 PIO2 PIO3
Advance Product Information
P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
DS486PP2
CS4811
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS CHARACTERISTICS CHARACTERISTICS SWITCHING CHARACTERISTICS SWITCHING CHARACTERISTICS CONTROL PORT MASTER. SWITCHING CHARACTERISTICS CONTROL PORT MASTER RECOMMENDED OPERATING CONDITIONS DIGITAL CHARACTERISTICS SWITCHING CHARACTERISTICS PROGRAMMABLE I/O. TYPICAL CONNECTION DIAGRAMS FUNCTIONAL DESCRIPTION Overview Analog Inputs 3.2.1 Line Level Inputs 3.2.2 Digital High Pass Filter Analog Outputs 3.3.1 Line Level Outputs Clock Generation 3.4.1 Clock Source Serial Control Port 3.5.1 3.5.1.1 Mode 3.5.2 3.5.2.1 Mode Resets POWER SUPPLY GROUNDING DESCRIPTIONS PARAMETER DEFINITIONS PACKAGE DIMENSIONS
Contacting Cirrus Logic Support
complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site
Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Items from Cirrus Logic website disk printed user. However, part printout electronic files copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc.Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
DS486PP2
CS4811
LIST FIGURES
Figure Control Port Timing Figure Control Port Timing Figure Typical Connection Diagram, Single-ended Input Figure Typical Connection Diagram, Mode Figure Typical Connection Diagram, Mode Figure Optional Line Input Buffer Figure Butterworth Output Filters Figure Output Mute Circuit Figure Control Port Timing, Master Mode Self-Boot Figure 10.Control Port Timing, Master Mode Self-Boot Figure 11.CS4811 Suggested Layout Figure 12.Pin Assignments
DS486PP2
CS4811
CHARACTERISTICS SPECIFICATIONS
CHARACTERISTICS Full Scale Input Sine wave, kHz; 12.2880 MHz; Measurement Bandwidth kHz)
Parameters Symbol Stereo Audio channels weighted, Note (unweighted, Note (Note 1,4) (Note (Note THD+N (Note -3dB (Note -0.14dB (Note (Note CMRR Units Bits Vrms ppm/°C Degree
Analog Input Characteristics
Conversion Dynamic Range Total Harmonic Distortion Noise Offset Error (with internal high pass filter enabled) Full Scale Input Voltage (Differential) Gain Drift Input Resistance Input Capacitance CMOUT Output Voltage Common Mode Rejection Ratio
High Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple Notes: Referenced typical full-scale differential input voltage Vrms). Bench tested only. Filter characteristics scale with output sample rate. Measured using differential analog input circuit, Figure Filter response tested guaranteed design.
DS486PP2
CS4811
CHARACTERISTICS Full Scale Output Sine wave,
kHz; 12.288 MHz; Measurement Bandwidth kHz) Parameters Resolution Dynamic Range Offset Voltage (differential) Offset Voltage (V+/V- relative CMOUT) Full Scale Output Voltage Gain Drift Band Energy Analog Output Load Resistance Capacitance CCIR-2K (DAC muted, weighted) THD+N (Note (Note (Differential) (Note (Fs/2 2Fs, Note Total Harmonic Distortion Noise Symbol -20±5 -45/-28 Units Bits Vrms ppm/°C dBFS
Analog Output Characteristics Minimum Attenuation, load; unless otherwise specified.
Analog Loopback Performance
Signal-to-Noise Ratio (CCIR-2K weighted, input)
Power Supply
Power Supply Current Power Supply Rejection Operating Power Down (Note
kHz, mVrms,, Note
Notes: Measured with calibration disabled. Measured with clock disabled. Specifications subject change without notice.
DS486PP2
CS4811
SWITCHING CHARACTERISTICS outputs loaded with
Parameters Sample Rate Frequency 256Fs Duty Cycle =256Fs Jitter Tolerance Time (Note (Note Symbol 7.68 12.8 Units
Notes: Guaranteed characterization tested. power-up, CS4811 should asserted until power supplies have reached steady state.
DS486PP2
CS4811
SWITCHING CHARACTERISTICS CONTROL PORT MASTER
Inputs: logic DGND, logic Parameter Symbol Master (Self-Boot) Mode (SPI/I2C SCPM/S fsck CCLK Clock Frequency CCLK Time CCLK High Time CCLK Rise Time CCLK Fall Time rising falling High Time Between Transmissions Falling CCLK Edge Falling CDOUT valid CCLK Falling CDOUT valid CDIN CCLK Rising Setup Time CCLK Rising DATA Hold Time CCLK Falling rising (Note (Note tscl tsch tsrs tcsh tcss tdsu tclcs 1/(2*Fs) 1/(2*Fs) Units
Notes: Measured with pullup resistor
CCLK
CDIN
clcs
CDOUT
Figure Control Port Timing
DS486PP2
CS4811
SWITCHING CHARACTERISTICS CONTROL PORT MASTER
Inputs: logic DGND, logic Parameter Symbol 13.5 1/(2*Fs) 1/(2*Fs) Units
I2C®
Master (Self-Boot) Mode (SPI/I2C SCPM/S (Note fscl Clock Frequency
Clock Time Clock High Time Free Time Between Transmissions tlow thigh tbuf tirs thdst tsust tsud (Note (Note (Note thdd tcldv tsusp
rising start condition Start Condition Hold Time Setup Time Repeated Start Condition Setup Time Rising Hold Time from Falling falling Output Valid Rise Time Fall Time Setup Time Stop Condition
Notes: interface requires license from Philips. registered trademark Philips Semiconductors. Data must held sufficient time bridge worst case fall time CCLK/SCL. both transmitting receiving.
Stop
(output)
Start
cldv
Repeated Start
Stop
hdst
high
hdst
susp
sust
Figure Control Port Timing
DS486PP2
CS4811
ABSOLUTE MAXIMUM RATINGS (All voltages with respect AGND DGND
Parameters Power Supplies Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Digital Analog (Note (Note (Note (Power Applied) Symbol -0.3 -0.3 -0.7 -0.7 ±10.0 (VA)+0.7 (VD)+0.7 +125 +150 Units
Notes: except supplies. Transient currents ±100 analog input pins will cause latch-up. maximum over under voltage limited input current. Warning: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. (All voltages with respect AGND DGND 4.75 4.75 5.25 5.25 Units
RECOMMENDED OPERATING CONDITIONS
Parameters Power Supplies 0.4V Operating Ambient Temperature Digital Analog
Symbol
DIGITAL CHARACTERISTICS
Parameters High-level Input Voltage Low-level Input Voltage High-level Output Voltage -2.0 Low-level Output Voltage High-level Input Voltage Low-level Input Voltage Input Leakage Current Output Leakage Current (except XTI) (except XTI) (except XTO) (except XTO) (XTI) (XTI) (Digital Inputs) (High-Z Digital Outputs) Symbol -0.3 (VD)-1.0 (VD)+0.3 Units
SWITCHING CHARACTERISTICS PROGRAMMABLE
±5%; Inputs: logic DGND, logic Parameters Output Rise Time Output Fall Time DS486PP2 Symbol trpo tfpo Units
CS4811
TYPICAL CONNECTION DIAGRAMS
Ferrite Bead
Supply
AIN+
AOUT ANALOG FILTER
AOUT
CS4811
Optional Input Output Buffers
RES-VD
CMOUT
CMFILT+
CMFILT-
RES-NC RES-NC RES-NC
SCL/CCLK SDA/CDOUT
AD0/CS AD1/CDIN
Serial EEPROM
RES-DGND Mode/Reset Circuit SPI/I2C RES-DGND RES-DGND RES-DGND Control/ Monitor Circuitry PIO0 PIO1 PIO2 RES-DGND RES-DGND
RESET
PIO3
AGND1.4 DGND1.4 Caps, Xtal, resistor needed with external clock input XTI.
unused inputs should tied ground.
Figure Typical Connection Diagram, Single-ended Input
DS486PP2
CS4811
CS4811
SCL/CCLK
SDA/CDOUT AD0/CS
EEPROM
AD1/CDIN
SPI/I2C
Reset Circuit
RESET
Figure Typical Connection Diagram, Mode
CS4811 SCL/CCLK
EEPROM
SDA/CDOUT
AD0/CS AD1/CDIN
SPI/I2C
Reset Circuit
RESET
Figure Typical Connection Diagram, Mode
DS486PP2
CS4811
FUNCTIONAL DESCRIPTION Overview
CS4811 complete audio subsystem chip, integrating proprietary 24-bit audio processing engine with large chip memories single channel 24-bit audio codec. delta-sigma includes linear phase digital anti-aliasing filters only requires single-pole external passive filter. sigma-delta includes switched-capacitor anti-image filter requires external order active filter that easily integrated into output differential-to-single-ended converter circuit. serial control port designed accommodate I2C® interfaces stand-alone operation with external non-volatile memory. pins allows signals centered around input CS4811. Figure shows operation with single-ended input source. This source supplied either positive negative input long unused input connected ground through capacitors shown. When operated with singleended inputs, distortion will increase input levels higher than Full Scale. better performance required, single-ended-to-differential converter, shown Figure used. This circuit provides unity gain, blocking input anti-alias filtering. output asserts when analog input out-of-range.
3.2.2
Digital High Pass Filter
3.2.1
Analog Inputs Line Level Inputs
AIN+ AIN- differential line level analog inputs (See Figure These pins internally biased CMOUT voltage blocking capacitor placed series with input
coupled systems, small offset exist between input circuitry converters. CS4811 includes high pass filter after decimator remove these components. high pass filter response, given High Pass Filter Characteristics, scales linearly with sample rate. Thus, frequency 44.1 sample rate will equal 44.1/48 times that sample rate kHz.
input signal Vrms max)
CMOUT
from CS4811
Buffered CMOUT
Figure Optional Line Input Buffer DS486PP2
CS4811
3.3.1 Analog Outputs Line Level Outputs
ommended mute circuit referenced Figure Activating mute circuit recommended power-up power-down avoid output undesirable audio signals.
CS4811 contains on-chip differential buffer amplifiers that produce line level outputs AOUT+ AOUT-, which capable driving loads. These amplifiers internally biased CMOUT voltage recommended off-chip analog filter order Butterworth with corner third order Butterworth filter with corner 0.75 used greater band noise filtering desired. These filters easily integrated into differential-to-single-ended converter circuit shown 2-pole 3-pole Butterworth filters Figure Figure shows rec-
Clock Generation
master clock operate CS4811 generated using on-chip oscillator with external crystal input from external clock source.
3.4.1
Clock Source
CS4811 requires master clock internal logic. possible clock sources on-chip crystal oscillator external clock input pin. master clock generated directly from on-chip crystal oscillator circuit. When using on-chip crystal oscillator, external loading capacitors required. (see Figure High frequency crystals MHz) should parallel resonant, fundamental mode designed loading. (equivalent ground each leg) master clock also generated directly from external CMOS clock input pin.
14.0 14.0 T1000 14.0 1000
BUFFERED CMOUT
3.24
Example Op-Amps MC33078
MUTE
Line
3.24
14.0
2-Pole Butterworth Filter
14.0k 2.8k 11.0k 2.8k
Line
MUTE
MMBT3906
Line
T2200 2200
MMBT3904
2.8k 11.0k
2.8k
2200
BUFFERED CMOUT
2200
14.0k
3-Pole Butterworth Filter
From CS4811
MMBT3906
Figure Butterworth Output Filters
Figure Output Mute Circuit
DS486PP2
CS4811
Serial Control Port
CS4811 then automatically clocks sequential bytes from EEPROM until last byte been received. These bytes include initialization configuration data device along with application firmware code. After last byte received, CS4811 deasserts begins program execution. this point, serial control port becomes inactive cannot accessed.
serial control port used self-booting from external EEPROM supports both I2C® interfaces. desired interface selected SPI/I2C pin, which sampled during de-assertion pin.
3.5.1
interface consists digital signals, CCLK, CDIN, CDOUT CCLK, control port clock, used clock individual data bits. CDIN, control data input, serial data input line CS4811. CDOUT, control data output, output data line from CS4811. chip select signal, asserted enable external port. Data clocked rising edge CCLK clocked falling edge.
3.5.2
interface implemented CS4811 consists digital signals, SDA. serial clock, used clock individual data bits. serial data, bidirectional data line. additional pins, AD0, inputs which determine lowest order bits 7-bit device address should tied ground.
3.5.1.1
Mode
3.5.2.1
Mode
master mode designed read-only operation during self-booting from serial EEPROM. typical self-boot sequence with Xicor X25650 serial EEPROM, equivalent, shown Figure exit from reset, CS4811 asserts 8-bit read instruction (00000011) sent EEPROM followed pre-defined 16-bit start address.
master mode designed read-only operation during self-booting from serial EEPROM. typical self-boot sequence with Microchip X24256 serial EEPROM, equivalent, shown Figure exit from reset, CS4811 sends initial write preamble EEPROM which consists start condition slave
DATA DATA
CDIN
READ COMMAND 16-BIT ADDRESS 0X0000
CDOUT
Figure Control Port Timing, Master Mode Self-Boot
DS486PP2
CS4811
dress byte. slave address consists most significant bits 1010, following bits corresponding device select bits, last (R/W) Following this, 2-byte EEPROM starting address 0x0000 sent EEPROM. 2-byte EEPROM starting address uses only lowest bits sets highest bits zero. begin reading from EEPROM, CS4811 sends another start condition followed read preamble. read preamble identical write preamble except state bit. CS4811 then automatically clocks sequential bytes from EEPROM until last byte been received. These bytes include initialization configuration data device along with application firmware code. After last byte, CS4811 initiates stop condition begins program execution. this point, serial control port becomes inactive cannot accessed.
Resets
Full chip reset only achieved asserting pin. With asserted, chip enters power mode during which control port, CODEC Audio Processor reset, registers returned their default values outputs muted. should asserted during power-up until power supplies have reached steady state. supply voltage drops below Volts, CODEC reset, outputs muted Audio Processor automatically executes soft reset. Upon exit from CODEC reset, Audio Processor restarts application code CODEC performs following procedure: CODEC resynchronizes. outputs unmute.
CHIP ADDRESS (WRITE) MEMORY ADDRESS
CHIP ADDRESS (READ)
DATA
DATA
START
START
STOP
Figure Control Port Timing, Master Mode Self-Boot
DS486PP2
CS4811
POWER SUPPLY GROUNDING
Proper layout grounding critical obtaining optimal audio performance your system. most important rule remember allow currents from digital circuitry couple into sensitive analog circuitry. This generally done using separate filtered power supply analog circuitry, physically separating analog digital components traces layout using wide traces planes ground power. misplaced component trace severely degrade overall system performance. When using separate supplies, analog digital power should connected ferrite bead, positioned closer than device (see Figure 11). CS4811 should derived from quietest power source available. only supply available, suggested arrangement Figure single solid ground plane simplest grounding scheme that works well many cases. this case, analog digital grounds shown Figure tied same ground plane. However, separate analog digital grounds used, they should tied together point with location this point determined circuit layout. considering where digital ground currents will return their supply, connection point chosen keep those currents from flowing through sensitive analog circuit areas. Decoupling capacitors should placed close possible device with lowest value capacitor closest chip. power ground connection vias should placed near their respective component pins should attached directly appropriate plane. traces used power supplies CS4811, they should wide possible maintain impedance. recommended solder CS4811 directly printed circuit board. Soldering improves performance enhances reliability. example layout, please refer CDB4811 data sheet.
1/8"
Digital Power Plane
Ferrite Bead
Note that CS4811 oriented with digital pins towards digital board.
CS4811
Analog Power Plane
Digital Interface
Analog Signals Components
Figure CS4811 Suggested Layout
DS486PP2
CS4811
DESCRIPTIONS
DGND AD1/CDIN AD0/CS SPI/I2C RES-VD RES-NC RES-VD RES-DGND RES-DGND AIN+ AINVA AGND RES-NC RES-NC CMOUT CMFILT+ CMFILTRES-NC RES-DGND RES-NC AOUT+ AOUTRES-NC RES-NC AGND AGND RES-NC RES-NC
CS4811 100-PIN MQFP
DGND SCL/CCLK SDA/CDOUT RES-NC RES-NC RES-NC RES-NC RES-NC RES-DGND RES-NC DGND DGND PIO0 PIO1 RES-DGND PIO2 RES-DGND PIO3 RES-DGND RES-DGND RES-NC RES-NC RES-NC RES-NC AGND RES-NC RES-NC
Figure Assignments
DS486PP2
CS4811
Power Supply
Analog Power Power: analog supply, AGND Analog Ground Ground: analog ground. Digital Power Power: digital supply, DGND Digital Ground Ground: digital ground.
Analog Input
AIN+/- Differential Audio Input Inputs: These pins accept differential analog input signals biased internal reference voltage approximately input signals should 180° phase resulting nominal differential input voltage twice input voltage. single-ended signal also directly applied either input with other input coupled ground through capacitor. general, differential input signals provide better performance. However, singled-ended inputs result reduced cost. Inputs coupled. coupled input signals must biased remaining offset removed internal digital HPF. best performance, passive anti-aliasing filter required. typical connection diagram Figure shows recommended single-ended input circuit. Figure shows recommended differential input circuit. Overload Indicator Output: This asserted when clipping. does latch de-asserts when clipping stops.
Analog Output
AOUT+/- Differential Audio Output Outputs: These pins output differential analog signals which biased internal reference voltage approximately output signals 180° phase resulting nominal differential output voltage twice output voltage. best performance, anti-imaging filter required. Figure shows recommended second third order Butterworth differential-to-singleended output buffer circuits.
DS486PP2
CS4811
Voltage Reference
CMOUT Common Mode Output Output: This provides internally generated reference used biasing external analog circuitry. load CMOUT must only, with impedance less than kilohms. CMFILT+,CMFILT- Common Mode Filter Connections Inputs: These pins connections external filter components required internal common mode reference circuit. typical connection diagram Figure details.
Serial Control Port SPI/I2C Serial Control Port Format Select
Input: This configures control port format tied format tied DGND. SCL/CCLK Serial Control Port Clock Output: This clocks serial control port data into mode. mode, clocks control port data into CDIN CDOUT. AD0/CS Address Chip Select Input/Output: I2C® mode, input must tied ground. mode, output used select boot EEPROM. AD1/CDIN Address Data Input Input: I2C® mode, input must tied ground. mode, CDIN serial control port data input clocked rising edge CCLK. SDA/CDOUT Data Data Output Bidirectional/Output: I2C® mode, bidirectional data line. mode, CDOUT serial control port data output clocked falling edge CCLK.
Clock Crystal
XTI, Crystal Oscillator Connections (Master Clock) Input, Output: These pins provide connections external parallel resonant quartz crystal. Alternately, external clock source applied XTI. clock frequency must 256xFs.
DS486PP2
CS4811
Miscellaneous
PIO0:3 General Purpose Inputs/Outputs Bidirectional: These pins general-purpose digital pins. Default state input. functionality these pins after boot-up determined application firmware. Reset Input: This causes device enter power mode forces control port registers reset their default values. control port accessed when reset low. Connect Input: These pins internally connected should tied ground optimal performance. RES-NC Reserved, Connect
These pins reserved must left unconnected normal operation.
RES-VD Reserved, Connect
These pins reserved must tied normal operation.
RES-DGND Reserved, Connect DGND
These pins reserved must tied digital ground normal operation.
RES-AGND Reserved, Connect AGND
These pins reserved must tied analog ground normal operation.
DS486PP2
CS4811
PARAMETER DEFINITIONS
Dynamic Range ratio full scale value signal other spectral components over specified bandwidth. Dynamic range signal-to-noise measurement over specified bandwidth made with dbFs signal. then added resulting measurement refer measurement full scale. This technique ensures that distortion components below noise level effect measurement. This measurement technique been accepted Audio Engineering Society, AES17-1991, Electronic Industries Association Japan, EIAJ CP-307. Total Harmonic Distortion Noise ratio value signal other spectral components over specified bandwidth (typically kHz), including distortion components. Expressed decibels. ADCs measured dBFs suggested 17-1991 Annex Idle Channel Noise Signal-to-Noise-Ratio ratio analog output level with full scale digital input analog output level with zeros into digital input. Measured A-weighted over bandwidth. Units decibels. This specification been standardized Audio Engineering Society, AES17-1991, referred Idle Channel Noise. This specification also been standardized Electronic Industries Association Japan, EIAJ CP-307, referred Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) ratio test signal amplitude in-band harmonics test signal. Units decibels. Interchannel Isolation measure crosstalk between channels. Measured each channel converter's output with signal input under test full-scale signal applied other channel. Units decibels. Frequency Response measure amplitude response variation from relative amplitude response kHz. Units decibels. Interchannel Gain Mismatch ADCs, difference input voltage that generates full scale code each channel. DACs, difference output voltages each channel with full scale digital input. Units decibels. Gain Error deviation from nominal full scale output full scale input. Gain Drift change gain value with temperature. Units ppm/°C. Offset Error ADCs, deviation LSB's output from mid-scale with selected input grounded. DAC's, deviation output from zero (relative CMOUT) with mid-scale input code. Units volts.
DS486PP2
CS4811
PACKAGE DIMENSIONS
100L MQFP PACKAGE DRAWING
INCHES -0.010 0.012 0.009 0.012 0.667 0.677 0.547 0.551 0.904 0.91 0.783 0.79 0.022 0.026 0.000° 4.00° 0.029 0.035 Nominal pitch 0.65 0.65 Controlling dimension JEDEC Designation: MS022 ASE/SPIL MILLIMETERS -0.30 0.30 17.20 14.00 23.20 20.0 0.65 4.00° 0.88
0.134 0.014 0.015 0.687 0.555 0.923 0.791 0.030 7.000° 0.041
-0.250 0.220 16.950 13.900 22.950 19.900 0.550 0.00° 0.73
3.400 0.350 0.380 17.450 14.100 23.450 20.100 0.750 7.00° 1.03
DS486PP2
Notes

Fixed Function Multi-Effects Audio Processor Audio Descripti

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