Phoenix Family AS9616-Sixteen-port 10/100M Ethernet Switch Contro

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Phoenix Family AS9616-Sixteen-port 10/100M Ethernet Switch Contro

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Phoenix Family
AS9616-Sixteen-port 10/100M Ethernet Switch Controller
Overview
AS9616, single chip, 10/100Mbps sixteen-port stand-alone switching controller which provides cost simple solution with high integration design. Sixteen-port reduced interfaces designed 10BASE/100BASE system. controller switch engines built chip. chip apply desktop workgroup applications each 10/100M port directly connects either 10BASE 100BASE devices. Furthermore, AS9616 breaks distance limitation 10BASE class 100BASE repeaters increases throughput.
Features
Non-blocking sixteen-port 10/100M switching controller with controller switching engine included cost
simple solution 100BASE-TX, 100BASE-FX, 10BASE applications. 10/100BASE reduced Interfaces. Speed auto-detect full/half duplex mode ports. Store-and- forward operation support. Full line speed capability 14880 packet/sec 148810 packet/sec 100M. Full-duplex (IEEE802.3x) three-way half-duplex flow control (Back pressure). Bridging functions such Local address filtering. direct mapping hashing scheme better address coverage. Short routing decision time. Aging function included with configurable aging time. Embedded entries address table. Buffer management included. 1024 blocks storing package 83MHz 256k SGRAM four SDRAM support external buffer memory Configurable IFG. Buffer full faulty provided. 93C46 EEPROM interface. power 3.3V, tolerance, CMOS technology. 208-pin PQFP package.
ADMtek Incorporated 99/12/28
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Phoenix Specification Block Diagram
N-WAY Monitor
EEPROM Configuration
Address Table
Link Table
Control Fabric
SDRAM/ SGRAM
From port port
TMAC RMAC TMAC RMAC
TMAC RMAC
From port port From port port
RMII
RMII
RMII
Example System Diagram
256K SGRAM 256K SGRAM
AS9616 16-port Switch
EEPROM
Quad PHYceiver
Quad PHYceiver
Quad PHYceiver
Quad PHYceiver
Transformer
Transformer
Transformer
Transformer
ADMtek Incorporated 99/12/28
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Phoenix Specification Diagram
D0[7] D0[15] D0[14] D0[13] D0[12] D0[16] D0[17] D0[18] D0[19] D0[11] D0[10] D0[9] D0[8] D0[20] D0[21] D0[22] D0[23] CAS# RAS# CLK_OUT ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 D1[8] D1[9] D1[10] D1[11] D1[23] D1[22] D1[21] D1[20] D1[12] D1[13] D1[14] D1[15] D1[19] D1[18]
D1[17] D1[16] D1[24] D1[25] D1[26] D1[27] D1[7] D1[6] D1[5] D1[4] D1[28] D1[29] D1[30] D1[31] D1[3] D1[2] D1[1] D1[0] RESET# TXE0 TXD0[0] TXD0[1] CRS_DV0 RXD0[0] RXD0[1] TXE1 TXD1[0] TXD1[1] CRS_DV1 RXD1[0] RXD1[1] TXE2 TXD2[0] TXD2[1] CRS_DV2 RXD2[0] RXD2[1] TXE3 TXD3[0] TXD3[1] CRS_DV3 RXD3[0] RXD3[1] TXE4 TXD4[0]
Phoenix
AS9616
D0[6] D0[5] D0[4] D0[24] D0[25] D0[26] D0[27] D0[3] D0[2] D0[1] D0[0] D0[28] D0[29] D0[30] D0[31] EEDO/NA16# EEDI/BP0 EECS/BP1 EESK/XFC# QFLED# RXD15[1] RXD15[0] CRS_DV15 TXD15[1] TXD15[0] TXE15 RXD14[1] RXD14[0] CRS_DV14 TXD14[1] TXD14[0] TXE14 RXD13[1] RXD13[0] CRS_DV13] TXD13[1] TXD13[0] TXE13 RXD12[1] RXD12[0] CRS_DV12 TXD12[1] TXD12[0] TXE12 RXD11[1] RXD11[0]
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CRS_DV11 TXD11[1] TXD11[0] TXE11 RXD10[1] RXD10[0] CRS_DV10 TXD10[1] TXD10[0] TXE10 RXD9[1] RXD9[0] CRS_DV9 TXD9[1] TXD9[0] TXE9 RXD8[1] RXD8[0] CRS_DV8 TXD8[1] TXD8[0] TXE8 MDIO REFCLK RXD7[1] RXD7[0] CRS_DV7 TXD7[1] TXD7[0] TXE7 RXD6[1] RXD6[0] CRS_DV6 TXD6[1] TXD6[0] TXE6 RXD5[1] RXD5[0] CRS_DV5 TXD5[1] TXD5[0] TXE5 RXD4[1] RXD4[0] CRS_DV4 TXD4[1]
Phoenix Specification General Description
AS9616 high performance, cost, quality assurance 16-port Fast Ethernet Controller which dedicated 16-port switch solutions. This chip operates 41.5MHz fully complies with IEEE series specifications included Physical layers. switch operations include forwarding scheme, packet filtering, address learning, buffer management, display, etc. Packets from reduced interface should stored memory. Then, source address learning, packet filtering, retransmission known unknown port(s) followed based real application.
Reduced
AS9616 supports Reduced standard interfaces each 10/100Mbps port. Reduced uses pins port, TXE0~15, TXD0~15[1:0], CRS_DV0~15, RXD0~15[1:0], plus reference clock, 50MHz.
Buffer Memory Interface
AS9616 offers 64-bit SDRAM/SGRAM data 9-bit address interface. SDRAM/SGRAM buffer 16-port switch includes output buffer queue only. entries look-up table embedded. Self-learning address recognition scheme selected either configurable hashing algorithms. buffer management, each packet occupies 2048 bytes, maximum length each packet determined engine 1536 bytes long programmable.
EEPROM Interface
EEPROM also option configuration settings 16-port switch.
Display
AS9616 supports buffer full faulty only assigned 133.
Operation Modes
Reduced interface PHYs transceivers operate 10/100Mbps full half duplex mode. keep consisted operation speed, these parts, switching controller, will automatically adjusted mode through MDC/MDIO pins. AS9616 also provided fixed speed operation mode configured EEPROM. modes allowed full wire speed operations without interference.
Flow Control Back pressure
AS9616 provides IEEE 802.3x flow control full-duplex mode back pressure half-duplex. back pressure, several settings chosen. This feature heightens traffic control ability ensures transmission warranty packets. Flow control enabled disabled regarding EEPROM settings.
Address Recognition
Self-learning bridge function based source address field packets. Look-up table different hashing algorithms strengthen bridge ability within high performance assurance. Configurable aging time supported also.
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Phoenix Specification Descriptions Name
Type
Descriptions
SDRAM/SGRAM Interface
Write Enable. signal defines operation commands conjunction with RAS# CAS# signals latched positive edges CLK_OUT. input used select BankActivate Precharge command Read Write command. Column Address Strobe. CAS# signal defines operation commands conjunction with RAS# signals latched positive edges CLK_OUT. When RAS# held "HIGH" asserted "LOW", column access started asserting CAS# "LOW". Then, Read Write command selected asserting "LOW" "HIGH". Address Strobe. RAS# signal defines operation commands conjunction with CAS# signals latched positive edges CLK_OUT. When RAS# asserted "LOW" CAS# asserted "HIGH", either BankActivate command Precharge command selected signal. When asserted "HIGH," BankActivate command selected bank designated turned active state. When asserted "LOW", Precharge command selected bank designated switched idle state after precharge operation. Chip Select. enables (sampled LOW) disables (sampled HIGH) command decoder. commands masked when sampled HIGH. Bank Select. defines which bank BankActivate, Read, Write, BankPrecharge command being applied. also used program 10th Mode Special Mode registers. SDRAM/SGRAM Address Output. ADDR[8:0] sampled during BankActivate command Read/Write command select location respective bank. During Precharge command, sampled determine both banks precharged HIGH). address inputs also provide op-code during Mode Register Special Mode Register command. SDRAM/SGRAM Data Input Output. D0~1[31:0] input output data synchronized with positive edges CLK_OUT.
CAS#
RAS#
ADDR [8:0]
183~191
D0[31:0] D1[31:0]
EEPROM Interface
EEDO/NA16# EEDI/BP0 EESK/XFC# EECS/BP1 EEDO: Data Output serial EEPROM. Internally pull (50K Ohm). Inputs configuration information AS9616.
EEDI: Data Input serial EEPROM. Internally pull down (50K Ohm). AS9616 outputs data EEPROM EESK: Clock input serial EEPROM. Internally pull AS9616 outputs clock signal EEPROM Chip Select serial EEPROM. Internally pull down.
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Phoenix Specification
Reduced Interface
TXE0 TXE1 TXE2 TXE3 TXE4 TXE5 TXE6 TXE7 TXE8 TXE9 TXE10 TXE11 TXE12 TXE13 TXE14 TXE15 TXD0[1:0] TXD1[1:0] TXD2[1:0] TXD3[1:0] TXD4[1:0] TXD5[1:0] TXD6[1:0] TXD7[1:0] TXD8[1:0] TXD9[1:0] TXD10[1:0] TXD11[1:0] TXD12[1:0] TXD13[1:0] TXD14[1:0] TXD15[1:0] 27,26 33,32 39,38 45,44 53,51 60,59 66,65 72,71 84,83 90,89 96,95 102,101 109,108 116,115 123,122 129,128 Transmit Data. These bundle signals output from AS9616 Reduced connecting device. These signals transmited synchronous with rising edge TXE0~15. When TXE0~15 asserts, then each period TXE0~15 AS9616 drives recovered encoded data into TXD0~15[1:0] transmission. While TXE0~15 de-asserted then TXD0~15[1:0] will have effect upon Reduced connecting device. TXD0~15[1:0] shall transition synchronously with respect REFCLK. When TXE0~15 asserted, TXD0~15[1:0] accepted transmission PHY. TXD0~15[1:0] shall "00" indicate idle when TXE0~15 deasserted. Values TXD0~15[1:0] other than "00" when TXE0~15 deasserted reserved out-of-band signalling defined). Values other than "00" TXD0~15[1:0] while TXE0~15 deasserted shall ignored PHY. Transmit Enable. TXE0~15 shows that AS9616 presenting recovered decoded data TXD0~15[1:0]. TXE0~15 indicates that presenting di-bits TXD0~15[1:0] Reduced transmission. TXE0~15 shall asserted synchronously with first nibble preamble shall remain asserted while di-bits transmitted presented Reduced MII. TXE0~15 shall negated prior first REFCLK rising edge following final di-bit frame. TXE0~15 shall transition synchronously with respect REFCLK.
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Phoenix Specification
CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 CRS_DV8 CRS_DV9 CRS_DV10 CRS_DV11 CRS_DV12 CRS_DV13 CRS_DV14 CRS_DV15 RXD0[1:0] RXD1[1:0] RXD2[1:0] RXD3[1:0] RXD4[1:0] RXD5[1:0] RXD6[1:0] RXD7[1:0] RXD8[1:0] RXD9[1:0] RXD10[1:0] RXD11[1:0] RXD12[1:0] RXD13[1:0] RXD14[1:0] RXD15[1:0] MDIO 30,29 36,35 42,41 48,47 56,55 63,62 69,68 75,74 87,86 93,92 99,98 106,105 112,111 119,118 126,125 132,131 Management Data Input/output. This provides channels AS9616 Transceivers transfer control information status. Management Data Clock. Provides reference clock MDIO signal. Receive Data. RXD2[1:0], RXD3[1:0], RXD5[1:0], RXD6[1:0], RXD7[1:0]. These bundle signals input from Reduced connecting device. RXD0~15[1:0] shall transition synchronously REFCLK. each clock period which CRS_DV0~15 asserted, RXD0~15[1:0] transfers bits recovered data from PHY. some cases (e.g. before data recovery during error conditions) pre-determined value RXD0~15[1:0] transferred instead recovered data. RXD0~15[1:0] shall "00" indicate idle when CRS_DV0~15 deasserted. Values RXD0~15[1:0] other than "00" when CRS_DV0~15 recovered from CRS_DV0~15 deasserted reserved out-of-band signalling defined). Values other than "00"on RXD0~15[1:0] while CRS_DV0~15 recovered from CRS_DV0~15 de-asserted shall ignored MAC. Upon assertion CRS_DV0~15, shall ensure that RXD0~15[1:0]="00"until proper receive decoding takes place. Carrier Sense Receive Data Valid. CRS_DV0~15 shall asserted when receive medium nonidle. specifics definition idle 10BASE-T 100BASE-X contained IEEE 802.3 IEEE 802.3u. CRS_DV0~15 also shows that receiving data presenting RXD0~15[1:0] from Reduced connecting device. CRS_DV0~15 asserted asynchronous detection carrier criteria relevant operating mode. That 10BASE-T mode, when squelch passed 100BASE-X mode when non-contiguous zeroes bits detected carrier said detected. Loss carrier shall result deassertion CRS_DV0~15 synchronous cycles REFCLK which presents first di-bit nibble onto RXD0~15[1:0]. additional bits presented RXD0~15[1:0] following initial deassertion CRS_DV0~15, then shall assert CRS_DV0~15 cycles REFCLK which present second di-bit each nibble deassert CRS_DV0~15 cycles REFCLK which present first di-bit nibble. During false carrier event, CRS_DV0~15 shall remain asserted duration carrier activity. data RXD0~15[1:0] considered valid once CRS_DV0~15 asserted. However, since assertion CRS_DV0~15 asynchronous relative REFCLK, data RXD0~15[1:0] shall "00" until proper receive signal decoding takes place.
Display
QFLED# Buffer Full Faulty Display. This happened when packet lost without flow control enable. flow control enabled PAUSE frames sent, buffer full will flashed. faulty found, will always (See function description)
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Phoenix Specification
Miscellaneous
CLK_OUT REFCLK Reset# 50MHz Reduced clock reference input. Synchronous clock reference receive, transmit, control interface. Reset#. Active low. power reset initiate AS9616 state machines statuses enter initial default state. Besides, will turned when power testing fail. 83MHz clock input system operation. only. 83MHz output clock SDRAM/SGRAM. internal system clock, 41.5MHz used
Power
113, 138, 147, 174, 181, 104, 120, 152, 156, 179, 192,
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Phoenix Specification EEPROM Content
EEPROM setting must 16-bit mode.
Offset
Content
Check Pattern System Configuration
Description
value this word must 3C03H. Initially, AS9616 reads this byte checks whether EEPROM existed not. Inter Frame half duplex mode only. Default zero time). sign bit. When zero, means negative. present decimal value time times four. example, 1010, equal 104. Configurable aging time. Default sec. When one, fast aging time, sec, set. zero, aging timer disable. others, list below. Aging time Aging time Aging time 1200 Aging time 2400 Aging time 4800 Aging time 9600 Aging time 38400 Reserved 10~9 Max_Length bit10 bit9 length 1536 (default) length 1518 length 1522 length 1548
Transmission abort after consecutive 16-collision Enable zero. Default zero. Hashing algorithm selection. zero, direct mapping algorithm chosen. Otherwise, hashing algorithm adopted. Default zero. Must Must
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Phoenix Specification
Back Pressure Bit[3:0] must 0001 Bit[7:4] must 0101 Bit[11:8] must 1010 mode disableBP jamALL carrier
must Auto-negotiation monitor port base auto-negotiation monitor. Default Stand autonegotiation monitor enable, e.g. port port When auto-negotiation monitor set, speed full/half operation will ignored. Speed Operation Speed operation, 10Mbps 100Mbps. port base. stands 100Mbps. Half/Full Operation Full/half operation. Each presents dedicated port number. Lower intends small port number. half duplex. 802.3x Flow Control 802.3x flow control enable port one. Lower Enable directly maps lower port number. value setting high priority than XFC# setting. 802.3x Flow Control Flow control write enable MDIO. Lower stands lower Write Enable port number. Default enable (1). indicated port enable port connected well AS9616 full duplex operation, will auto-negotiate with remote device decide final result flow control. disable, negotiation stopped. Reserved Must 000c (Hex) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Transceiver Configuration Must 0010 (Hex) Must 00d0 (Hex) Must 00f0 (Hex) Must 0190 (Hex) Must 01b0 (Hex) Must 0190 (Hex) Must 01b0 (Hex) extra written register address -Reserved extra written enable start address (default Reserved extra written data.
Transceiver Configuration
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Phoenix Specification Function Description
Reset Restart
When AS9616 power AS9616 initially goes SGRAM embedded memory self-test mode.
Port Interface 10/100Mbps Reduced Interface
Each port AS9616 also supports Reduced interfaces. features similar MII, different frequency well integration function. RMII specification following characteristics: capable supporting 10Mbps 100Mbps data rates single clock reference sourced from from external source) provides independent wide (di-bit) transmit receive data paths RMII Specification Signals Signal Name Direction with respect REFCLK Input
Direction with respect Usage Input Output Synchronous clock reference receive, transmit control interface CRS_DV Output Input Carrier Sense/Receive Data Valid RXD[1:0] Output Input Receive Data Input Output Transmit Enable TXD[1:0] Input Output Transmit Data detail description please assignment.
Media Access Control
AS9616 implement functions IEEE 802.3 protocol such frame formatting, collision handling, etc. AS9616 generates 56-bit preamble Start Frame delimiter while packet sending. half duplex mode, listening before transmitting prevent traffic jam. collision, packet will delay random time and, then, retransmit.
Automatic Address Learning, Forwarding, Filtering Function Address Recognition
entry hashing table calculated 32-bit polynomial, called hashing function, direct mapping, called simple hashing function, well address, called input data. Direct mapping function adopted lowest bits SA/DA address buffer address entry. Hashing function selection offset EEPROM. Each Destination Address, passes through hashing function gets 11-bit entry point embedded SRAM. record empty, packet broadcast, treated unknown frame. Otherwise, record read, then address storage from current packet compared. addresses same, port number decided, packet forward assigned port. addresses different, incoming packet unknown packet also. broadcast packet will pass through other port without address recognition.
Learning Process
Address learning process composed packets hashing function described before. each incoming packet, AS9616 will check whether packet errorless whether content entry address SRAM occupied. positive, packet will compare with source address, port number. both fields same information packet, aging status revised learned address. same addresses compared, port number different, port number re-assigned. When entry collided, address ignored record keeps one. Last possibility, record free, address port number incoming packet will stored. following diagram describes general operations address learning recognition.
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Phoenix Specification
[0:10] Address Entry Point
Direct Mapping Hashing Function
AAA-1 AAA+1 Address Look-up Table
Fig.
Address Learning Recognition
Forwarding Scheme
AS9616 forwarding scheme adopts store-and-forward method. Each determined outgoing packet buffer incoming port directly sent assigned port. forwarding scheme unknown packets treated same broadcast packet. AS9616 also obligates first- in-first-out service that packets will disorder.
IEEE 802.3x Congestion Control
half duplex operation, AS9616 supports back pressure feature. When buffer full, preamble signal, packet 802.3x control frame sent connected segment, which called back pressure. AS9616 implements Alternative back pressure based either three algorithms described EEPROM section. free blocks buffer memory equal below threshold, packet directly transmitted regardless routing decision. Full duplex flow control, AS9616 follows IEEE 802.3x standard. delay time PAUSE frame zero maximum value. feature allows AS9616 handle remote-side PAUSE frame. full duplex flow contol, state machine threshold values described EEPROM, too. octets octets octets octets 2octets octets
Destination Address
Source Address
Type Opcode
Pause Time
IEEE 802.3x PAUSE Frame Format
diagram showed above IEEE 802.3x Pause frame format. field listed below. Destination Address destination address (Generally content 0x0180c2000001) Source Addrress source address Type PAUSE frame type 0x8808 Opcode value fixed, 0x0001 (PAUSE operation) Pause Time number slot time zero AS9616, PAUSE frame received from certain port with 0x0180c2000001 0xFFFFFFFFFFFF, AS9616 will stop port transmitting packets counting timer until timeout another PAUSE frame with zero time. buffer full full duplex mode, AS9616 will send PAUSE frame with maximum delay time defer receiving packet. When enough buffer release, PAUSE frame with zero delay sent.
Auto-negotation Operations
When MDC/MDIO pins communicate with transceivers, AS9616 selected 10/100Mbps half/full duplex mode independently. Otherwise, AS9616 result auto-negotiation from PHYceiver adjust speed itself.
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Phoenix Specification Inter-Frame
idle time between continuous packets from same port. default value 10Mbps 9.6usec 0.96usec 100Mbps.
MDC, MDIO Interface AS9616
MDIO
MDIO
Fig.
specific application Serial Management Interface
There pins Serial Management Interface AS9616. MDC, Management Data Clock, input pin. functions Reduced interface device. MDIO bi-direction reduced interface device. following conditions true, AS9616 will write register with register with connected transceiver. First, IEEE 802.3x flow control enable. Secondly, port number Flow Control Write EEPROM offset enabled. Last, AS9616 full duplex operation well same operation Transceiver. After write operation through MDIO, auto-negotiation restarted AS9616 gain information remote 802.3x flow control. Finally, final operation flow control determined.
Interface
AS9616 supports only which presents buffer full test fault. When AS9616 reset, state. While SGRAM/SDRAM testing mode, SGRAM/SDRAM test fail, will flash time, around sec, keep Next, embedded SRAM testing fail, will flash twice, around 1.6sec. After tests done passed, status down, around minimum. back pressure full duplex flow control set, buffer full will flash every 200ms keep based packet PAUSE frame sent. arrival packet dropped, will flash every 50ms keep long.
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Phoenix Specification Absolute Maximum Ratings
Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature Protection -0.5 -0.5 -0.5 C(-85 302° C(32 158° 2000V
Specifications
Parameter
Cinp Lpinp
Description
Supply Voltage Power Supply Input Voltage Input HIGH Voltage Input Leakage Current Input HIGH Leakage Current Output Voltage Output HIGH Voltage Input Capacitance Inductance
Condition
3.3V
-0.5
Typical
Units
0.8V 2.0V Iout =2~8mA Iout =-2~-8mA
Specifications
SGRAM/SDRAM Read Timing
ACTIVE
READ
ACTIVE
A0-A7
BANK
DISABLE AUTO PRECHARGE BANK
BANK
BANK
BANK(S)
BANK
Dout
latency
UNDEFINED
NOTE: this example, burst length latency READ burst followed "manual" PRECHARGE. ADMtek Incorporated 99/12/28 Industrial Road, SBIP, HsinChu Version 0.25 (03)578-8879 (03)578-8871
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Phoenix Specification
Parameters
Units
120,000
SGRAM/SDRAM Write Timing
ACTIVE
READ
ACTIVE
A0-A7
BANK
DISABLE AUTO PRECHARGE BANK
BANK
BANK
BANK(S)
BANK
UNDEFINED
NOTE: this example, burst length WRITE burst followed "manual" PRECHARGE.
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Phoenix Specification
Parameters
Units
120,000
EEPROM Timing
EECK
EECS EEDI
EEDO
Parameter
Description
EESK (50% duty cycle) EECS/EEDI delay from falling EESK idle time EECS EEDO valid before rising EESK EEDO hold after rising EESK
Condition
Clock 83MHz Clock 83MHz Clock 83MHz
4000
Units
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Phoenix Specification
RMII Transmit Receive Timing
REF_CLK TX_EN
TXD(1)
TXD(0)
Preamble
Data
REF_CLK CRS_DV
RXD(1)
RXD(0)
Preamble
Data
Symbol
Thold
Parameter
REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN, RXD[1:0], CRS_DV, Data setup REF_CLK rising edge TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, Data hold from REF_CLK rising edge
Type
Units
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Phoenix Specification AS9616 Package
ADMtek Incorporated 99/12/28
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Phoenix Family AS9616-Sixteen-port 10/100M Ethernet Switch Contro

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