Olive Family LES108 Eight-port 10/100M Ethernet Switch Controller

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Olive Family LES108 Eight-port 10/100M Ethernet Switch Controller

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Olive Family
LES108 Eight-port 10/100M Ethernet Switch Controller
Overview
Olive, single chip, 10/100Mbps eight-port stand-alone switching controller which provides cost simple solution with high integration design. Eight configurable reduced interfaces designed 10BASE/100BASE ports. controller switch engines built chip. chip apply desktop SOHO application each 10/100M port directly connects either 10BASE 100BASE devices. Furthermore, Olive breaks distance limitation 10BASE class 100BASE repeaters increases throughput.
Features
Non-blocking eight-port 10/100M switching controller with controller switching engine included cost simple solution 100BASE-TX, 100BASE-FX, 10BASE applications. Configurable 10/100BASE 10/100BASE reduced Interfaces. Speed auto-detect full/half duplex mode ports. Store-and- forward operation support. Full line speed capability 14880 packet/sec 148810 packet/sec 100M. Full-duplex (IEEE802.3x) three-way half-duplex flow control (Back pressure). Bridging functions such Local address filtering. direct mapping hashing scheme better address coverage. Short routing decision time. Aging function included with configurable aging time. Embedded entries address table. Buffer management included. block storing package 83MHz 256k 512k SGRAM support external buffer memory. Buffer full faulty provided. 93C46 EEPROM interface. power 3.3V, tolerance, CMOS technology. 208-pin Plastic Quad Flat Package.
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Olive Specification
Block Diagram
N-WAY Monitor EEPROM
Link
Link List
Address Table
Configuration SGRAM
Command Queue/ Link Control
From port port
TMAC RMAC TMAC RMAC
TMAC RMAC From port port
RMII
RMII
RMII
From port port
Example System Diagram
256K SGRAM
Olive 8-port Switch
EEPROM
Quad PHYceiver
Quad PHYceiver
Transformer
Transformer
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Olive Specification
Diagram
CAS# RAS# CLK_OUT ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3
ADDR2 ADDR1 ADDR0 RESET# CRS0 COL0 TXE0 TXD0[0] TXD0[1] TXD0[2] TXD0[3] TXC0 RXC0 RXDV0 RXD0[0] RXD0[1] RXD0[2] RXD0[3] CRS1 COL1 TXE1 TXD1[0] TXD1[1] TXD1[2] TXD1[3] TXC1 RXC1 RXDV1 RXD1[0] RXD1[1] RXD1[2] RXD1[3] CRS2 COL2 TXE2 TXD2[0] TXD2[1] TXD2[2] TXD2[3]
LES108
Olive
EEDO/NA16# EEDI/BP0 EECS/BP1 EESK/XFC# QFLED# MDIO RXD7[3] RXD7[2] RXD7[1] RXD7[0] RXDV7 RXC7 TXC7 TXD7[3] TXD7[2] TXD7[1] TXD7[0] TXE7 COL7 CRS7 RXD6[3] RXD6[2] RXD6[1] RXD6[0] RXDV6 RXC6 TXC6 TXD6[3] TXD6[2] TXD6[1] TXD6[0] TXE6 COL6 CRS6 RXD5[3] RXD5[2] RXD5[1] RXD5[0] RXDV5 RXC5
ADMtek Incorporated 99/09/13
TXC5 TXD5[3] TXD5[2] TXD5[1] TXD5[0] TXE5 COL5 CRS5 RXD4[3] RXD4[2] RXD4[1] RXD4[0] RXDV4 RXC4 TXC4/REFCLK TXD4[3] TXD4[2] TXD4[1] TXD4[0] TXE4 COL4 CRS4 RMII# RXD3[3] RXD3[2] RXD3[1] RXD3[0] RXDV3 RXC3 TXC3 TXD3[3] TXD3[2] TXD3[1] TXD3[0] TXE3 COL3 CRS3 RXD2[3] RXD2[2] RXD2[1] RXD2[0] RXDV2 RXC2 TXC2
Active
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Olive Specification
General Description
LES108 high performance, cost, quality assurance 8-port Fast Ethernet Controller which dedicated 8-port switch solutions. This chip operates 41.5MHz fully complies with IEEE series specifications included Physical layers. switch operations include forwarding scheme, packet filtering, address learning, buffer management, display, etc. Packets from MII, Reduced interface should stored memory. Then, source address learning, packet filtering, retransmission known unknown port(s) followed based real application.
Reduced
LES108 supports standard interfaces each port, which Reduced 10/100Mbps. Reduced uses pins, TXE0~7, TXD0~7[1:0], RXDV0~7, RXD0~7[1:0], shared MII. Feature setting chosen configuration pin.
Buffer Memory Interface
LES108 offers 32-bit SDRAM/SGRAM data 9-bit address interface. SDRAM/SGRAM buffer eight port switch includes output buffer queue only. entries look-up table embedded Olive. Self-learning address recognition scheme selected either configurable hashing algorithms. buffer management, each packet occupies 2048 bytes, memory maximum length each packet determined engine which 1536 bytes long.
EEPROM Interface
EEPROM also option configuration settings 8-port switch.
Display
Olive supports buffer full faulty only assigned 146.
Operation Modes
Both Reduced interfaces PHYs transceivers operate 10/100Mbps full half duplex mode. keep consisted operation speed, these parts, switching controller, will automatically adjusted mode through MDC/MDIO pins. Olive also provided fixed speed operation mode configured EEPROM. modes allowed full wire speed operations without interference.
Flow Control Back pressure
LES108 provides IEEE 802.3x flow control full-duplex mode back pressure half-duplex. back pressure, several settings chosen. This feature heightens traffic control ability ensures transmission warranty packets. Flow control enable disable regards EEPROM settings.
Address Recognition
Self-learning bridge function based source address field packets. Look-up table different hashing algorithms strengthen bridge ability within high performance assurance. Configurable aging time supported also.
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Olive Specification
Descriptions
Name Type Descriptions
SDRAM/SGRAM Interface
Data Input/Output Mask. byte specific, nonpersistent buffer controls. buffers placed high-z state when sampled HIGH. Write Enable. signal defines operation commands conjunction with RAS# CAS# signals latched positive edges CLK_OUT. input used select BankActivate Precharge command Read Write command. Column Address Strobe. CAS# signal defines operation commands conjunction with RAS# signals latched positive edges CLK_OUT. When RAS# held "HIGH" asserted "LOW", column access started asserting CAS# "LOW". Then, Read Write command selected asserting "LOW" "HIGH". Address Strobe. RAS# signal defines operation commands conjunction with CAS# signals latched positive edges CLK_OUT. When RAS# asserted "LOW" CAS# asserted "HIGH", either BankActivate command Precharge command selected signal. When asserted "HIGH," BankActivate command selected bank designated turned active state. When asserted "LOW", Precharge command selected bank designated switched idle state after precharge operation. Chip Select. enables (sampled LOW) disables (sampled HIGH) command decoder. commands masked when sampled HIGH. Bank Select. defines which bank BankActivate, Read, Write, BankPrecharge command being applied. also used program 10th Mode Special Mode registers.
CAS#
RAS#
ADDR0~8
SDRAM/SGRAM Address Output. ADDR0~8 sampled during BankActivate 208, command Read/Write command select location respective bank. During 205, Precharge command, sampled determine both banks precharged 203, HIGH). address inputs also provide op-code during Mode Register Special Mode Register command. 154,153 SDRAM/SGRAM Data Input Output. D0~31 input output data 152,161 synchronized with positive edges CLK_OUT. 162,164 170,172 188,186 185,184 179,178 177,176 173,174 181,182 189,190 191,192 169,167 166,165 159,158 157,155
D0~31
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Olive Specification
EEPROM Interface
EEDO EEDI EESK EECS EEDO: Data Output serial EEPROM. Internally pull (50K Ohm). Inputs configuration information Olive.
EEDI: Data Input serial EEPROM. Internally pull down (50K Ohm). Olive outputs data EEPROM EESK: Clock input serial EEPROM. Internally pull Olive outputs clock signal EEPROM Chip Select serial EEPROM. Internally pull down. EECK/s:50ns, h:0ns
Interface
TXC0 TXC1 TXC2 TXC3 TXC4 TXC5 TXC6 TXC7 TXE0 TXE1 TXE2 TXE3 TXE4 TXE5 TXE6 TXE7 TXD0[3:0] TXD1[3:0] TXD2[3:0] TXD3[3:0] TXD4[3:0] TXD5[3:0] TXD6[3:0] TXD7[3:0] 120,136 Transmit Clock. Internally pull down except TXC4. TXC0~7 continuous clock that provides reference clock transfer TXE0~7 TXD0~7[3:0] from connecting device. This clock comprised Olive transmit clock generator.
Transmit Enable. TXE0~7 shows that Olive presenting recovered decoded data TXD0~7[3:0]. TXE0~7 synchronous with rising edge TXC0~7 encompass receiving frame asserting signal, starting later than start frame delimiter 113, excluding frame delimiter.
Transmit Data. These bundle signals output from Olive connecting device. These signals transited synchronous with rising edge TXC0~7. When TXE0~7 asserts, then each period TXC0~7 Olive drives recovered encoded data into TXD0~7[3:0] transmission. While TXE0~7 de-asserted then TXD0~7[3:0] will have effect upon connecting device. 101, 115, 117, 131, 133,
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Olive Specification RXC0 RXC1 RXC2 RXC3 RXC4 RXC5 RXC6 RXC7 RXDV0 RXDV1 RXDV2 RXDV3 RXDV4 RXDV5 RXDV6 RXDV7 RXD0[3:0] RXD1[3:0] RXD2[3:0] RXD3[3:0] RXD4[3:0] RXD5[3:0] RXD6[3:0] RXD7[3:0] 121, Receive Clock. Internally pull down. RXC0~7 continuous clock that provides reference clock transfer RXDV0~7 RXD0~7[3:0] from connecting device.
122,
Receive Data Valid. RXDV2, RXDV3, RXDV5, RXDV6, RXDV7 internally pull down. RXDV0~7 shows that receiving data presenting RXD0~7[3:0] from connecting device. RXDV0~7 synchronous with rising edge RXC0~7 encompasses receiving frame asserting signal, starting later than start frame delimiter excluding frame delimiter.
107, 109, 123, 125, 139, 141, 111,
Receive Data. RXD0[3:2], RXD1[3:2], RXD4[3:2], RXD2~3[3:0], RXD5~7[3:0] internally pull down. These bundle signals input from connecting device. These signals transited synchronous with rising edge RXC0~7. These pins will high impedance ignores input when RXDV0~7 negated.
CRS0 CRS1 CRS2 CRS3 CRS4 CRS5 CRS6 CRS7
Carrier Sense. Internally pull down. CRS0~7 active when either transmit receive medium carrier been sensed will negated when both transmit receive media idle. CRS0~7 active high input from connecting device.
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Olive Specification COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 MDIO 112, Collision Detection. Internally pull down. COL0~7 active when carrier collision medium. This active signal will remained till collision condition. COL0~7 active high input from connecting device.
Management Data Clock. Provides reference clock MDIO signal. Management Data Input/output. This provides channels Olive Transceivers transfer control information status.
Reduced Interface
TXE0 TXE1 TXE2 TXE3 TXE4 TXE5 TXE6 TXE7 TXD0[1:0] TXD1[1:0] TXD2[1:0] TXD3[1:0] TXD4[1:0] TXD5[1:0] TXD6[1:0] TXD7[1:0] Transmit Enable. TXE0~7 shows that Olive presenting recovered decoded data TXD0~7[1:0]. TXE0~7 indicates that presenting di-bits TXD0~7[1:0] Reduced 113, transmission. TXE0~7 shall asserted synchronously with first nibble preamble shall remain asserted while di-bits transmitted presented Reduced MII. TXE0~7 shall negated prior first REFCLK rising edge following final di-bit frame. TXE0~7 shall transition synchronously with respect REFCLK.
Transmit Data. These bundle signals output from Olive Reduced connecting device. These signals transited synchronous with rising edge TXE0~7. When TXE0~7 asserts, then each period TXE0~7 Olive drives recovered encoded data into TXD0~7[1:0] transmission. While TXE0~7 de-asserted then TXD0~7[1:0] will have effect upon Reduced connecting device. TXD0~7[1:0] shall transition synchronously with respect REFCLK. When TXE0~7 115, asserted, TXD0~7[1:0] accepted transmission PHY. TXD0~7[1:0] shall 131, "00" indicate idle when TXE0~7 deasserted. Values TXD0~7[1:0] other than "00" when TXE0~7 deasserted reserved out-of-band signalling defined). Values other than "00" TXD0~7[1:0] while TXE0~7 deasserted shall ignored PHY.
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Olive Specification RXDV0 RXDV1 RXDV2 RXDV3 RXDV4 RXDV5 RXDV6 RXDV7 122, Carrier Sense Receive Data Valid. RXDV2, RXDV3, RXDV5, RDDV6, RXDV7 internally pull down. RXDV0~7 shall asserted when receive medium nonidle. specifics definition idle 10BASE-T 100BASE-X contained IEEE 802.3 IEEE 802.3u. RXDV0~7 also shows that receiving data presenting RXD0~7[1:0] from Reduced connecting device. RXDV0~7 asserted asynchronous detection carrier criteria relevant operating mode. That 10BASE-T mode, when squelch passed 100BASE-X mode when non-contiguous zeroes bits detected carrier said detected. Loss carrier shall result deassertion RXDV0~7 synchronous cycles REFCLK which presents first di-bit nibble onto RXD0~7[1:0]. additional bits presented RXD0~7[1:0] following initial deassertion RXDV0~7, then shall assert RXDV0~7 cycles REFCLK which present second di-bit each nibble deassert RXDV0~7 cycles REFCLK which present first di-bit nibble. During false carrier event, RXDV0~7 shall remain asserted duration carrier activity. data RXD0~7[1:0] considered valid once RXDV0~7 asserted. However, since assertion RXDV0~7 asynchronous relative REFCLK, data RXD0~7[1:0] shall "00" until proper receive signal decoding takes place. Receive Data. RXD2[1:0], RXD3[1:0], RXD5[1:0], RXD6[1:0], RXD7[1:0] internally pull down. These bundle signals input from Reduced connecting device. RXD0~7[1:0] shall transition synchronously REFCLK. each clock period which RXDV0~7 asserted, RXD0~7[1:0] transfers bits recovered data from PHY. some cases (e.g. before data recovery during error conditions) pre-determined value RXD0~7[1:0] transferred instead recovered data. RXD0~7[1:0] shall "00" indicate idle when RXDV0~7 deasserted. Values RXD0~7[1:0] other than "00" when RXDV0~7 recovered from RXDV0~7 deasserted reserved out-of-band signalling defined). Values other than "00"on RXD0~7[1:0] while RXDV0~7 recovered from RXDV0~7 de-asserted shall ignored MAC. Upon assertion RXDV0~7, shall ensure that RXD0~7[1:0]="00"until proper receive decoding takes place. These pins will high impedance ignores input when RXDV0~7 negated.
RXD0[1:0] RXD1[1:0] RXD2[1:0] RXD3[1:0] RXD4[1:0] RXD5[1:0] RXD6[1:0] RXD7[1:0]
107, 123, 139,
Display
QFLED# Buffer Full Faulty Display. This happened when packet lost without flow control 12ma enable. flow control enabled PAUSE frames sent, buffer full will flashed. faulty found, will always (See function description)
Configuration
Back Pressure Mode. Internally pull down. BP0~1 modes define different back pressure methods. Each BPA1~3 different algorithm described EEPROM section. following shows Olive configuration back pressure. Back Pressure Disable BPA1 (Back Pressure Algorithm Enable BPA2 (Back Pressure Algorithm Enable BPA3 (Back Pressure Algorithm Enable Full Duplex Flow Control. Internally pull When 802.3x flow control disable, PAUSE frame will sent. (default)
XFC#
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Olive Specification NA16# RMII# Abort after continuous 16-time collision pull down. Internally pull
Reduced Selection. Internally pull Active low. This tied reversing Reduced MII. There internal pull high default configuration.
Miscellaneous
CLK_OUT REFCLK Reset# 83MHz clock input system operation. only. 83MHz output clock SDRAM/SGRAM. 50MHz Reduced clock reference input. Synchronous clock reference receive, transmit, control interface. Reset#. Active low. power reset initiate Olive state machines statuses enter initial default state. Besides, will turned when power testing fail. internal system clock, 41.5MHz used
Power
114, 119, 143, 156, 160, 168, 180, 183, 193, 103, 130, 135, 151, 163, 171, 175, 187,
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Olive Specification
EEPROM Content
EEPROM setting must 16-bit mode.
Offset
Content
Check Pattern System Configuration
Description
value this word AD39H. Initially, Olive reads this byte checks whether EEPROM existed not. Configurable (Inter Frame Gap). Default time without EEPROM. sign bit. positive zero negative. equal 96-bit time plus minus value other bits times four. example, when value 0010, Configurable aging time. Default sec. When one, means Fast aging time, sec, set. zero, aging timer disable. Aging time Aging time Aging time 1200 Aging time 2400 Aging time 4800 Aging time 9600 Aging time 38400 Continuous 16-time collision abort packet enable zero. Default zero. EEPROM setting higher priority than pin's. Hashing algorithm selection. one, direct mapping algorithm chosen. Otherwise, hashing algorithm adopted. Default one.
Other bits Back Pressure Back- Must 1010. Must 1010. Back pressure mode selected. same 149, BP0. same 148, BP1. These bits have high priority change back pressure mode regardless these pin's settings. Back-off algorithm disable only buffer full. Default zero. function this disabled. Force back-off. Default zero, force. Reserved. Must one. Reserved. Must zero. Other bits Must 11001000. 802.3x flow control enable port one. Lower directly maps lower port number. value setting high priority than XFC# setting. Speed operation, 10Mbps 100Mbps. port. stands 100Mbps. Auto-negotiation. Default stands auto-negotiation enable. port. e.g. port port When auto-negotiation set, speed full/half operation will ignored. (03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
802.3x Flow Control
Auto-negotiation
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Olive Specification Auto-negotiation
Full/half operation. Each presents dedicated port number. Lower intends small port number. half duplex. Flow control write enable MDIO. Lower stands lower port number. Default enable (1). indicated port enable port connected well Olive full duplex operation, will auto-negotiate with remote device decide final result flow control. disable, negotiation stopped. Must 10000000. Must 11000000. Must 10000000. Must 11000000. Must 10000000. Must 11000000. rewrite register address. These bits present register address selection. rewrite enable. Default zero (disable). start Default 04H. This means from sequence default value set. Remember start always keep consistent first port setting PHY. N/A. rewrite data. After rewrite register address selected, register each port rewrite data.
Reserved Reserved Reserved Transceiver Configuration
Transceiver Configuration
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Olive Specification
Function Description
Reset Restart
When Olive power Olive initially goes SGRAM embedded memory self-test mode.
Port Interface 10/100Mbps Interface
Olive provides interfaces without glue logic directly connect Reduced interface. LES108 capable result full auto-negotiation from automatically adjust speed itself. port forced operate certain mode controlled EEPROM settings. Data paths each transmission reception 4-bit width. Transfer clock rate 10Mbps 2.5MHz 100Mbps 25MHz. clock inputs driven determinate auto-negotiation. Each interface compliant IEEE 802.3 standard following characteristics. able support both 10Mbps 100Mbps either half full duplex mode Data delimiters synchronous clock reference MDC/MDIO management interface Driving capability with limited length shield cable basic description listed below. Carrier sense Indicate activity cable, either incoming outgoing. Driven transceiver. Collision half-duplex transceivers, indicate simultaneous transmission reception. Full-duplex transceivers never activate this signal. Driven transceiver. enable switch while transmitting. clock 25MHz 100Base-T. Driven transceiver. continuously. data 4-bit width data path while packet transmitting. clock 25MHz 100base-T. Driven transceiver. continuously. data valid: transceiver while receiving valid packet. presence carrier sense, data valid, indicates reception broken packet headers, probably wiring broken transceiver. data 4-bit data path while receiving packet MDC, MDIO Serial management interface. host drives MDIO operation bi-directional. Every incorporates simple, two-wire serial control bus, called management interface. Using management interface, adapter card gather status from transceiver, also control transceiver. management interface consists MDIO wires connector.
10/100Mbps Reduced Interface
Each port Olive also supports Reduced interfaces. only features similar MII, also assignment same. system design level, Reduced interface chosen RMII# pins. RMII specification following characteristics: capable supporting 10Mbps 100Mbps data rates single clock reference sourced from from external source) provides independent wide (di-bit) transmit receive data paths RMII Specification Signals Signal Name REFCLK RXDV0~7 RXD0~7[1:0] Direction with respect Input Output Output Direction with respect Usage Input Output Synchronous clock reference receive, transmit control interface Input Carrier Sense/Receive Data Valid Input Receive Data
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Olive Specification TXE0~7 Input Output TXD0~7[1:0] Input Output detail description please assignment. Transmit Enable Transmit Data
Media Access Control
LES108 implement functions IEEE 802.3 protocol such frame formatting, collision handling, etc. Olive generates 56-bit preamble Start Frame delimiter while packet sending. half duplex mode, listening before transmitting prevent traffic jam. collision, packet will delay random time and, then, retransmit.
Automatic Address Learning, Forwarding, Filtering Function Address Resolution Table
architecture address look-up table listed below. size, 53bit, fixed Olive.
Port Aging Status
Address
Fig. Content Address Look-up Table address (Source Address Ethernet Packet) Aging status Aging status invalid (The record free called empty record) learned address address, record been established before Reserved Port number source address
Address Recognition
entry hashing table calculated 32-bit polynomial, called hashing function, direct mapping, called simple hashing function, well address, called input data. Direct mapping function adopted lowest bits SA/DA address buffer address entry. Hashing function selection offset EEPROM. Each Destination Address, passes through hashing function gets 10-bit entry point embedded SRAM. record empty, packet broadcast, treated unknown frame. Otherwise, record read, then address storage from current packet compared. addresses same, port number decided, packet forward assigned port. addresses different, incoming packet unknown packet also. broadcast packet will pass through other port without address recognition.
Learning Process
Address learning process composed packets hashing function described before. each incoming packet, Olive will check whether packet errorless whether content entry address SRAM occupied. positive, packet will compare with source address, port number. both fields same information packet, aging status revised learned address. same addresses compared, port number different, port number re-assigned. When entry collided, address ignored record keeps one. Last possibility, record free, address port number incoming packet will stored. following diagram describes general operations address learning recognition.
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Olive Specification [0:9] Address Entry Point
Direct Mapping Hashing Function
AAA-1 AAA+1 Address Look-up Table
Fig.
Address Learning Recognition
Aging Time
Olive automatically examine status address look-up table. round robin speed, checking timer, depends aging time setting EEPROM. normal, Olive aging time configurable with seconds unit least fast aging time seconds. Aging time also enable disable depending system requirement. When enabled, this guaranty requiring free spaces released from occupied address entries. Aging time operation works following state machine. Empty (00) Olive updates aging status Packets with same (10) Fig. (01) Packets with same
Olive updates aging status
Aging Timer State Machine
beginning, aging status empty (00) state. This means record look-up table free. When first packet with occupied this record, aging state changed next state, (01). Suppose incoming packets with same processed (01) state, aging status will keep current state. Each time, aging timer scans record changes current state next state, either (10) (00) state. When aging status back (00) state, means record aging out. incoming packet goes into Olive with same status (10) state, status will changed (01) state again.
Forwarding Scheme
Olive forwarding scheme adopts store-and-forward method. Each determined outgoing packet buffer incoming port directly sent assigned port. forwarding scheme unknown packets treated same broadcast packet. Olive also obligates first- in-first-out service that packets will disorder.
Buffer Management Queues Link List Table Multicast-link Table
Olive includes buffer management function inside. embedded tables show below.
Next Link Address
Multicast Fig.
Packet Length Link List Table Format
Destination Port
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Olive Specification
Port link Port link Port link Port link Port link Port link Port link Port link Address Address Address Address Address Address Address Address Fig. Multicast Link Table Format
Olive buffer divided into blocks each block contains 2048 bytes, space storing packet. manage buffer, link list multicast link tables take over function. sizes link list multicast tables bit.
Link List Table
Next Link Address address point next record Next Link Address Multicast show packet status current block, unicast multicast. Packet Length length current packet storing block memory. Destination Port outgoing port packet.
Multicast Link Table
Multicast Link Table used multicast, broadcast, unknown packets. When multicast packet records Link List Table Multicast set. Then, Next Link Address will point Multicast Link Table meaning each field Multicast Link Table showed below. Port Link Address each field stands current multicast packet destination port content points entry address Link List Table.
Buffer Management
Olive buffer size each port decided incoming packets from port available block number. Olive inside also several registers like Header, Tail, Packet Count pointers each port free link. Initially, empty records Link List Table chained together. incoming unicast packet arrived, free block will released from free link free packet count decreases one. Next, port link list incoming packet will record Link List Table tail. Then, packet count will increase one. packet been transmitted, block controlled free link again. Free Link Header Tail Packet Count Port Header Tail Packet Count
Link List Table
Multicast Link Table SGRAM/SDRAM Buffer Fig. Port Buffer Management
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Olive Specification
diagram above shows example buffer management function. multicast, broadcast, unknown packets, Multicaast Link Table used. pointer outgoing port field Multicast Link record directly indicates entry Link List Table. Initially, Multicast Link Table chain together control three registers, Header, Tail, Counter. fetch record from Multicast Link Table, Header register will point next record Counter decrease one. After packet sent multi-ports, record released. This record will free link list.
IEEE 802.3 Congestion Control
half duplex operation, Olive supports back pressure feature. When buffer full, packet 802.3x control frame sent connected segment, which called back pressure. Olive implements Alternative back pressure based either three algorithms described EEPROM section. free blocks buffer memory equal below threshold, packet directly transmitted regardless routing decision. Olive, select back pressure algorithm. Each back pressure algorithm list below. means released path from current state next one. means fetched path from current state next one. BPA1 adopted carrier sense solution. When buffer face congestion, Phoenix will generate preamable onto desired input port(s). length preamable time length preamable signals. BPA2 Idle BPA3 Idle
Back Pressure State Machine
Initially, back pressure algorithms started Idle state. express transition condition. Both include instructions. means every packets jammed, then packet will passed from source port destination port. presents packets will jammed entering state. free buffer blocks chip less than 128, BPA2 BPA3 will transit from Idle free buffer blocks over 192, BPA2 BPA3 will transit from Idle. Full duplex flow control, Olive follows IEEE 802.3x standard. delay time PAUSE frame zero maximum value. feature allows Olive handle remote-side PAUSE frame. full duplex flow control, state machine threshold values described EEPROM, too. octets octets octets octets 2octets octets
Destination Address
Source Address
Type Opcode
Pause Time
IEEE 802.3x PAUSE Frame Format
diagram showed above IEEE 802.3x Pause frame format. fields listed below. Destination Address destination address (Generally content 0x0180C2000001)
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Olive Specification Source Address source address Type PAUSE frame type 0x8808 Opcode value fixed, 0x0001 (PAUSE operation) Pause Time number slot time zero
Olive, PAUSE frame received from certain port with 0x0180C2000001 0xFFFFFFFFFFFF, Olive will stop port transmitting packets counting timer until timeout another PAUSE frame with zero time. buffer full full duplex mode, Olive will send PAUSE frame with maximum delay time defer receiving packet. When enough buffer release, PAUSE frame with zero delay sent. 802.3x flow control algorithm listed below. Initially, flow control operation idle state after this function enabled. PAUSE frame will active F1transition condition true. escape PAUSE frame activity, transition condition reached. Idle PAUSE 802.3x Flow Control State Machine
When 802.3x flow control threshold less than free blocks, state will transit from idle state PAUSE frame activity (F1). When 802.3x flow control threshold over free blocks, state will transit from PAUSE frame activity idle state (R1).
Auto-negotiation Operations
When MDC/MDIO pins communicate with transceivers, Olive selected 10/100Mbps half/full duplex mode independently. Otherwise, Olive result auto-negotiation from PHYceiver adjust speed itself.
Inter-Frame
idle time between continuous packets from same port. default value 10Mbps 9.6usec 0.96usec 100Mbps.
MDC, MDIO Interface
Phoenix MDIO
MDIO
Fig. specific application Serial Management Interface
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive Specification
There pins Serial Management Interface Olive. MDC, Management Data Clock, input pin. functions interface device. MDIO bi-direction interface device. following conditions true, Olive will write register with register with connected transceiver. First, IEEE 802.3x flow control enable. Secondly, port number Flow Control Write EEPROM offset enabled. Last, Olive full duplex operation well same operation Transceiver. After write operation through MDIO, auto-negotiation restarted Olive gain information remote 802.3x flow control. Finally, final operation flow control determined.
Interface
Olive supports only which presents buffer full test fault. When Olive reset, state. While SGRAM/SDRAM testing mode, SGRAM/SDRAM test fail, will flash time, around sec, keep Next, embedded SRAM testing fail, will flash twice, around 1.6sec. After tests done passed, status down, around minimum. back pressure full duplex flow control set, buffer full will flash every 200ms keep based packet PAUSE frame sent. arrival packet dropped, will flash every 50ms keep long.
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive Specification
-0.5 -0.5 -0.5 °C(-85°F 302°F) 70°C(32°F 158°F) 2000V
Absolute Maximum Ratings
Supply Voltage(Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature Protection
Specifications
Parameter
Cinp Lpinp
Description
Condition
-0.5
Typical
Units
Supply Voltage Power Supply 3.3V Input Voltage Input HIGH Voltage Input Leakage Current 0.8V Input HIGH Leakage Current 2.0V Output Voltage Iout =2~8mA Output HIGH Voltage Iout =-2~-8mA Input Capacitance Inductance
Specifications
SGRAM/SDRAM Read Timing
READ WITHOUT AUTO PRECHARGE
READ
COMMAND
ACTIVE
PRECHARGE
ACTIVE
COLUMN
A0-A7
BANK
DISABLE AUTO PRECHARGE BANK
BANK
BANK
BANK(S)
BANK
Dout
Dout
Dout
Dout
latency
UNDEFINED
NOTE: this example, burst length latency READ burst followed "manual" PRECHARGE.
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive Specification
Parameters
Units
tCKH tCKS tCMH tCMS tRAS tRCD
120,000
SGRAM/SDRAM Write Timing
READ
COMMAND
ACTIVE
PRECHARGE
ACTIVE
A0-A7
COLUMN
BANK
DISABLE AUTO PRECHARGE BANK
BANK
BANK
BANK(S)
BANK
UNDEFINED
NOTE: this example, burst length WRITE burst followed "manual" PRECHARGE.
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive Specification
Parameters
Units
tCKH tCKS tCMH tCMS tRAS tRCD
120,000
EEPROM Timing
EECK
EECS EEDI
EEDO
Parameter
Description
EECK (50% duty cycle) EECS/EEDI delay from falling EECK idle time EECS EEDO valid before rising EECK EEDO hold after rising EECK
Condition
Clock 83MHz Clock 83MHz Clock 83MHz
4000
Units
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive Specification
Transmit Receive Timing
TXCLK
TXEN
RXCLK
RXDV
MDIO
(driven AL962)
MDIO
(driven PHY)
Parameter
Description
TXEN/TXD delay from rising TXCLK RXDV/RXD valid before rising RXCLK RXDV/RXD hold from rising RXCLK pulse width MDIO delay from rising MDIO valid before rising MDIO hold after rising
Condition
25MHz
Units
Clock 83MHz
RMII Transmit Receive Timing
REF_CLK TX_EN
TXD(1)
TXD(0)
Preamble
Data
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive Specification
REF_CLK CRS_DV
RXD(1)
RXD(0)
Preamble
Data
Symbol
Thold
Parameter
REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN, RXD[1:0], CRS_DV, Data setup REF_CLK rising edge TXD[1:0]. TX_EN, RXD[1:0], CRS_DV, Data hold from REF_CLK rising edge
Type
Units
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential
Olive Specification
Olive Package
ADMtek Incorporated 99/09/13
Industrial Road, SBIP, HsinChu Version 1.10
(03)578-8879 (03)578-8871 ADMtek Incorporated Confidential

Olive Family LES108 Eight-port 10/100M Ethernet Switch Controller

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