54SX Family FPGAs Lead ance Feat Internal Performance Clock-

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54SX Family FPGAs Lead ance Feat Internal Performance Clock-

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v3.0.1
54SX Family FPGAs
Lead ance Feat
Internal Performance Clock-to-Out (Pin-to-Pin) Input Set-Up 0.25 Clock Skew
peci fica
CPLD FPGA Integration Single Chip Solution 100% Resource Utilization with 100% Locking 3.3V Operation with 5.0V Input Tolerance Very Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic Debug capability with Silicon Explorer Boundary Scan Testing Compliance with IEEE Standard 1149.1 (JTAG) Secure Programming Technology Prevents Reverse Engineering Design Theft
12,000 48,000 System Gates User-Programmable Pins 1080 Flip-Flops 0.35µ CMOS
A54SX08 Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Register Cells (Dedicated Flip-Flops) Maximum User I/Os Clocks JTAG Clock-to-Out Input Set-Up (External) Speed Grades Temperature Grades Packages count) PLCC PQFP VQFP TQFP PBGA FBGA 8,000 12,000 Std, 144, A54SX16 16,000 24,000 1,452 Std, A54SX16P 16,000 24,000 1,452 Std, 144, A54SX32 32,000 48,000 2,880 1800 1,080 Std, 144, 313,
2000 Actel Corporation
Actel's family FPGAs features sea-of-modules architecture that delivers device performance integration levels currently achieved other FPGA architecture. devices greatly simplify design time, enable dramatic reductions design costs power consumption, further decrease time market performance-intensive applications. Actel's architecture features types logic modules, combinatorial cell (C-cell) register cell (R-cell), each optimized fast efficient mapping synthesized logic functions. routing interconnect resources metal layers above logic modules, providing optimal silicon. This enables entire floor device spanned with uninterrupted grid fine-grained, synthesis-friendly logic modules "sea-of-modules"), which reduces distance signals have travel between logic modules. minimize signal propagation delay, devices employ both local general routing resources. high-speed local routing resources (DirectConnect FastConnect) enable very fast local signal propagation that optimal fast counters, state
A54SX16
machines, datapath logic. general system segmented routing tracks allows logic module array connected other logic module. Within this system, propagation delay minimized limiting number antifuse interconnect elements five percent connections typically only three antifuses). unique local general routing structure featured devices gives fast predictable performance, allows percent pin-locking with full logic utilization, enables concurrent development, reduces design time, allows designers achieve performance goals with minimum effort. Further complementing SX's flexible routing structure hard-wired, constantly loaded clock network that been tuned provide fast clock propagation with minimal clock skew. Additionally, high performance internal logic eliminated need embed latches flip-flops cells achieve fast clock-to-out fast input set-up times. devices have easy-to-use cells that require instantiation, facilitating design re-use reducing design verification time.
Application (Temperature Range) Blank Commercial +70°C) Industrial (-40 +85°C) Military (-55 +125°C) Pre-production Package Lead Count Package Type Ball Grid Array Plastic Leaded Chip Carrier Plastic Quad Flat Pack Thin (1.4 Quad Flat Pack Very Thin (1.0 Quad Flat Pack Fine Pitch Ball Grid Array (1.0 Speed Grade Blank Standard Speed Approximately Faster than Standard Approximately Faster than Standard Approximately Faster than Standard Blank Compliant Compliant Part Number A54SX08 A54SX16 A54SX16P A54SX32 12,000 System Gates 24,000 System Gates 24,000 System Gates 48,000 System Gates
Speed Grade* A54SX08 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 144-Pin Thin Quad Flat Pack (TQFP) 144-Pin Fine Pitch Ball Grid Array (FBGA) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) A54SX16 Device 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) A54SX16P Device 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 144-Pin Thin Quad Flat Pack (TQFP) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) A54SX32 Device 144-Pin Thin Quad Flat Pack (TQFP) 176-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 313-Pin Plastic Ball Grid Array (PBGA) 329-Pin Plastic Ball Grid Array (PBGA) Application
Contact your Actel sales representative product availability. Applications: Commercial Availability: Available Industrial Planned Military Planned
*Speed Grade: Approx. faster than Standard Approx. faster than Standard Approx. faster than Standard Only Std, Speed Grade Only Std, Speed Grade
User I/Os (including clock buffers) Device A54SX08 A54SX16 A54SX16P A54SX32 PLCC 84-Pin VQFP 100-Pin PQFP 208-Pin TQFP 144-Pin TQFP 176-Pin PBGA 313-Pin PBGA 329-Pin FBGA 144-Pin
Package Definitions (Consult your local Actel sales representative product availability.) PLCC Plastic Leaded Chip Carrier, PQFP Plastic Quad Flat Pack, TQFP Thin Quad Flat Pack, VQFP Very Thin Quad Flat Pack, PBGA Plastic Ball Grid Array, FBGA Fine Pitch (1.0 Ball Grid Array
family architecture designed satisfy next-generation performance integration requirements production-volume designs broad range applications.
nect
antifuse interconnect elements, which embedded between layers. antifuses normally open circuit and, when programmed, form permanent low-impedance connection. extremely small size these interconnect elements gives family abundant routing resources provides excellent protection against design pirating. Reverse engineering virtually impossible because extremely difficult distinguish between programmed unprogrammed antifuses, there configuration bitstream intercept. Additionally, interconnect (i.e., antifuses metal tracks) have lower capacitance lower resistance than other device similar capacity, leading fastest signal propagation industry.
family provides efficient silicon locating routing interconnect resources between Metal (M2) Metal (M3) layers (Figure This completely eliminates channels routing interconnect resources between logic modules implemented SRAM FPGAs previous generations antifuse FPGAs), enables entire floor device spanned with uninterrupted grid logic modules. Interconnection between these logic modules achieved using Actel's patented metal-to-metal programmable
Routing Tracks
Metal Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Tungsten Plug Metal
Metal Tungsten Plug Contact
Silicon Substrate
Figure Family Interconnect Elements
Logi Modul
family architecture described "sea-of-modules" architecture because entire floor device covered with grid logic modules with virtually chip area lost interconnect elements routing. Actel's family provides types logic modules, register cell (R-cell) combinatorial cell (C-cell).
R-cell contains flip-flop featuring asynchronous clear, asynchronous preset, clock enable (using lines) control signals (Figure page R-cell registers feature programmable clock polarity selectable register-by-register basis. This provides additional flexibility while allowing mapping synthesized functions into FPGA. clock source R-cell chosen from either hard-wired clock routed clock.
C-cell implements range combinatorial functions 5-inputs (Figure Inclusion input associated inverter function dramatically increases number combinatorial functions that implemented single module from options previous architectures more than 4,000 architecture. example improved flexibility
enabled inversion capability ability integrate 3-input exclusive-OR function into single C-cell. This facilitates construction 9-bit parity-tree functions with propagation delays. same time, C-cell structure extremely synthesis friendly, simplifying overall design reducing synthesis time.
Routed Data Input
PSETB Direct Connect Input
HCLK CLKA, CLKB, Internal Logic CLRB
Figure R-Cell
Figure C-Cell
family's chip architecture provides unique approach module organization chip routing that delivers best register/logic wide variety emerging applications.
Modu gani
Actel arranged C-cell R-cell logic modules into horizontal banks called Clusters. There types Clusters: Type contains C-cells R-cell, while Type contains C-cell R-cells.
increase design efficiency device performance, Actel further organized these modules into SuperClusters (Figure page SuperCluster two-wide grouping Type clusters. SuperCluster two-wide group containing Type cluster Type cluster. devices feature more SuperCluster modules than SuperCluster modules because designers typically require significantly more combinatorial logic than flip-flops.
R-Cell
Routed Data Input PSETB Direct Connect Input
C-Cell
HCLK CLKA, CLKB, Internal Logic CLRB
Cluster
Cluster
Cluster
Cluster
Type SuperCluster
Figure Cluster Organization
Type SuperCluster
Clusters SuperClusters connected through innovative local routing resources called FastConnect DirectConnect, which enable extremely fast predictable interconnection modules within Clusters SuperClusters (Figure Figure page This routing architecture also dramatically reduces number antifuses required complete circuit, ensuring highest possible performance. DirectConnect horizontal routing resource that provides connections from C-cell neighboring R-cell given SuperCluster. DirectConnect uses hard-wired signal path requiring programmable interconnection achieve fast signal propagation time less than FastConnect enables horizontal routing between logic modules within given SuperCluster vertical routing with SuperCluster immediately below Only programmable connection used FastConnect path, delivering maximum pin-to-pin propagation addition DirectConnect FastConnect, architecture makes globally oriented routing resources known segmented routing high-drive routing. Actel's segmented routing structure provides variety track lengths extremely fast routing between SuperClusters. exact combination track lengths antifuses within each path chosen percent
automatic place route software minimize signal propagation delays. Actel's high-drive routing structure provides three clock networks. first clock, called HCLK, hard wired from HCLK buffer clock select each R-cell. This provides fast propagation path clock signal, enabling clock-to-out (pin-to-pin) performance devices. hard-wired clock tuned provide clock skew 0.25 remaining clocks (CLKA, CLKB) global clocks that sourced from external pins from internal logic signals within device.
echno
Actel's family implemented high-voltage twin-well CMOS process using 0.35µ design rules. metal-to-metal antifuse made combination amorphous silicon
dielectric material with barrier metals programmed ("on" state) resistance with capacitance signal impedance.
Direct Connect antifuses routing delay
Fast Connect antifuse routing delay
Routing Segments Typically antifuses Max. antifuses
Type SuperClusters
Figure DirectConnect FastConnect Type SuperClusters
Direct Connect antifuses routing delay
Fast Connect antifuse routing delay
Routing Segments Typically antifuses Max. antifuses
Type SuperClusters
Figure DirectConnect FastConnect Type SuperClusters
ounda
combination architectural features described above enables devices operate with internal clock frequencies exceeding MHz, enabling very fast execution even complex logic functions. Thus, family optimal platform upon which integrate functionality previously contained multiple CPLDs. addition, designs that previously would have required gate array meet performance goals integrated into device with dramatic improvements cost time market. Using timing-driven place route tools, designers achieve highly deterministic device performance. With devices, designers need complicated performance-enhancing design techniques such redundant logic reduce fanout critical nets instantiation macros code achieve high performance.
Modules
devices IEEE 1149.1 compliant. devices offer superior diagnostic testing capabilities providing Boundary Scan Testing (BST) probing capabilities. These functions controlled through special test pins conjunction with program fuse. functionality each described Table 2.In dedicated test mode, TCK, dedicated pins cannot used regular I/Os. flexible mode, should HIGH through pull-up resistor 10k. pulled initiate test sequence. program fuse determines whether device dedicated flexible mode. default (fuse blown) flexible mode. Table Boundary Scan Functionality
Program Fuse Blown (Dedicated Test Mode) TCK, TDI, dedicated pins need pull-up resistor Program Fuse Blown (Flexible Mode) TCK, TDI, flexible used I/Os pull-up resistor
Each device configured input, output, tristate output, bidirectional pin. Even without inclusion dedicated registers, these I/Os, combination with array registers, achieve clock-to-out (pad-to-pad) timing fast cells that have embedded latches flip-flops require instantiation code; this design complication encountered FPGAs. Fast pin-to-pin timing ensures that device will have little trouble interfacing with other device system, which turn enables parallel design system components reduces overall design time.
ower
lopm
family supports 3.3V operation designed tolerate 5.0V inputs. (Table Power consumption extremely very short distances signals required travel complete circuit. Power requirements further reduced because small number low-resistance antifuses path. antifuse architecture does require active circuitry hold charge SRAM EPROM), making lowest-power architecture market. Table Supply Voltages
VCCA A54SX08 A54SX16 A54SX32 3.3V 3.3V 3.3V A54SX16P 3.3V 3.3V VCCI 3.3V 3.3V 3.3V 3.3V 5.0V Input Output VCCR Tolerance Drive 5.0V 5.0V 3.3V 5.0V 5.0V 3.3V 5.0V 3.3V 5.0V 5.0V 3.3V 3.3V 3.3V 3.3V 5.0V
devices fully supported Actel's line FPGA development tools, including Actel DeskTOP series Designer Advantage tools. Actel DeskTOP series integrated design environment that includes design entry, simulation, synthesis, place route tools. Designer Advantage, Actel's suite FPGA development point tools Workstations, includes ACTgen Macro Builder, Designer with DirectTime timing driven place route analysis tools, device programming software. addition, devices contain ActionProbe circuitry that provides built-in access every node design, enabling 100-percent real-time observation analysis device's internal logic nodes without design iteration. probe circuitry accessed Silicon Explorer easy-to-use integrated verification logic analysis tool that sample data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard port, turning into fully functional 18-channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle only seconds.
Silicon Explorer tool uses boundary scan ports (TDI, TCK, TDO) select desired nets verification. selected internal nets assigned PRA/PRB pins observation. Figure illustrates
interconnection between Silicon Explorer FPGA perform in-circuit verification. TRST equipped with pull-up resistor. remove boundary scan state machine from reset state during probing, recommended that TRST left floating.
TDI, TCK, TDO, PRA, pins should used input bidirectional ports. Because these pins active during probing, critical signals input through these pins available while probing. addition, Security Fuse should programmed because doing disables Probe Circuitry.
Channels
FPGA Serial Connection Silicon Explorer
Figure Probe Setup
Symbol VCCR2 VCCA VCCI
Units Parameter Temperature Range1 3.3V Power Supply Tolerance 5.0V Power Supply Tolerance Commercial Industrial to+70 Military +125 Units
Parameter Supply Voltage3 Supply Voltage Supply Voltage (A54SX08, A54SX16, A54SX32) Supply Voltage (A54SX16P) Input Voltage Output Voltage Source Sink Current3 Storage Temperature
Limits -0.3 +6.0 -0.3 +4.0 -0.3 +4.0
%VCC
VCCI2 TSTG
-0.3 +6.0 -0.5 +5.5 -0.5 +3.6 +5.0 +125
%VCC
Note: Ambient temperature (TA) used commercial industrial; case temperature (TC) used military.
Notes: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operating Conditions. VCCR A54SX16P must greater than equal VCCI during power-up power-down sequences during normal operation. Device inputs normally high impedance draw extremely current. However, when input voltage greater than 0.5V less than 0.5V, internal protection diodes will forward-bias draw excessive current.
Commercial Symbol Parameter (IOH -20uA) (CMOS) (IOH -8mA) (TTL) (IOH -6mA) (TTL) (IOL= 20uA) (CMOS) ICC(D) Input Transition Time Capacitance Standby Current, ICC(D) IDynamic Supply Current (IOL 12mA) (TTL) (IOL 8mA) (TTL) 0.10 0.50 0.50 Min. (VCCI 0.1) Max. VCCI VCCI VCCI Industrial Min. (VCCI 0.1) Max. VCCI Units
"Evaluating Power 54SX Devices" page
54SX family supports 3.3V compliant with Local Specification Rev. 2.1.
A54SX16P Specifications (5.0V Operation)
Symbol VCCA VCCR VCCI CCLK CIDSEL
Parameter Supply Voltage Array Supply Voltage required Internal Biasing Supply Voltage Input High Voltage Input Voltage
Condition
Min. 4.75 4.75 -0.5
Max. 5.25 5.25
Units
Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage
IOUT IOUT
0.55
Input Capacitance Capacitance
IDSEL Capacitance
Notes: Input leakage currents include hi-Z output leakage bi-directional buffers with tri-state outputs. Signals without pull-up resistors must have output current. Signals requiring pull must have latter include, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, ACK64#. Absolute maximum capacitance input (except CLK). Lower capacitance this input-only allows non-resistive coupling AD[xx].
A54SX16P Specifications (PCI Operation)
Symbol
Parameter
Condition VOUT 1.41
Min.
Max.
Units
IOH(AC)
Switching Current High
VOUT VOUT VOUT
(VOUT 1.4)/0.024 Equation page -142
VOUT (Test Point)
IOL(AC)
Switching Current High
VOUT 0.55 0.71 VOUT VOUT 0.71
VOUT/0.023 Equation page (VIN 1)/0.015 V/ns V/ns
(Test Point) slewR slewF Clamp Current Output Rise Slew Rate Output Fall Slew Rate
0.4V 2.4V load 2.4V 0.4V load
Notes: Refer curves Figure Switching current characteristics REQ# GNT# permitted half that specified here; i.e., half size output drivers used these signals. This specification does apply RST# which system outputs. "Switching Current High" specification relevant SERR#, INTA#, INTB#, INTC#, INTD# which open drain outputs. Note that this segment minimum current curve drawn from drive point directly drive point rather than toward voltage rail done pull-down curve). This difference intended allow optional N-channel pull-up. Maximum current requirements must drivers pull beyond last step voltage. Equations defining these maximums provided with respective diagrams Figure equation defined maxima should design. order facilitate component testing, maximum current test point defined each side output driver. This parameter interpreted cumulative edge rate across specified range, rather than instantaneous rate point within transition range. specified load (diagram below) optional; i.e., designer elect meet this parameter with unloaded output revision Local Specification. However, adherence both maximum minimum parameters required (the maximum longer simply guideline). Since adherence maximum slew rate required prior revision specification, there components market some time that have faster edge rates; therefore, motherboard designers must bear mind that rise fall times faster than this specification could occur, should ensure that signal integrity modeling accounts this. Rise slew rate does apply open drain outputs. output buffer max.
Figure shows 5.0V curve minimum maximum drive characteristics A54SX16P family.
0.50 0.45 0.40 0.35 0.30 Current 0.25 0.20 0.15 0.10 0.05 -0.05 -0.10 -0.15 -0.20 Voltage Minimum Maximum Minimum Maximum
Figure 5.0V Curve A54SX16P Family Equation 11.9 (VOUT 5.25) (VOUT 2.45) VOUT 3.1V Equation 78.5 VOUT (4.4 VOUT) VOUT 0.71V
peci ions 3.3V
Symbol VCCA VCCR VCCI IIPU CCLK CIDSEL
Parameter Supply Voltage Array Supply Voltage required Internal Biasing Supply Voltage Input High Voltage Input Voltage Input Pull-up Voltage
Condition
Min. 0.5VCC -0.5 0.7VCC
Max. 0.3VCC
Units
Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance
IOUT -500 IOUT 1500 0.9VCC
0.1VCC
IDSEL Capacitance
Notes: This specification should guaranteed design. minimum voltage which pull-up resistors calculated pull floated network. Applications sensitive static power utilization should assure that input buffer conducting minimum current this input voltage. Input leakage currents include hi-Z output leakage bi-directional buffers with tri-state outputs. Absolute maximum capacitance input 10pF (except CLK). Lower capacitance this input-only allows non-resistive coupling AD[xx].
54SX16P Specifications (3.3V Operation)
Symbol
Parameter
Condition VOUT 0.3VCC1
Min.
Max.
Units
Switching Current High IOH(AC) (Test Point)
0.3VCC VOUT 0.9VCC 0.7VCC VOUT VOUT 0.7VCC
-12VCC -17.1 (VCC VOUT) Equation page -32VCC
VOUT 0.6VCC Switching Current High IOL(AC) (Test Point) slewR slewF Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate
0.6VCC VOUT 0.1VCC 0.18VCC VOUT VOUT 0.18VCC 0.2VCC 0.6VCC load 0.6VCC 0.2VCC load
16VCC 26.7VOUT (VIN 1)/0.015 (VIN VOUT 1)/0.015 page 38VCC
V/ns V/ns
Notes: Refer curves Figure Switching current characteristics REQ# GNT# permitted half that specified here; i.e., half size output drivers used these signals. This specification does apply RST# which system outputs. "Switching Current High" specification relevant SERR#, INTA#, INTB#, INTC#, INTD# which open drain outputs. Maximum current requirements must drivers pull beyond last step voltage. Equations defining these maximums provided with respective diagrams Figure equation defined maxima should design. order facilitate component testing, maximum current test point defined each side output driver. This parameter interpreted cumulative edge rate across specified range, rather than instantaneous rate point within transition range. specified load (diagram below) optional; i.e., designer elect meet this parameter with unloaded output latest revision Local Specification. However, adherence both maximum minimum parameters required (the maximum longer simply guideline). Rise slew rate does apply open drain outputs. output buffer max.
Figure shows 3.3V curve minimum maximum drive characteristics A54SX16P family.
0.50 0.45 0.40 0.35 0.30
Current Maximum
0.25 0.20
0.15 0.10 0.05 -0.05 -0.10 -0.15 -0.20
Voltage Minimum Maximum Minimum
Figure 3.3V Curve A54SX16P Family Equation (98.0/VCC) (VOUT VCC) (VOUT 0.4VCC) VOUT Equation (256/VCC) VOUT (VCC VOUT) VOUT 0.18
VCCA VCCR VCCI Power-Up Sequence Comments
A54SX08, A54SX16, A54SX32 5.0V First 3.3V Second 3.3V First 5.0V Second A54SX16P 3.3V 3.3V 3.3V 3.3V Only 5.0V First 3.3V Second 3.3V First 5.0V Second 5.0V First 3.3V Second 3.3V First 5.0V Second possible damage device. possible damage device. Possible damage device. possible damage device. possible damage device. possible damage device. Possible damage device.
3.3V
5.0V
3.3V
3.3V
5.0V
3.3V
3.3V
5.0V
5.0V
VCCA VCCR VCCI Power-Down Sequence Comments
A54SX08, A54SX16, A54SX32 5.0V First 3.3V Second 3.3V First 5.0V Second A54SX16P 3.3V 3.3V 3.3V 3.3V Only 5.0V First 3.3V Second 3.3V First 5.0V Second 5.0V First 3.3V Second 3.3V First 5.0V Second possible damage device. Possible damage device. possible damage device. possible damage device. possible damage device. Possible damage device. possible damage device.
3.3V
5.0V
3.3V
3.3V
5.0V
3.3V
3.3V
5.0V
5.0V
critical element system reliability ability electronic devices safely dissipate heat generated during operation. thermal characteristics circuit depend device package used, operating temperature, operating current, system's ability dissipate heat. should complete power evaluation early design process help identify potential heat-related problems system prevent system from exceeding device's maximum allowed junction temperature. actual power dissipated most applications significantly lower than power package dissipate. However, thermal analysis should performed projects. perform power evaluation, follow these steps: Estimate power consumption application. Calculate maximum power allowed device package. Compare estimated power maximum power values.
(0.5 CEQCR fq1) fq1))RCLKA (0.5 CEQCR fq2)+ fq2))RCLKB (0.5 CEQHV fs1) (CEQHF fs1))HCLK]
efin
CEQM CEQI CEQO CEQCR CEQHV CEQHF
total power dissipation 54SX family power dissipation power dissipation. Equation calculate estimated power consumption your application. PTotal
power standby current typically small component overall power. Standby power shown below commercial, worst case conditions (70°C). Table
3.6V Power 14.4mW
Number logic modules switching Number input buffers switching Number output buffers switching Number clock loads first routed array clock Number clock loads second routed array clock Number I/Os logic Number I/Os logic high Fixed capacitance first routed array clock Fixed capacitance second routed array clock Number clock loads dedicated array clock Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers Equivalent capacitance routed array clock Variable capacitance dedicated array clock Fixed capacitance dedicated array clock Output lead capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate Average dedicated array clock rate A54SX16 0.615 A54SX16P 0.615 A54SX32 0.615
power dissipation defined Equation follows: (Istandby)*VCCA (Istandby)*VCCR (Istandby)*VCCI x*VOL*IOL y*(VCCI VOH)*VOH
power dissipation 54SX Family usually dominated dynamic power dissipation. Dynamic power dissipation function frequency, equivalent capacitance power supply voltage. power dissipation defined follows: PModule PRCLKA PRCLKB PHCLK POutput Buffer PInput Buffer VCCA CEQM fm)Module CEQI fn)Input Buffer+ (CEQO fp)Output Buffer+
A54SX08 CEQM (pF) CEQI (pF) CEQO (pF) CEQCR (pF) CEQHV 0.615 CEQHF (pF) (pF)
Guid ower
following guidelines meant represent worst-case scenarios that they generally used predict upper limits power dissipation. These guidelines follow: modules inputs/4 output/4 register cells Second Routed Array Clock Loads (q2) register cells Load Capacitance (CL) Average Logic Module Switching Rate f/10 (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp) f/10 Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) Average Dedicated Array Clock Rate (fs1) Dedicated Clock Array clock loads (s1) regular modules
Buffer+ (0.5 CEQCR fq1) fq1))RCLKA (0.5 CEQCR fq2)+ fq2))RCLKB (0.5 CEQHV fs1) (CEQHF fs1))HCLK]
Step Define Terms Used Formula
Logic Modules Inputs Switching Outputs Switching First Routed Array Clock Loads (q1)
designs used characterize A54SX family serial serial shift register. design utilized 100% dedicated flip-flops A54SX16P device. pattern 0101. clocked into device frequencies ranging from MHz. Shifting series 0101. caused flip-flops toggle from high every clock cycle. Follow steps below estimate power consumption. values provided sample calculation below shift register design above. This method estimating power consumption conservative actual power consumption your design less than estimated power consumption. total power dissipation 54SX family power dissipation power dissipation. PTotal (dynamic power) (static power)
VCCA Module Number logic modules switching (Used 50%) Average logic modules switching rate (MHz) (Guidelines: f/10) Module capacitance CEQM (pF) Input Buffer Number input buffers switching Average input switching rate (MHz) (Guidelines: f/5) Input buffer capacitance CEQI (pF) Output Buffer Number output buffers switching Average output buffers switching rate fp(MHz) (Guidelines: f/10) Output buffers buffer Capacitance CEQO (pF) Output Load capacitance (pF) RCLKA Number Clock loads Capacitance routed array clock (pF) Average clock rate (MHz) Fixed capacitance (pF) RCLKB Number Clock loads Capacitance routed array clock (pF) Average clock rate (MHz) Fixed capacitance (pF) HCLK Number Clock loads Variable capacitance dedicated array clock (pF) Fixed capacitance dedicated array clock (pF) Average clock rate (MHz)
CEQM CEQI
CEQO CEQCR CEQCR
CEQHV 0.615 CEQHF
PModule PRCLKA PRCLKB PHCLK POutput Buffer PInput Buffer VCCA CEQM fm)Module CEQI fn)Input Buffer+ (CEQO fp)Output
Step Calculate Dynamic Power Consumption
(Istandby)*VCCA 10.89 0.02112 0.000136 0.000794 0.11208 .55mA*3.3V 0.001815W
Step Calculate Total Power Consumption
VCCA*VCCA m*fm*CEQM n*fn*CEQI p*fp*(CEQO+CL) 0.5*(q1*CEQCR*fq1)+(r1*fq1) 0.5*(q2*CEQCR*fq2)+(r2*fq2) *(s1 CEQHV fs1)+(CEQHF*fs1) 1.461W
Step Calculate Power Dissipation
PTotal PTotal 1.461 0.001815 PTotal 1.4628W
Step Compare Estimated Power Consumption against Characterized Power Consumption
Power Dissipation (Istandby)*VCCA (Istandby)*VCCR (Istandby)*VCCI X*VOL*IOL Y*(VCCI VOH)*VOH rough estimate Power Dissipation, only (Istandby)*VCCA. rest formula provides very small number that considered negligible.
1200
estimated total power consumption this design 1.46W. characterized power consumption this design 1.0164W. Figure shows characterized power dissipation numbers shift register design using frequencies ranging from MHz.
1000 Power Dissipation
Frequency
Figure Power Dissipation
temperature that select Designer Series software junction temperature, ambient temperature. This important distinction because heat generated from dynamic power consumption usually hotter than ambient temperature. equation below calculate junction temperature. Junction Temperature Where: Ambient Temperature
Power calculated from Estimating Power Consumption section
Junction ambient package. numbers located Package Thermal Characteristics section.
device junction case thermal characteristic junction ambient characteristic thermal characteristics shown with different flow rates. maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed TQFP 176-pin package commercial temperature still follows:
Temperature gradient between junction (silicon) ambient
150°C 70°C -Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C) 2.86W 28°C/W (°C/W) Still 38.8 ft/min 14.5 13.5 26.7
Package Type Plastic Leaded Chip Carrier (PLCC) Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Very Thin Quad Flatpack (VQFP) Plastic Quad Flat Pack (PQFP) without Heat Spreader Plastic Quad Flat Pack (PQFP) with Heat Spreader Plastic Ball Grid Array (PBGA) Plastic Ball Grid Array (PBGA) Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Note: SX08 does have heat spreader.
Count
Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Input Delays Module tINY
Internal Delays Combinatorial Cell tIRD2
Predicted Routing Delays
Output Delays Module
tDHL =0.6 tRD1 tRD4 tRD8
Module tDHL
Register Cell
Register Cell
tRD1
tRD1 tENZH
tSUD Routed Clock tRCO tRCKH (100% Load) FMAX Hard-Wired Clock tRCO
tHCKH
FHMAX *Values shown A54SX08-3, worst-case commercial conditions.
External Set-Up
tINY tIRD1 tSUD tHCKH
External Set-Up tINY tIRD1 tSUD tRCKH Clock-to-Out (Pin-to-Pin) tRCKH tRCO tRD1 tDHL 1.52+
Clock-to-Out (Pin-to-Pin) tHCKH tRCO tRD1 tDHL
TRIBUFF test loads (shown below)
tDLH 1.5V tDHL 1.5V
1.5V tENZL tENLZ
1.5V tENZH tENHZ
Load (Used measure propagation delay) output under test output under test Load (Used measure enable delays) Load (Used measure disable delays)
tPZL tPZH
output under test
tPLZ tPHZ
INBUF
tINY 1.5V 1.5V tINY
Flop
PRESET
ositive edge triggered) tSUD tHPWH, tRPWH tHPWL, tRPWL
tRCO
tCLR ASYN PRESET
tPRESET
Timing characteristics 54SX devices fall into three categories: family-dependent, device-dependent, design-dependent. input output buffer characteristics common 54SX family members. Internal routing delays device dependent. Design dependency means actual delays determined until after placement routing user's design complete. Delay values then determined using DirectTime Analyzer utility performing simulation with post-layout delays.
Some nets design long tracks. Long tracks special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes five antifuse connections. This increases capacitance resistance, resulting longer delays macros connected long tracks. Typically nets fully utilized device require long tracks. Long tracks contribute approximately delay. This additional delay represented statistically higher fanout (FO=24) routing delays data sheet specifications section.
Propagation delays expressed only typical nets, which used initial design performance evaluation. Critical delays then applied most time-critical paths. Critical nets determined property assignment prior placement routing. nets design designated critical, while nets design typical.
54SX devices manufactured CMOS process. Therefore, device performance varies according temperature, voltage, process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, worst-case processing.
(Normalized Worst-Case Commercial, 3.0V)
Junction Temperature (TJ) VCCA 0.75 0.70 0.66 0.78 0.73 0.69 0.87 0.82 0.77 0.89 0.83 0.78 1.00 0.93 0.87 1.04 0.97 0.92 1.16 1.08 1.02
(Worst-Case Commercial Conditions, 4.75V, 3.0V,
`-3' Speed Parameter Description
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Min.
Max.
C-Cell Propagation Delays
Internal Array Module
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
R-Cell Timing tRCO tCLR tPRESET tSUD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Commercial Conditions)
`-3' Speed Parameter Description Min. Max.
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ
Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad,
Note: Delays based loading, except tENZL tENZH tENZL tENZH loading
(Worst-Case Commercial Conditions, 4.75V, 3.0V,
`-3' Speed Parameter Description
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Min.
Max.
C-Cell Propagation Delays
Internal Array Module
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
R-Cell Timing tRCO tCLR tPRESET tSUD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Predicted Input Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Commercial Conditions)
`-3' Speed Parameter Description Min. Max.
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Output ModuleTiming tDLH tDHL tENZL tENZH tENLZ tENHZ
Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad,
Note: Delays based loading, except tENZL tENZH tENZL tENZH loading
(Worst-Case Commercial Conditions, 4.75V, 3.0V,
`-3' Speed Parameter Description
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Min.
Max.
C-Cell Propagation Delays
Internal Array Module
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
R-Cell Timing tRCO tCLR tPRESET tSUD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Predicted Input Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 3.0V,
`-3' Speed Parameter Description Min. Max.
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tDLH tDHL tENZL tENZH tENLZ tENHZ tDLH tDHL tENZL tENZH tENLZ tENHZ Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Output Module Timing Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad,
TTL/PCI Output Module Timing Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad,
(continued)
(Worst-Case Commercial Conditions 3.0V, 3.0V, 70°C)
`-3' Speed Parameter Description
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Min.
Max.
Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ
Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad,
Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad,
Note: Delays based loading.
(Worst-Case Commercial Conditions, 4.75V, 3.0V,
`-3' Speed Parameter Description
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Min.
Max.
C-Cell Propagation Delays
Internal Array Module
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
R-Cell Timing tRCO tCLR tPRESET tSUD tWASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Predicted Input Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Commercial Conditions)
`-3' Speed Parameter Description Min. Max.
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
0.85 1.23 1.30
0.98
Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ
Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad,
Note: Delays based 35pF loading, except tENZL tENZH tENZL tENZH loading 5pF.
CLKA/B Clock Test Data Input
These pins 3.3V/5.0V PCI/TTL clock inputs clock distribution networks. clock input buffered prior clocking R-cells. used, this must HIGH board. must left floating. (For A54SX72A, these clocks configured bidirectional.)
Ground
Serial input boundary scan testing diagnostic probe. flexible mode, active when (refer Table page This functions when boundary scan state machine reaches "logic reset" state.
Test Data Output
supply voltage.
HCLK Dedicated (Hard-wired) Array Clock
This 3.3V/5.0V PCI/TTL clock input sequential modules. This input directly wired each R-cell offers clock speeds independent number R-cells being driven. used, this must HIGH board. must left floating.
Input/Output
Serial output boundary scan testing. flexible mode, active when (refer Table page This functions when boundary scan state machine reaches "logic reset" state.
Test Mode Select
functions input, output, tristate, bidirectional buffer. Based certain configurations, input output levels compatible with standard TTL, LVTTL, 3.3V 5.0V specifications. Unused pins automatically tristated Designer Series software.
Connection
controls IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). flexible mode when LOW, TCK, TDI, pins boundary scan pins (refer Table page Once boundary scan pins test mode, they will remain that mode until internal boundary scan state machine reaches "logic reset" state. this point, boundary scan pins will released will function regular pins. "logic reset" state reached cycles after HIGH. dedicated test mode, functions specified IEEE 1149.1 specifications.
Supply Voltage
This connected circuitry within device.
PRA, Probe
Supply voltage I/Os. Table page
Supply Voltage
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality.
PRB, Probe
Supply voltage Array. Table page
Supply Voltage
Supply voltage input tolerance (required internal biasing) Table page
Probe used output data from node within device. This diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality.
Test Clock
Test clock input diagnostic probe device programming. flexible mode, becomes active when (refer Table page This functions when boundary scan state machine reaches "logic reset" state.
84-Pin PLCC
acka
Number
A54SX08 Function VCCR VCCA PRA, VCCI TCK, TDI, VCCI PRB, VCCA
Number
A54SX08 Function VCCR HCLK TDO, VCCA VCCI VCCA CLKA CLKB
54SX Family FPGAs
(continued)
208-
208-Pin PQFP
208-
Number
A54SX08 Function
TDI, VCCI VCCR VCCA VCCI VCCA
A54SX16, A54SX16P Function
TDI, VCCI VCCR VCCA VCCI VCCA
A54SX32 Function
TDI, VCCI VCCR VCCA VCCI VCCA
Number
A54SX08 Function
VCCI PRB, VCCA VCCR HCLK VCCI TDO,
A54SX16, A54SX16P Function
VCCI PRB, VCCA VCCR HCLK VCCI TDO,
A54SX32 Function
VCCI PRB, VCCA VCCR HCLK VCCI TDO,
Please note that A54SX32-PQ208 connect (NC).
54SX Family FPGAs
208-
Number
A54SX08 Function
A54SX16, A54SX16P Function
A54SX32 Function
Number
A54SX08 Function
VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
A54SX16, A54SX16P Function
VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
A54SX32 Function
VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
VCCA VCCA VCCA VCCI VCCI VCCI VCCA VCCA VCCA VCCR VCCR VCCR VCCA VCCA VCCA VCCI VCCI VCCI Please note that A54SX32-PQ208 connect (NC).
(continued)
144-
144-Pin TQFP
54SX Family FPGAs
144-Pin TQFP
Number
A54SX08 Function TDI, VCCI VCCR VCCA VCCI VCCA
A54SX16P Function TDI, VCCI VCCR VCCA VCCI VCCA
A54SX32 Function TDI, VCCI VCCR VCCA VCCI VCCA
Number
A54SX08 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO, VCCA VCCI
A54SX16P Function VCCI PRB, VCCA VCCR HCLK VCCI TDO, VCCA VCCI
A54SX32 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO, VCCA VCCI
144-Pin TQFP (Continued)
Number
A54SX08 Function VCCA VCCR VCCA VCCI
A54SX16P Function VCCA VCCR VCCA VCCI
A54SX32 Function VCCA VCCR VCCA VCCI
Number
A54SX08 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
A54SX16P Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
A54SX32 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
54SX Family FPGAs
(continued)
176-
176-Pin TQFP
176-
Number
A54SX08 Function TDI, VCCI VCCA VCCI VCCA
A54SX16, A54SX16P Function TDI, VCCI VCCA VCCI VCCA
A54SX32 Function TDI, VCCI VCCA VCCI VCCA
Number
A54SX08 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO,
A54SX16, A54SX16P Function VCCI PRB, VCCA VCCR HCLK VCCI TDO,
A54SX32 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO,
54SX Family FPGAs
176-
Number
A54SX08 Function VCCA VCCI VCCA VCCA VCCI
A54SX16, A54SX16P Function VCCA VCCI VCCA VCCA VCCI
A54SX32 Function VCCA VCCI VCCA VCCA VCCI
Number
A54SX08 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
A54SX16, A54SX16P Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
A54SX32 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
(continued)
100-
100-Pin VQFP
54SX Family FPGAs
100-
Number
A54SX08 Function TDI, VCCI VCCI PRB, VCCA VCCR HCLK VCCI TDO,
A54SX16, A54SX16P Function TDI, VCCI VCCI PRB, VCCA VCCR HCLK VCCI TDO,
Number
A54SX08 Function VCCA VCCI VCCA VCCI CLKA CLKB VCCR VCCA PRA, TCK,
A54SX16 A54SX16P Function VCCA VCCI VCCA VCCI CLKA CLKB VCCR VCCA PRA, TCK,
(continued)
313-Pin PBGA (Top View)
54SX Family FPGAs
Number AA11 AA13 AA15 AA17 AA19 AA21 AA23 AA25 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC11 AC13
A54SX32 Function VCCR VCCI VCCR
Number AC15 AC17 AC19 AC21 AC23 AC25 AD10 AD12 AD14 AD16 AD18 AD20 AD22 AD24 AE11 AE13 AE15 AE17 AE19 AE21 AE23 AE25
A54SX32 Function VCCI PRB, VCCA TDO, TCK, TDI,
Number
A54SX32 Function VCCI VCCI VCCA
Number
A54SX32 Function VCCI CLKB PRA, VCCI CLKA VCCI
313-
Number
A54SX32 Function VCCA VCCI
Number
A54SX32 Function VCCA VCCR VCCI VCCR VCCA
Number
A54SX32 Function HCLK VCCI VCCA
Number
A54SX32 Function VCCA VCCI VCCI
54SX Family FPGAs
(continued)
329-Pin PBGA (Top View)
Number AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22
A54SX32 Function VCCI VCCI CLKB VCCI VCCI TDO, VCCI
Number AA23 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21
A54SX32 Function VCCI PRB, HCLK VCCI VCCI
Number AC22 AC23
A54SX32 Function VCCI VCCI PRA, CLKA VCCI TDI,
Number
A54SX32 Function VCCI TCK, VCCA VCCR VCCI
54SX Family FPGAs
Number
A54SX32 Function VCCA VCCR VCCR
Number
A54SX32 Function VCCA VCCA VCCI
Number
A54SX32 Function VCCA VCCA VCCI
Number
A54SX32 Function VCCA VCCR
(Continued)
144-Pin FBGA (Top View)
144-
Number
A54SX08 Function VCCA CLKA CLKB TCK, PRA, VCCI TDI,
Number
A54SX08 Function VCCI VCCI VCCI VCCA VCCR VCCI VCCI VCCA VCCA VCCI VCCI VCCA VCCR
Number
A54SX08 Function PRB, VCCA HCLK VCCA TDO,
Leade
.048 (1.219) .042 (1.067)
.049 (1.244)
D2/E2
0.006
.075 (1.905)
.032 (0.812) .005 (0.127) After Lead Finish Base Line .035 (0.889)
.020 (0.508)
.044 (1.117)
54SX Family FPGAs
Leade acka
JEDEC Equiv Dimension D1/E1 D2/E2 D3/E3
PLCC MS007 Min. 3.94 2.29 0.33 0.66 0.13 29.72 28.96 27.69 4.45 3.30 0.69 0.81 0.28 30.73 29.46 28.70
25.4 nominal 1.27
Notes: dimensions millimeters. BSC-Basic Spacing between Centers.
(continued)
Quad
Detail Detail
0.20
Theta
0.20
54SX Family FPGAs
(continued)
Quad ngul acka
Detail Detail
0.20
Theta
0.20
Quad acks
JEDEC Equiv Dimension D1/E1 Theta Diameter 19.82 0.50 0.25 3.20 0.17 0.09 30.25 27.90 Min.
PQFP MO-143 3.70 0.38 3.40 3.60 0.27 0.20 30.60 28.00 0.50 0.60 0.75 0.10 20.32 20.82 30.85 28.10 4.10
Quad
JEDEC Equiv Dimension D1/E1 Theta 0.45 0.05 1.35 0.17 0.09 21.75 19.90 Min.
TQFP MO-136 1.60 0.10 1.40 0.15 1.45 0.27 0.20 22.00 20.00 0.50 0.60 0.75 0.10 0.45 22.25 20.10 0.05 1.35 0.17 0.09 25.75 23.90
TQFP MO-136 1.60 0.10 1.40 0.15 1.45 0.27 0.20 26.00 24.00 0.50 0.60 0.75 0.10 26.25 24.10
Notes: dimensions millimeters. BSC-Basic Spacing between Centers.
54SX Family FPGAs
Quad (VQFP
JEDEC Equiv Dimension D1/E1 Theta 0.45 0.05 0.95 0.17 0.09 15.75 13.90
VQFP MO-136 1.20 0.10 1.00 0.15 1.05 0.27 0.20 16.00 14.00 0.50 0.60 0.75 0.10 16.25 14.10
Notes: dimensions millimeters. BSC-Basic Spacing between Centers.
(continued)
144-
View
D/D2
Bottom View
Corner
E/E2
Side View
Detail
D1/E1
Detail
54SX Family FPGAs
FBGA Dimension 12.80 12.80 12.80 12.80 13.00 11.00 13.00 13.00 11.00 13.00 1.00 13.20 1.10 13.20 13.20 0.35 0.25 13.20 0.45 0.50 Min. 1.35 0.35 0.65 Nom. 1.45 0.40 0.70 Max. 1.55 0.45 0.75 0.15 0.55 0.20
Notes: dimensions millimeters. BSC-Basic Spacing between Centers.
(continued)
View Corner
Bottom View Corner 1615 (dia.)
Side View Detail
D1/E1
Detail R0.025 Typ.
(continued)
View Corner
Bottom View Corner
Side View Detail
D1/E1
Detail R0.025 Typ.
JEDEC Equivalent Dimension 29.50 0.60 0.53 29.50 34.80 Min. 2.12 0.50 1.12 34.80
PBGA313 Nom. 2.33 0.60 1.17 35.00 30.48 30.00 35.00 30.48 30.00 0.76 0.56 30.70 0.90 0.61 0.15 0.35 1.27 typ. 27.90 0.60 0.53 30.70 35.20 27.90 30.80 Max. 2.52 0.70 1.22 35.20 Min. 2.17 0.50 1.10 30.80
PBGA329 Nom. 2.33 0.60 1.20 31.00 27.94 28.00 31.00 27.94 28.00 0.76 0.60 28.10 0.90 0.70 0.20 0.20 0.25 1.27 typ. 28.10 31.20 Max. 2.70 0.70 1.30 31.20
Notes: dimensions millimeters. BSC-Basic Spacing between Centers.
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54SX Family FPGAs Lead ance Feat Internal Performance Clock-

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