User I/Os 1,080 Dedicated Flip-Flops Tested Total Ionizing Dose (

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54SX Family FPGAs RadTolerant HiRel
User I/Os 1,080 Dedicated Flip-Flops
Tested Total Ionizing Dose (TID) Survivability Level Radiation Performance 100Krads (Si) (ICC Standby Parametric) Devices Available from Tested Pedigreed Lots On-Chip Performance Offered Class E-Flow (Actel Space Level Flow) Certified Devices
Non-Volatile, User Programmable Highly Predictable Performance with 100% Automatic Place Route 100% Resource Utilization with 100% Locking Mixed Voltage Support-3.3V Operation with 5.0V Input Tolerance Power Operation JTAG Boundary Scan Testing Compliance with IEEE Standard 1149.1 Secure Programming Technology Prevents Reverse Engineering Design Theft Permanently Programmed Operation Power-Up Unique In-System Diagnostic Debug Facility with Silicon Explorer Supported Actel's Designer Series DeskTOP Series Development Systems with Automatic Timing Driven Place Route Predictable, Reliable, Permanent Antifuse Technology Performance
Fastest HiRel FPGA Family Available On-Chip Performance Cost Prototyping Vehicle RadTolerant Devices Offered Commercial Military Temperature Tested Class Cost Effective MIL-Temp Plastic Packaging Options Standard Hermetic Packaging Offerings Certified Devices
High
16,000 32,000 Available Logic Gates
Device Capacity System Gates Logic Gates Logic Modules Register Cells Combinatorial Cells User I/Os (Maximum) JTAG Packages count) CQFP 208, RT54SX16
A54SX16
RT54SX32
A54SX32
24,000 16,000 1,452
24,000 16,000 1,452
48,000 32,000 2,880 1,080 1,800
48,000 32,000 2,880 1,080 1,800
208,
208,
208,
2000 Actel Corporation
Actel's family FPGAs features revolutionary sea-of-modules architecture that delivers next-generation device performance integration levels currently achieved other FPGA architecture. devices greatly simplify design time, enable dramatic reductions design costs power consumption, speed time-to-market performance-intensive applications. Actel's RadTolerant (RT) HiRel versions Family FPGAs offer these advantages applications such commercial military satellites, deep space probes, types military high reliability equipment. HiRel versions fully compatible allowing designs migrate across different applications that have radiation requirements. Also, HiRel devices used cost prototyping tool designs. programmable architecture these devices offer high performance, design flexibility, fast inexpensive prototyping-all without expense test vectors, charges, long lead times, schedule cost penalties design modifications that required ASIC devices.
Further complementing SX's flexible routing structure hard-wired, constantly-loaded clock network that been tuned provide fast clock propagation with minimal clock skew. Additionally, high performance internal logic eliminated need embed latches flip-flops cells achieve fast clock-to-out fast input set-up times. devices have easy-to-use cells that require instantiation, facilitating design re-use reducing design verification time.
RT54SX16 A54SX16 devices have 16,000 available gates I/Os. RT54SX32 A54SX32 have 32,000 available gates I/Os. these devices support JTAG boundary scan testability. these devices available Ceramic Quad Flat Pack (CQFP) packaging, with 208-pin 256-pin versions. 256-pin version offers user highest capability, while 208-pin version offers compatibility with commercial Plastic Quad Flat Pack (PQFP-208). This compatibility allows user prototype using very cost plastic package then switch ceramic package production. more information plastic packages, refer family FPGAs data sheet A54SX16 A54SX32 manufactured using 0.35µ technology Chartered Semiconductor facility Singapore. These devices offer highest speed performance available FPGAs today. RT54SX16 RT54SX32 manufactured using 0.6µ technology Matsushita (MEC) facility Japan. These devices offer levels radiation survivability excess typical CMOS devices.
Actel's architecture features types logic modules, combinatorial cell (C-cell) register cell (R-cell), each optimized fast efficient mapping synthesized logic functions. Optimal silicon made locating routing interconnect resources metal layers above logic modules, enabling entire floor device spanned with uninterrupted grid fine-grained, synthesis-friendly logic modules "sea-of-modules") which reduces distance signals have travel between logic modules. minimize signal propagation delay, devices employ both local general routing resources. high-speed local routing resources (DirectConnect FastConnect) enable very fast local signal propagation that optimal fast counters, state machines, datapath logic. general system segmented routing tracks allows logic module array connected other logic module. Within this system, propagation delay minimized limiting number antifuse interconnect elements five (typically percent connections only three antifuses). unique local general routing structure featured devices gives fast predictable performance, allows percent pin-locking with full logic utilization, enables concurrent development, reduces design time, allows designers achieve performance goals with minimum effort.
Total dose results summarized ways. First maximum total dose level that reached when parts fail meet device specification remain functional. Actel FPGAs, parameter that exceeds specification first ICC, standby supply current. Second maximum total dose that reached prior functional failure device. devices have varying total dose radiation survivability. ability these devices survive radiation effects both device dependent. customer must evaluate determine applicability these devices their specific design environmental requirements.
Actel will provide total dose radiation testing along with test data each pedigreed that available sale. These reports available website contact your local sales representative receive copy. listing available lots devices will also provided. These results only provided reference customer information. radiation performance summary, Radiation Performance Actel Products http://www.actel.com/hirel. This summary will also show single event upset (SEU) single event latch-up (SEL) testing that been performed Actel FPGAs.
widely variety factors, including limited characteristics orbit, radiation environment, proximity satellite exterior, amount inherent shielding from other sources within satellite actual bare variations. these reasons, Actel does guarantee level radiation survivability, solely responsibility customer determine whether device will meet requirements specific design.
Actel achieved full certification, demonstrating that quality management, procedures, processes, controls place comply with MIL-PRF-38535, performance specification used Department Defense monolithic integrated circuits. certification good example Actel's commitment supplying highest quality products types high-reliability, military space applications. Many suppliers microelectronics components have implemented their primary worldwide business system. Appropriate this system only helps implementation advanced technologies, also allows quality, reliable cost-effective logistics support throughout products' life cycles.
54SX RadTolerant RadHard devices fully supported Actel's line FPGA development tools, including Actel DeskTOP series Designer Advantage tools. Actel DeskTOP Series integrated design environment that includes design entry, simulation, synthesis, place route tools. Designer Advantage Actel's suite FPGA development point tools Workstations that includes ACTgen Macro Builder, Designer with DirectTime timing driven place route analysis tools, device programming software. addition, 54SX RadTolerant RadHard devices contain ActionProbe circuitry that provides built-in access every node design, enabling 100-percent real-time observation analysis device's internal logic nodes without design iteration. probe circuitry accessed Silicon Explorer, easy integrated verification logic analysis tool that sample data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard port, turning into fully functional channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle seconds.
radiation performance information provided information purposes only guaranteed. total dose effects lot-dependent, Actel does guarantee that future devices will continue exhibit similar radiation characteristics. addition, actual performance vary
RT54SX32
Application (Temperature Range) Blank Commercial +70°C) Military (-55 +125°C) MIL-STD-883 E-Flow (Actel Space Level Flow) Package Lead Count Package Type Ceramic Quad Flat Pack Speed Grade Blank Standard Speed Approximately Faster than Standard Part Number A54SX16 A54SX32 RT54SX16 RT54SX32 16,000 Gates 32,000 Gates 16,000 Gates-RadTolerant 32,000 Gates-Rad Tolerant
Speed Grade RT54SX16 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) A54SX16 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) RT54SX32 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) A54SX32 Devices 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) Application
Contact your Actel sales representative product availability. Applications: Commercial Availability: Available Military Planned MIL-STD-883 Planned E-flow (Actel Space Level Flow)
Speed Grade: Approx. Faster than Standard
User I/Os Device RT54SX16 A54SX16 RT54SX32 A54SX32 CQFP 208-Pin CQFP 256-Pin
Table JTAG Functionality
Program Fuse Blown (Dedicated JTAG Mode) TCK, TDI, dedicated JTAG pins need pull-up resistor Program Fuse Blown (Flexible Mode) TCK, TDI, flexible used I/Os pull-up resistor
Package Definitions: CQFP Ceramic Quad Flat Pack (Contact your Actel sales representative product availability.)
devices feature hard-wired IEEE 1149.1 JTAG Boundary Scan Test circuitry offer superior diagnostic testing capabilities providing JTAG probing capabilities. These functions controlled through special JTAG pins conjunction with program fuse. functionality each described Table Figure block diagram A54SX JTAG circuitry Figure page shows RT54SX JTAG circuitry.
dedicated JTAG mode, TCK, TDI, dedicated JTAG pins cannot used regular I/Os. flexible mode, should HIGH through pull-up resistor pulled initiate JTAG sequence. addition, RT54SX devices include TRST which used reset JTAG state machine "test-logic-reset" mode. program fuse determines whether device dedicated flexible mode. default (fuse blown) flexible mode. Regardless which mode chosen, tying TRST will disable JTAG functionality.
Data Registers (DRs)
Instruction Register (IR)
output stage
clocks and/or controls
Power-up Reset
Controller
Figure A54SX JTAG Circuitry
Data Registers (DRs)
Instruction Register (IR)
output stage
clocks and/or controls
TRST external hard-wired
Controller
Figure RT54SX JTAG Circuitry
family architecture designed satisfy next-generation performance integration requirements production-volume designs broad range applications.
nect
interconnect elements, which embedded between layers. antifuses normally open circuit and, when programmed, form permanent low-impedance connection. extremely small size these interconnect elements gives family abundant routing resources provides excellent protection against design pirating. Reverse engineering virtually impossible, because extremely difficult distinguish between programmed unprogrammed antifuses, there configuration bitstream intercept. Additionally, interconnects (i.e., antifuses metal tracks) have lower capacitance lower resistance than other device similar capacity, leading fastest signal propagation industry.
Actel's family provides much more efficient silicon locating routing interconnect resources between Metal (M2) Metal (M3) layers (Figure This completely eliminates channels routing interconnect resources between logic modules implemented SRAM FPGAs previous generations antifuse FPGAs), enables entire floor device spanned with uninterrupted grid logic modules. Interconnection between these logic modules achieved using Actel's patented metal-to-metal programmable antifuse
Routing Tracks
Metal Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Tungsten Plug Metal
Metal Tungsten Plug Contact
Silicon Substrate
Figure Family Interconnect Elements
Logi Modul
family architecture been called "sea-of-modules" architecture because entire floor device covered with grid logic modules with virtually chip area lost interconnect elements routing (see Figure Actel provides types logic modules, register cell (R-cell) combinatorial cell (C-cell). R-cell contains flip-flop featuring more control signals than previous Actel architectures, including asynchronous clear, asynchronous preset, clock enable (using lines). R-cell registers feature programmable clock polarity, selectable register-by-register basis (Figure page This provides designer with additional flexibility while allowing mapping synthesized functions into FPGA. clock source R-cell chosen from hard-wired clock routed clock. C-cell implements range combinatorial functions 5-inputs (Figure page Inclusion input
associated inverter function dramatically increases number combinatorial functions that implemented single module from options previous architectures more than 4,000 architecture. example improved flexibility enabled inversion capability ability integrate 3-input exclusive-OR function into single C-cell. This facilitates construction 9-bit parity-tree functions with propagation delays. same time, C-cell structure extremely synthesis-friendly, simplifying overall design reducing synthesis time.
family's chip architecture provides unique approach module organization chip routing that delivers best register/logic wide variety emerging applications.
Channelled Array Architecture
Sea-of-Modules Architecture
Figure Channelled Array Sea-of-Modules Architectures
Routed Data Input
PSETB Direct Connect Input
HCLK CLKA, CLKB CLRB
Figure R-Cell
Figure C-Cell
Modu gani
Actel arranged C-cell R-cell logic modules into horizontal banks called Clusters. There types Clusters: Type contains C-cells R-cell, while Type contains C-cell R-cells. increase design efficiency device performance, Actel further organized these modules into SuperClusters (see Figure page 10). SuperCluster two-wide grouping Type clusters. SuperCluster two-wide group containing Type cluster Type cluster. devices feature more SuperCluster modules than
SuperCluster modules because designers typically require more combinatorial logic than flip-flops.
Clusters SuperClusters connected through innovative local routing resources called FastConnect DirectConnect that enable extremely fast predictable interconnections modules within Clusters SuperClusters (see Figure Figure page 11). This routing architecture also dramatically reduces number antifuses required complete circuit, ensuring highest possible performance.
R-Cell
Routed Data Input PSETB Direct Connect Input
C-Cell
HCLK CLKA, CLKB CLRB
Cluster
Cluster
Cluster
Cluster
Type SuperCluster
Figure Cluster Organization DirectConnect horizontal routing resource that provides connections from C-cell neighboring R-cell given SuperCluster. DirectConnect uses hard-wired signal path requiring programmable interconnection achieve fast signal propagation time less than FastConnect enables horizontal routing between logic modules within given SuperCluster, vertical routing with SuperCluster immediately below Only programmable connection used FastConnect path, delivering maximum pin-to-pin propagation addition DirectConnect FastConnect, architecture makes globally-oriented routing resources known segmented routing high-drive routing. Actel's segmented routing structure provides
Type SuperCluster
variety track lengths extremely fast routing between SuperClusters. exact combination track lengths antifuses within each path chosen 100% automatic place route software minimize signal propagation delays. Actel's high-drive routing structure provides three clock networks. first clock, called HCLK, hard-wired from HCLK buffer clock select each R-cell. This provides fast propagation path clock signal. hard-wired clock tuned provide clock skew 0.25 remaining clocks (CLKA, CLKB) global clocks that sourced from external pins from internal signal logic within device.
DirectConnect antifuses
FastConnect antifuse
Routing Segments Typically antifuses Max. antifuses
Type SuperClusters
Figure DirectConnect FastConnect Type SuperClusters
DirectConnect antifuses
FastConnect antifuse
Routing Segments Typically antifuses Max. antifuses
Type SuperClusters
Figure DirectConnect FastConnect Type SuperClusters
Symbol VCCR VCCA VCCI TSTG Parameter Supply Voltage Supply Voltage Supply Voltage Input Voltage Output Voltage Source Sink Current
Units Parameter Temperature Range1 3.3V Power2 Supply Tolerance Power Supply Tolerance Commercial Military +125 Units %VCC %VCC
Limits -0.3 +6.0 -0.3 +4.0 -0.3 +4.0 -0.5 +5.5 -0.5 +3.6 +5.0 +125
Storage Temperature
Notes: Stresses beyond those listed Absolute Maximum Ratings table cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Device should operated outside Recommended Operating Conditions. source sink numbers refer tristated inputs outputs
Note: Ambient temperature (TA) used commercial industrial; case temperature (TC) used military. power supplies must recommended operating range 250µs. more information, please refer Power-Up Design Considerations application note http://www.actel.com/appnotes.
Commercial Symbol Parameter (IOH -20µA) (CMOS) (IOH -8mA) (TTL) (IOH -6mA) (TTL) (IOL= 20µA) (CMOS) ICC(D) (IOL 12mA) (TTL) (IOL 8mA) (TTL) Level Inputs High Level Inputs Input Transition Time Capacitance Standby Current, ICC(D) IDynamic Supply Current 0.10 0.50 Min. (VCCI 0.1) Max. VCCI VCCI Min.
Military Max. VCCI VCCI 0.50 Units
(VCCI 0.1)
"Power Dissipation" section page
VCCA
VCCR
VCCI
Power-Up Sequence 5.0V First 3.3V Second 3.3V First 5.0V Second
Comments possible damage device. Possible damage device.
3.3V
5.0V
3.3V
RT54SX16, A54SX16, RT54SX32, A54SX32
VCCA
VCCR
VCCI
Power-Down Sequence 5.0V First 3.3V Second 3.3V First 5.0V Second
Comments Possible damage device. possible damage device.
3.3V
5.0V
3.3V
device junction case thermal characteristic junction ambient characteristic thermal characteristics shown with different flow rates.
Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed RT54SX16 CQFP 256-pin package military temperature still follows:
Max. junction temp. (°C) Max. ambient temp. (°C) 150°C 125°C Absolute Maximum Power Allowed 1.09W (°C/W) 23°C/W
Package Type RT54SX16 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) RT54SX32 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) A54SX16 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) A54SX32 Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack (CQFP) °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Count Still Units
[ICCstandby ICCactive] VCCA *(VCCA VOH) where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. Accurate values difficult determine because they depend design system I/O. power divided into components: static active.
ponen
totempole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation.
acit
power dissipated CMOS circuit expressed Equation Power (µW) VCCA2 where: VCCA Equivalent capacitance Power supply volts Switching frequency
power standby current typically small component overall power. Standby power shown below military, worst case conditions (70°C). 3.6V Power
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCCA. Equivalent capacitance frequency-independent that results used over wide range operating conditions. Equivalent capacitance values shown below.
(pF)
ower nent
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency-dependent, function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation
calculate active power dissipated from complete design, switching frequency each part logic must known. Equation shows piece-wise linear summation over components. Power =VCCA2 CEQM fm)modules CEQI fn)inputs+ (CEQO fp)outputs+ CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2+ fq2)routed_Clk2 CEQCD fs1)dedicated_CLK]
RT54SX16 Equivalent Capacitance (pF) Modules Input Buffers Output Buffers Routed Array Clock Buffer Loads Dedicated Clock Buffer Loads Fixed Capacitance (pF) routed_Clk1 routed_Clk2 Fixed Clock Loads Clock Loads Dedicated Array Clock CEQM CEQI CEQO CEQCR CEQCD 10.0 0.25
A54SX16
RT54SX32
A54SX32
0.15
10.0 0.34
0.23
1,080
1,080
where: CEQM CEQI CEQO CEQCR CEQCD Number logic modules switching Number input buffers switching Number output buffers switching Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock Fixed number clock loads dedicated array clock (528 A54SX16) Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers Equivalent capacitance routed array clock Equivalent capacitance dedicated array clock Output lead capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate
hing ency
determine switching frequency design, must have detailed understanding data input values circuit. following guidelines meant represent worst-case scenarios that they generally used predict upper limits power dissipation. These guidelines follows: Logic Modules Inputs Switching Outputs Switching modules inputs/4 output/4 sequential modules sequential modules F/10 F/10
First Routed Array Clock Loads (q1) Second Routed Array Clock Loads (q2) Load Capacitance (CL) Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average First Routed Array Clock Rate (fq1)
Average Output Switching Rate (fp)
Average Second Routed Array Clock Rate (fq2) Average Dedicated Array Clock Rate (fs1)
(Normalized Worst-Case Commercial, 3.0V)
Junction Temperature (TJ) VCCA 0.78 0.73 0.69 0.87 0.82 0.77 0.89 0.83 0.78 1.00 0.93 0.87 1.04 0.97 0.92 1.16 1.08 1.02
Input Delays Module tINY
Internal Delays Combinatorial Cell tIRD2
Predicted Routing Delays
Output Delays Module
tDHL =0.9 tRD1 tRD4 tRD8
Module tDHL
Register Cell
Register Cell
tRD1
tRD1 tENZH
tSUD Routed Clock tRCO tRCKH (100% Load) FMAX Hard-Wired Clock tRCO
tHCKH
FHMAX *Values shown A54SX16-1 worst-case commercial conditions.
External Set-Up tINY tIRD1 tSUD tHCKH Clock-to-Out (Pin-to-Pin) tHCKH tRCO tRD1 tDHL
External Set-Up tINY tIRD1 tSUD tRCKH Clock-to-Out (Pin-to-Pin) tRCKH tRCO tRD1 tDHL
TRIBUFF test loads (shown below)
tDLH 1.5V tDHL 1.5V
1.5V tENZL tENLZ
1.5V tENZH tENHZ
Load (Used measure propagation delay) Load (Used measure rising/falling edges) output under test
output under test
tPLZ/tPZL tPHZ/tPZH
INBUF
tINY 1.5V 1.5V tINY
Flop
PRESET
(Positive edge triggered) tSUD tHPWH, tRPWH tHPWL, tRPWL
tRCO
tCLR tWASYN PRESET
tPRESET
Timing characteristics 54SX devices fall into three categories: family-dependent, device-dependent, design-dependent. input output buffer characteristics common 54SX family members. Internal routing delays device dependent. Design dependency means actual delays determined until after placement routing user's design complete. Delay values then determined using DirectTime Analyzer utility performing simulation with post-layout delays.
Some nets design long tracks. Long tracks special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes five antifuse connections. This increases capacitance resistance, resulting longer delays macros connected long tracks. Typically nets fully utilized device require long tracks. Long tracks contribute approximately delay. This additional delay represented statistically higher fanout (FO=24) routing delays data sheet specifications section.
Propagation delays expressed only typical nets, which used initial design performance evaluation. Critical delays then applied most time-critical paths. Critical nets determined property assignment prior placement routing. percent nets design designated critical, while percent nets design typical.
54SX devices manufactured CMOS process. Therefore, device performance varies according temperature, voltage, process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, worst-case processing.
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
C-Cell Propagation Delays1 Parameter Description Internal Array Module
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay
12.4
11.0 14.6
Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Module Input Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Predicted Input Routing Delays3 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay 12.4 11.0 14.6
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
Module Output Timing1 Parameter tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Description Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Delta HIGH Delta HIGH
`-1' Speed Min. Max. 0.05 0.05
`Std' Speed Min. Max. 0.06 0.08 Units ns/pF ns/pF
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Note: Delays based loading, except tENZL tENZH tENZL tENZH loading
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
C-Cell Propagation Delays1 Parameter Description Internal Array Module
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay
10.1 17.0 22.4
11.9 19.8 26.3
Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Module Input Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Predicted Input Routing Delays3 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay 10.1 17.0 22.4 11.9 19.8 26.3
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
Module Output Timing1 Parameter tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Description Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Delta HIGH Delta HIGH
`-1' Speed Min. Max. 0.09 0.09
`Std' Speed Min. Max. 0.11 0.15 Units ns/pF ns/pF
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Note: Delays based loading, except tENZL tENZH tENZL tENZH loading
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
C-Cell Propagation Delays1 Parameter Description Internal Array Module
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay
12.4
11.0 14.6
Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Module Input Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Predicted Input Routing Delays3 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay 12.4 11.0 14.6
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
Module Output Timing1 Parameter tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Description Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Delta HIGH Delta HIGH
`-1' Speed Min. Max. 0.05 0.05
`Std' Speed Min. Max. 0.06 0.08 Units ns/pF ns/pF
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Note: Delays based loading, except tENZL tENZH tENZL tENZH loading
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
C-Cell Propagation Delays1 Parameter Description Internal Array Module
`-1' Speed Min. Max.
`Std' Speed Min. Max. Units
Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 tRD18 tRD24 R-Cell Timing tRCO tCLR tSUD tWASYN
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay
10.1 17.0 22.4
11.9 19.8 26.3
Sequential Clock-to-Q Asynchronous Clear-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width
Module Input Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y
Predicted Input Routing Delays3 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tIRD18 tIRD24 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay FO=18 Routing Delay FO=24 Routing Delay 10.1 17.0 22.4 11.9 19.8 26.3
Notes: dual-module macros, tRD1 tPDn tRCO tRD1 tPDn tPD1 tRD1 tSUD whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual worst-case performance. Post-route timing based actual routing delay measurements performed device prior shipment.
(continued)
(Worst-Case Military Conditions, 4.75V, CCA, 3.0V,
Module Output Timing1 Parameter tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL Description Data-to-Pad HIGH Data-to-Pad HIGH Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Enable-to-Pad, Delta HIGH Delta HIGH
`-1' Speed Min. Max. 0.09 0.09
`Std' Speed Min. Max. 0.11 0.15 Units ns/pF ns/pF
Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW fHMAX Input HIGH (Pad R-Cell Input) Input HIGH (Pad R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (Light Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (50% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Input HIGH (100% Load) (Pad R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Note: Delays based loading, except tENZL tENZH tENZL tENZH loading
CLKA Clock (Input)
Test Data Input (Input)
clock input clock distribution networks. clock input buffered prior clocking R-cells. used, this must HIGH board. must left floating.
CLKB Clock (Input)
Serial input JTAG diagnostic probe. flexible mode, active when (Table page This functions when JTAG state machine reaches "logic reset" state.
Test Data Output (output)
clock input clock distribution networks. clock input buffered prior clocking R-cells. used, this must HIGH board. must left floating.
Ground
Serial output JTAG. flexible mode, active when (Table page This functions when JTAG state machine reaches "logic reset" state.
Test Mode Select (Input)
supply voltage.
HCLK Dedicated (Hard-wired) Array Clock (Input)
clock input sequential modules. This input directly wired each R-cell offers clock speeds independent number R-cells being driven. used, this must HIGH board. must left floating.
Input/Output (Input, Output)
functions input, output, three-state, bi-directional buffer. Input output levels compatible with standard CMOS specifications. Unused pins tri-stated Designer Series software.
Connection
controls JTAG pins (TCK, TDI, TDO). flexible mode, when LOW, TCK, TDI, pins JTAG pins (Table page Once JTAG pins JTAG mode they will remain JTAG mode until internal JTAG state machine reaches "logic reset" state. this point JTAG pins will released will function regular pins. "logic reset" state reached cycles after HIGH. dedicated JTAG mode, functions specified IEEE 499.1 JTAG Specifications. JTAG operation further described page
TRST Test Reset (Input)
This connected circuitry within device.
ActionProbe (Output)
Probe used output data from user-defined design node within device. This independent diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed.
ActionProbe (Output)
JTAG reset (active LOW). This used reset JTAG state machine "test-logic-reset" state avoid accidental shifts into various JTAG operations effects heavy ions radiation environment. When this tied LOW, device held "test-logic-reset" state JTAG functionality cannot used. When this tied HIGH, JTAG function operate. This should left floating.
3.3V Supply Voltage
Supply voltage I/Os.
3.3V Supply Voltage
Supply voltage Array.
5.0V Supply Voltage
Probe used output data from node within device. This diagnostic used conjunction with Probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed.
Test Clock (Input)
Supply voltage input tolerance (required internal biasing). Table Supply Voltages
Maximum Maximum Input Output Tolerance Drive 3.3V 5.0V 3.3V 3.3V
Test clock input diagnostic probe device programming. flexible mode, becomes active when (Table page This functions when JTAG state machine reaches "logic reset" state.
A54SX16 A54SX32 RTSX16 RTSX32
3.3V 3.3V
3.3V 3.3V
5.0V 5.0V
208-Pin CQFP (Top View)
Index
208-Pin CQFP
54SX Family FPGAs RadTolerant HiRel
208-
Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function TDI, VCCI VCCR VCCA TRST VCCI VCCA Number A54SX16 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO, RT54SX16 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO, A54SX32 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO, RT54SX32 Function VCCI PRB, VCCA VCCR HCLK VCCI TDO,
TDI, TDI, TDI, VCCI VCCI VCCI VCCR VCCR VCCR VCCA VCCA VCCA TRST VCCI VCCI VCCI VCCA VCCA VCCA Notes: RT54SX16 RT54SX32-CQ208 TRST pins. A54SX32 RT54SX32-CQ208 Connects.
208-
Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function VCCA VCCI VCCA VCCR VCCA VCCI Number A54SX16 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK, RT54SX16 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK, A54SX32 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK, RT54SX32 Function VCCI CLKA CLKB VCCR VCCA PRA, VCCI TCK,
VCCA VCCA VCCA VCCI VCCI VCCI VCCA VCCA VCCA VCCR VCCR VCCR VCCA VCCA VCCA VCCI VCCI VCCI Notes: RT54SX16 RT54SX32-CQ208 TRST pins. A54SX32 RT54SX32-CQ208 Connects.
(continued)
256-
Index
256-Pin CQFP
256-Pin CQFP
Number A54SX16 Function TDI, VCCI VCCA VCCA RT54SX16 Function TDI, VCCI VCCA TRST VCCA A54SX32 Function TDI, VCCI VCCA VCCA RT54SX32 Function TDI, VCCI VCCA TRST VCCA Number A54SX16 Function PRB, VCCI VCCA HCLK RT54SX16 Function PRB, VCCI VCCA HCLK A54SX32 Function PRB, VCCI VCCA HCLK RT54SX32 Function PRB, VCCI VCCA HCLK
Note: RT54SX16 RT54SX32-CQ256 TRST pins.
256-Pin CQFP (Continued)
Number A54SX16 Function TDO, VCCA RT54SX16 Function TDO, VCCA A54SX32 Function TDO, VCCA RT54SX32 Function TDO, VCCA Number A54SX16 Function VCCR VCCI VCCA RT54SX16 Function VCCR VCCI VCCA A54SX32 Function VCCR VCCI VCCA RT54SX32 Function VCCR VCCI VCCA
Note: RT54SX16 RT54SX32-CQ256 TRST pins.
256-Pin CQFP (Continued)
Number A54SX16 Function CLKA CLKB VCCI VCCR PRA, RT54SX16 Function CLKA CLKB VCCI VCCR PRA, A54SX32 Function CLKA CLKB VCCI VCCR PRA, RT54SX32 Function CLKA CLKB VCCI VCCR PRA, Number A54SX16 Function TCK, RT54SX16 Function TCK, A54SX32 Function TCK, RT54SX32 Function TCK,
Note: RT54SX16 RT54SX32-CQ256 TRST pins.
208-
View
Ceramic
Side View
Heat Sink CQ256
Lead Kovar
Notes: Outside lead frame holes (from dimension circular. Seal ring connected Ground. Lead material Kovar with minimum microinches gold plate over nickel. Packages shipped unformed with ceramic bar. CQ256 Heat Sink back.
Flat
CQFP Dimension D1/E1 D2/E2 74.60 6.86 Min. 2.20 2.05 0.18 0.10 28.96 Nom. 2.44 2.29 0.20 0.15 29.21 25.50 0.50 7.75 70.00 65.90 75.00 75.40 74.62 0.38 8.64 7.67 Max. 2.67 2.52 0.22 0.20 29.46 Min. 2.19 2.04 0.18 0.10 35.64
CQFP Nom. 2.44 2.29 0.20 0.15 36.00 31.50 0.50 7.75 70.00 65.90 75.00 0.51 75.38 0.64 7.83 Max. 2.69 2.50 0.22 0.18 36.36
Notes: dimensions millimeters. equals Basic Spacing between Centers. This theoretical true position dimension tolerance.
54SX Family FPGAs RadTolerant HiRel
following table lists critical changes that were made current version document.
Previous version
Changes current version (Preliminary 1.5.1 (web-only)) Power down sequencing information modified: damage device possible when 3.3V powered first when 5.0V powered down first.
Page
Preliminary v1.5
last line equation previous version. been replaced existing version.
54SX Family FPGAs RadTolerant HiRel
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User I/Os 1,080 Dedicated Flip-Flops Tested Total Ionizing Dose (

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