8-bit Enhanced Processor General Purpose, Protocol Engines Roboti

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AB181E-20
8-bit Enhanced Processor
General Purpose, Protocol Engines Robotics Applications
Combines High Performance Low-Cost
AB181E-20 Protocol Engine Processor
Product Specification
Semicon AB181E-20General Purpose Protocol Engine Processor Product Specification
latest information AB181E-20, check product specification Semicon website http://www.ab-semicon.com
Copyright Copyright 1999 Semicon Limited. rights reserved. part this publication reproduced, transmitted, transcribed, stored retrieval system, translated into language computer language, form third party, without prior written permission Semicon Limited.
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AB181E-20General Purpose Protocol Engine Cycle Architecture Processor
answer every Z80, Z180, HD64180 user world horsepower were looking for, have re-write your code, your existing Assemblers, Linkers Ccompilers. Some minor differences exist.
Features: frequency synthesized processor Memory Memory Block Transfer Mbytes/sec Memory Memory Block Transfer Mbytes/sec Data Address Synchronous serial suitable Apple Local Talk 1Mbaud Asynchronous Serial 2Mbaud suitable IrDA 2Mbit/s Fixed point arithmetic unit 100pin Quad Flat Pack packaging 16bit Timers Dual 3.3/5V operation single 3.3V Each Clock cycle MHz) instruction (for single byte instructions) instruction carried last byte fetch multi-byte instruction
Contents
Introduction
Chip Structure Applications Programmer Guide Hardware Guide
Device Details
Packaging Information Assignment Current Consumption Frequency AB181E-20
Overview
AB181E-20 Architecture Internal Registers Table Registers Addressing Notes Dynamic Refresh Control Refresh Control RESET Dynamic Refresh Operation Notes Logical Address Spaces Logical Physical Address Translation
Memory Management Unit (MMU)
Wait State Control Block Diagram Register Register Description Physical Address Translation RESET Register Access Timing
Interrupt Control
Interrupt Control Registers Flags INT/TRAP Control Register (ITC) TRAP Interrupt External Interrupts Internal Interrupts Interrupt Acknowledge Cycle Timing Interrupt Sources RESET
Asynchronous Serial Communication Interface (ASCI)
ASCI Block Diagram ASCI Register Description ASCI Baud Rate Prescale Register PRSCALE Modem Control Signals ASCI Interrupts ASCI RESET
Direct Memory Access (DMA)
DMAC Register Description Operation Timing DMAC Channel Priority DMAC BUSREQ*, BUSACK* DMAC Internal Interrupts DMAC DMAC RESET
Programmable Reload Timer (PRT)
Block Diagram Register Description
Clocked Serial Port (CSI/O)
CSI/0 Block Diagram CSI/0 Register Description CSI/O Interrupts CSI/O Operation CSI/O Operation Notes CSI/O RESET CSI/O Operation Timing Notes
Arithmetic Unit
Arithmetic Registers
Timing Information
Basic Timing Read Cycle Timing Write Cycle Timing Refresh Cycle Timing Grant Timing Wait State Generation Clock Generation Crystal Oscillator Filter Network External Clock
Appendices
OP-Code Maps
Introduction
This guide provides product information specifications AB181E-20 General Purpose Protocol Engine Processor, detailing performance capability this fast, state-of-the-art microprocessor using Semicon's unique (One Cycle Architecture) technology. Applications include: Network Connected Devices Digital Cameras Cell Phones Automotive Motor Controllers Digital Signal Processing kHz) Robotics/Motion Control
Figure
Laser Printer
Digital Copier
Chip Structure
processor core processor driven 5MHz crystal oscillator phase locked loop (PLL) which generates chip 40MHz clock. address connected outside world giving 20bit externally addressable space. channels Memory Memory Memory Memory available. processor wakes Wait State Mode allowing lower speed external used.
External Address External Data
Core
Timer Timer 16bit Async Serial
40MHz
Memory Logic
Syncro Serial
Fixed Point Arithmetic
Functional Blocks
Figure
Applications
chip used many different applications most powerful protocol engine applications such Network Controller modem controller multi function Copiers, Laser Printers, BubbleJet Printers Machines. fixed point arithmetic unit makes AB181 ideal robotics other closed-loop servo systems. Application where existing Processor already fully utilised this cost Protocol Engine Processor take over work handling Network Protocol Stacks provide data printer controller. also handle SNMP data from Printer Controller NPMPmanagement information without taking Main Printer Controllers time.
Digital Copier Application Multi Function Printer AB181E-20 very good match Digital Copier Designs Multi Function Printer/Scanner Designs. allows Network Modem connectivity achieved extremely hardware cost board space. following diagram shows typical Digital Copier Design making AB181E-20 processor.
Printing Mechanism
Scanner Mechanism
Front Panel Display
AB181E-20 Motor Control Laser Control Sensors
Scanner Control AB-2QX
Front Panel Display Processor AB181E-20
Raster Image Processor Scanned Image Parser Image
Printer Page PCL5 Language Processor convert Raster Image (Option)
2061-33G interface Protocol Engine Processor AB181E-20 layer Network
Figure
Programmer Guide
Operationally, AB181E-20 compatible with classic CPU. programmer same register sets, uses same op-codes. With exceptions (noted later), program that designed will function AB181E-20 with little modification. addition instruction set, AB181E-20 some extra instructions designed increase efficiency many common applications. well core, AB181E-20 also some on-chip peripherals that easily accessed programmer, makes device very powerful most applications without need plethora support logic usually required Z80. These peripherals code functionally compatible with "180" processors manufactured Zilog Hitachi. peripherals included on-chip are: versatile wait-state generator that programmed insert different wait-states different areas memory, order allow different speed memories used. Memory Management Unit (MMU) that allows total addressed memory range 1048576 bytes addressing). channels, allowing memory-memory memory-I/O transfers background. clock-timers, which programmed interrupt regular intervals and/or generate hardware signal. Asynchronous Serial Communications ports that allow RS232 channels, either internally externally clocked. synchronous serial Communications port, allow inter-processor communication. Also suitable downloading many popular FPGA devices. channel interrupt handler. DRAM refresh circuit (same Z80). This disabled high-speed operation. Afixed-point arithmetic unit optimised control applications.
following list exceptions instruction that need taken into account when porting code: interrupt modes supported. AB181E-20 uses interrupt mode only. interrupt mode instructions treated NOPs. interrupt acknowledge cycles generated. fast internal state machine, software timing loops will execute much faster than Z80. This need taken into account with some programs. AB181E-20 powers with maximum wait states, DRAM refresh cycles enabled. obtain maximum performance some additional instructions should inserted during initialisation phase optimum configuration. -9Ver
some undocumented instructions, such being able load upper lower bits index register independently. This used handful programs, especially some "copy protected" code. AB181E-20 does support undocumented instructions.
Hardware Guide
AB181E-20 interface signals follow classic conventions, interfacing straightforward using conventional logic, configurable logic devices. Internally, state-machine been greatly enhanced give very fast code execution times. Most instructions have internal states, AB181E-20 (without wait-states) will execute based memory access internal clock cycle. internal clock runs times crystal speed. This internal clock available output pin. this difference, fact that conventional peripherals cannot used (they slow), hardware state signals provided. This should present down-sides, AB181E-20 used most applications replacement processors. internal wait-state generator, fast memory necessity, although faster execution times naturally available wait-states avoided. With wait-state, there least three-fold increase speed over fastest processor currently available, five-fold increase usual with faster memory wait-states. Some applications will even more dramatic improvement, because "block" instructions (e.g. LDIR) greatly enhanced. external -WAIT- input different timing that 180. Generally this makes interfacing easier, -WAIT- asserted together with -IOE- -ME-, without needing gate or-WR- signals. consideration that trip unwary however. core logic AB181E-20 operates 3.3V, this must provided. pins capable either 3.3V true operation, depending upon what voltage applied power supply pins. Thus AB181E-20 suitable either 3.3V circuits. use, simple zener-diode voltage dropping circuit ample supply low-current core. operates times core frequency (see timing diagrams) which times crystal frequency.
Device Details
Packaging Information
following diagram shows packaging AB181E-20 Protocol Engine Processor:
Index corner
Figure
Packaging Information
0°7°
Figure
Symbol
Control Dimensions Alternative Dimensions millimetres inches Nominal Nominal 2.80 3.40 0.110 0.134 0.25 0.85 0.010 0.033 2.55 3.05 0.100 0.120 23.65 24.15 0.931 0.951 19.80 20.20 0.780 0.795 18.85 REF. 0.742 REF. 17.65 18.15 0.695 0.715 13.80 14.20 0.543 0.559 12.35 REF. 0.486 REF. 0.73 1.03 0.029 0.041 0.65 BSC. 0.026 BSC. 0.22 0.38 0.009 0.015 0.11 0.23 0.004 0.009 features NOTE RECTANGULAR
Conforms JEDEC MO-112 CC-1 Iss.
Note: This package rectangular
Assignment
Signal
Designator
input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output
A<0> A<1> A<2> A<3> A<4> A<5> A<6> A<7> MixVdd 3.3/5V A<8> A<9> A<10> A<11> A<12> A<13> A<14> A<15> A<16>
Assignment
Signal
Designator
Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Output Output Output
MixVdd 3.3/5V MixVdd 3.3/5V MixVdd 3.3/5V MixVdd 3.3/5V A<19> /TOUT D<0> D<1> D<2> D<3> D<4> D<5> D<6> D<7> RTSO CTSO DCDO TXAO A<17> A<18> MixVdd 3.3/5V MixVdd 3.3/5V
Assignment
Signal
Designator
Input Input/Output Output -Input Input/Output Output Input Output Input Output Output Output Output Output Output Output
MixVdd 3.3/5V MixVdd 3.3/5V RXAO CKAO/DREQO TXA1 RXA1 CKA1/TENDO RXS/CTS1 MixVdd 3.3/5V DREQ1 TEND1 HALT
Assignment
Signal
Designator
Output Input Input Input Input Input Output Input Output Input Input
MixVss MixVss MixVss MixVss INTO INT1 INT2 MixVdd 3.3/5V Vdd3 3.3V Vdd3 3.3V sig) EXTAL sig) XTAL sig) WAIT BUSACK RESET BUSREQ
Notes:
Connect MixVss pins Connect pins 3.3V. MixVdd pins must connected same voltage (either 3.3V). voltage MixVdd pins determines operating voltage pins. Regardless voltage MixVdd, EXTAL test pins 3.3V inputs only.
Current Consumption Frequency AB181E-20
Current Consumption (mA)
Internal Frequency (MHz)
(3.3V) Core Supply Supply (5V)
Frequency (5V) (3V3) 1.39 2.08 3.43 4.44 6.65 9.99 12.35 13.26 15.72
(5V) 4.98 5.01 4.93
(3V3) 3.28 3.28 3.28 3.28 3.28 3.196
Overview
AB181E-20 Architecture
AB181E-20 five functional blocks: Central Processing Unit: AB181E-20 uses superset instruction set, with interface signals that follow conventions, using conventional logic configurable logic devices. been engineered give very fast code execution times. addition instruction set, AB181E-20 includes extra instructions increase efficiency many common applications. clock generator consists crystal oscillator Phased locked loop (PLL) which generates on-chip 40MHz 20MHz clocks. This performs control status activity associated with on-chip peripherals, including exchanges, reset cycles, DRAM refresh, wait state timing.
Clock Generator:
State Controller:
Memory Management Unit:The allows user increase available memory from (for Z80) Byte. This achieved with common banked area structure. Interrupt Controller: order provide correct responses from CPU, interrupt controller monitors prioritizes various external internal interrupts traps.
AB181E-20 five on-chip peripherals: Asynchronous Serial Communications Interface (ASCI channels): ASCI provides full-duplex UARTs. Each channel includes programmable baud rate generator modem control signals. Controller: controller provides high speed transfers from memory memory, memory to/from I/O, I/O. supports modes request cycle steal. transfers access complete 1Mbyte addressing range.
Programmable Reload Timer (PRT channels): consists separate channels containing timer count reload register. Before reaching counters, system clock provides time base required. Channel optional output that enables waveform generation. Clock Serial (CSIO): CSIO channel enables synchronous high-speed data communication with other microprocessors, microcomputers peripherals using halfduplex serial transmitter receiver.
Fixed Point Arithmetic Unit: FPAU designed provide functionality that aids control servo motors robotics applications. also provides 32-bit multiplyaccumulate function.
Internal Registers
internal registers AB180-20 occupy addresses between reset. avoid conflicts with external devices these registers relocated within bottom bytes address space.
Control Registers IOA7 IOA6
[7:6] Address Relocation These bits relocate internal registers shown below Table
[7:6]
[7:6]
[7:6]
[7:6]
Table
00FFh
0000h 00BFh
0080h 007Fh
0040h 003Fh
00BFh
Table Registers
Address Register ASCI Control Register ASCI Control Register ASCI Control Register ASCI ASCI Control Register ASCI Status Register ASCI Status Register ASCI Transmit Data Register ASCI Transmit Data Register ASCI Receive Data Register ASCI Receive Data Register CSI/0 CSI/O Control Register CSI/O Transmit/Receive Data Register Timer Data Register Timer Data Register Reload Register Timer Reload Register Timer Control Register Reserved Mnemonic CNTLA0 CNTLA1 CNTLB0 CNTLB1 STAT0 STAT1 TDR0 TDR1 RDR0 RDR1 CNTR TRDR TMDROL TMDROH RLDROL RLDROH Binary XX000000 XX000001 XX000010 XX000011 XX000100 XX000101 XX000110 XX000111 XX001000 XX001001 XX001010 XX001011 XX001100 XX001101 XX001110 XX001111 XX010000 Hexadecimal
XX010011 Timer Data Register Timer Data Register Reload Register Reload Register ASCI Baud Rate Prescaler TMDR1L TMDR1H RLDR1L RLDR1H PRSCALE XX010100 XX010101 XX010110 XX010111 XX011000
XX011001 Reserved XX011111
Unused
XX010001
Address Register Source Address Register Source Address Register Source Address Register Destination Address Register Destination Address Register Destination Address Register Byte Count Register Byte Register Memory Address Register Memory Address Register Memory Address Register Address Register Address Register Internal Wait Control Register Byte Count Register Status Register Mode Register DMA/ WAIT Control Register Register (INT VEctor Register) INT/ TRAP Control Register Reserved Refresh Refresh Control Register Reserved Common Base Register Bank Base Register Common/Bank Area Register FPAU Register Access Port_LOW BYTE Register Access Port_HIGH BYTE Control/Status Register CBAR RP_LO RP_HI Mnemonic SAROL SAROH SAROB DAROL DAROH DAROB BCROL BCROH MAR1L MAR1H MAR1B IAR1L IAR1H IMWR BCR1H DSTAT DMODE DCNTL Binary XX100000 XX100001 XX100010 XX100011 XX100100 XX100101 XX100110 XX100111 XX101000 XX101001 XX101010 XX101011 XX101100 XX101101 XX101111 XX110000 XX110001 XX110010 XX110011 XX110100 XX110101 XX110110 XX110111 XX111000 XX111001 XX111010 XX111011 XX111100 Hexadecimal
AUCNTRL XX111101
Address Register Reserved Control Register Mnemonic Binary XX111110 XX111111 Hexadecimal
Addressing Notes
on-chip register addresses located address space from 0000H 00FFH (16-bit addresses). order access on-chip registers (using instruction), high-order bits 16-bit address must conventional instruction (OUT (m),A/ OUTI /INI etc.) place contents register high-order bits address bus, difficult accessing chip registers. more efficient on-chip register access, AB181E-20 additional instructions above Z180 which force high-order bits address These instructions IN0, OUT0, OTIMR, OTDMR TSTIO (See Appendicies back this book). When writing internal register, same write occurs external bus. However, duplicate external write cycle will exhibit internal write cycle timing. example, WAIT* input programmable wait state generator ignored. This will same internal read cycles however, external read data ignored AB181E-20. advised that external addresses should chosen avoid overlap with internal addresses. This avoids duplicate accesses.
Dynamic Refresh Control
AB181E-20 incorporates dynamic refresh control circuit including refresh address generation programmable refresh timing. This circuit generates asynchronous refresh cycles inserted programmable interval independent program execution. systems which don't dynamic RAM, refresh function disabled. When internal refresh controller determines that refresh cycle should occur, current cycle inserted placing refresh address A0-A7 REF* output driven LOW. programming REFW (Refresh Wait) (Refresh Control Register), refresh cycles clock cycle either three. external WAIT* input internal wait state generator effective during refresh. Fig.6 shows timing refresh cycle with refresh wait (Trw) cycle.
Refresh Cycle Trw* MCi+1
Refresh signal (Internal signal) Refresh address
Note: three cycles specified, inserted. Otherwise, inserted. Machine Cycle
Figure
Refresh Timing
Refresh Control Register (RCR) sets interval length refresh cycles enables disables refresh function. REFE REFW CYC1 CYC0
REFE: Refresh Enable (bit REFE disables refresh controller while REFE enables refresh cycle insertion. REFE during RESET. REFW: Refresh Wait (bit REFW causes refresh cycle clocks duration. REFW causes refresh cycle three clocks duration adding refresh wait cycle (Trw). REFW during RESET. CYC1,0: Cycle Interval (bit 1,0) These bits specify interval between refresh cycles.
CYC1 CYC0 Interval (Cycles PHY) Interval 20MHz) 11.7 15.5 19.5
Reset CYC1,0 cleared giving shortest refresh interval. case dynamic RAMs requiring refresh cycles every cycles every 4ms), required refresh interval less than equal 15.625
Refresh Control RESET
After RESET, based initialised value RCR, refresh cycles will occur with interval clock cycles clock cycles duration.
Dynamic Refresh Operation Notes
Refresh cycle insertion stopped when following states. During RESET When released response BUSREQ* During WAIT states Refresh cycles suppressed when released response BUSREQ*, refresh timer continues operate, time which first refresh cycle occurs after AB181E-20 re-acquires depends refresh timer. There timing relationship with exchange. Note: each refresh cycle will refresh address that increased from previous refresh cycle (This each completed refresh cycle, each refresh request).
Logical Address Spaces
bytes logical address space interpreted consisting three separate logical address areas, Common Area Bank Area Common Area displays logical memory configurations that possible. boundaries between Common Bank areas programmes with bytes resolution.
Common Area Common Area Common Area Common Area Bank Area
Common Area
Bank Area Common Area
Figure
Logical Address Mapping Examples
Logical Physical Address Translation
example which three logical address space portions mapped into bytes physical address space. seen that Common Bank areas overlap that Common Area Bank Area relocated bytes physical address boundaries). Common Area exists) always based physical address
FFFFFH
FFFFH Common Area Bank Area
Common Base Bank Base
0000H
Common Area Logical Space
Physical Space 00000H
Figure
Logical Physical Mapping Example
Memory Management Unit (MMU)
AB181E-20 contains on-chip which performs translation bytes (16-bit addresses- 0000H FFFFH) logical memory address space into bytes (20-bit addresses- 00000H toFFFFFH) physical memory address space. Address translation performed internally parallel with other operation.
Memory Wait State Control
Each logical memory address space have independantly assigned number wait states. This controlled through IMWR register (2dh). internal memory register function similar Z180, with following additions. Internal Memory Wait Control Register (IMWR Address 2dH). Waits Common Area Bank Area Common Area Read Strobe Mode Normal Edge Mode Suppression)
#Waits
When using IMWR different numbers wait states each bank required that following restriction observed:
Wait State Control
number wait states inserted controller during cycles through DMA/ WAIT Control Register (DCNTL). DMA/WAIT Control Register (DCNTL Address 32H) IWII IWI0 DMS1 DMS0 DIM1 DIM0
IWII IWIO bits control number wait states automatically inserted into cycles controller.
IWII IWIO Waits
Reset IWII IWI0 giving wait states cycles. details DMSn DIMn bits refer Controller section.
Block Diagram
shows block diagram. translates internal 16-bit logical addresses external 20-bit physical addresses.
Internal Address/Data LA12 LA15
Common/Bank Area Register; CBAR Memory Management Unit Common Base Register; CBAR Bank Base Register;
PA12 PA19
Figure
Logical Address Physical Address
Block Diagram
Whether address translation takes place depends type cycle follows: Memory Cycles Address Translation occurs memory access cycles including instruction operational fetchs, memory data reads write, hardware interrupt vector fetch software interrupt restarts. Cycles logically bypassed cycles. 16-bit logical address space corresponds directly with 16-bit physical address space. four high order bits (A16-A19) physical address always during cycles.
LA15 "0000" PA19 Logical Address PA15
PA16
Physical Address
Figure
Address Translation
Cycles When AB181E-20 on-chip DMAC using external bus, physically bypassed. 20-bit source destination registers DMAC directly output physical address (AOA19).
Register
Three registers used program specific configuration logical physical memory. Common/Bank Area Register (CBAR) Common Base Register (CBR) Bank Base Register (BBR)
CBAR used define logical memory organisation. used relocate logical areas within 512k bytes physical address space. resolution setting boundaries within space relocation within physical space bytes. fiels CBAR determines start address Common Area (Up-per Common) default, address Bank Area. field determines start address Bank Area default, address Common Area (Lower Common). field CBAR programmed subject restriction that never less than show examples logical memory organisations associated with different values
Common Area
Common Area
Common Area
Common Area Bank Area Bank Area Common Area Common Area
Common Area Lower limit address Bank Area Lower limit address 0000H
Common Area Lower limit address Bank Area Lower limit address 0000H (RESET condition)
Common Area Lower limit address Bank Area Lower limit address 0000H
Common Area Lower limit address Bank Area Lower limit address 0000H
Figure
Logical Memory Organisation
FFFFH
Common/Bank Area Register
D000H CFFFH
Common Area
Bank Area
Common/Bank Area Register
4000H 3FFFH Common Area 0000H
Figure
Logical Space Configuration (Example)
Register Description
Common/Bank Area Register (CBAR) CBAR specifies boundaries within AB181E-20 bytes logical address space three areas, Common Area Bank Area Common Area Common/Bank Area Register (CBAR Address 3AH)
CA3-CA0: (bits 7-4) specifies start (low) address bytes boundaries) Common Area This also determines last address Bank Area. bits during RESET. BA3-BAO: (bits 3-0) specifies start (low) address bytes boundaries) Bank Area. This also determines last address Common Area bits reset during RESET. Common Base Register (CBR) specifies base address boundaries) used generate 19-bit physical address Common Area accesses. bits reset during RESET. Common/Bank Area Register (CBAR Address 38H)
Bank Base Register (BBR) specifies base address boundaries) used generate 19-bit physical address Common Area accesses. bits reset during RESET. Bank Base Register (BBR Address 39H)
Physical Address Translation
shows which physical addresses generated based contents CBAR, BBR. comparators classify access logical area defined CBAR. Depending which three potential logical areas (Common Area Bank Area Common Area being accessed, appropriate 7-bit base address added high-order bits logical address, yeilding 20-bit physical address. associated with Common Area accesses. Common Area accesses internal base register (non-accessible) which contains Thus, Common Area defined, always based physical address
Logical Address (64K)
Common/ Bank Area Register
Comparator
Common/ Bank Area Register
Common Base Reg.
Bank Base Reg.
Adder
Physical Address (1M)
Figure
Physical Address Generation
Reset
During REST, bits field CBAR bits field CBAR, reset logical bytes address space corresponds directly with first bytes (0000H FFFFH) bytes (00000H FFFFFH) physical address space, after RESET AB181E-20 will begin execution logical physical address
Register Access Timing
When data written into CBAR, BBR, value will effective from cycle immediately following write cycle which updates these registers. Note: care must taken during programming insure that program execution disrupted. next cycle following register programming will normally op-code fetch from newly translated address. ensuring this localise programming routines Common Area that always enabled.
Interrupt Control
AB181E-20 thirteen interrupt sources, four external nine internal, with fixed priority.
Higher Priority
(10) (11) (12) (13)
TRAP (Undefined Op-code Trap) Internal Interrupt (Non Maskable Interrupt) INT0 (Maskable Interrupt Level External Interrupt INT1 (Maskable Interrupt Level INT2 (Maskable Interrupt Level Timer Timer channel channel Internal Interrupt Clocked Serial Port Asynchronous channel Asynchronous channel Arithmetic Unit
Figure
Interrupt Sources
This section explains registers associated with interrupt processing, TRAP interrupt, interrupt response modes external interrupts. full information internal interrupt generation other than TRAP sections ASCI, DMA, CSI/O required.
Interrupt Control Registers Flags
AB181E-20 contains three registers flags which associated with interrupt processing. Function Interrupt Vector High Interrupt Vector Interrupt/Trap Control Interrupt Enable Flag Name IEF1,2 Access Method instructions instruction (addr=33H) instruction (addrs=34H) instructions
Interrupt Vector Register External interrupts INT1, INT2 internal interrupts (except TRAP) programmable vectored technique (similar mode determine address which interrupt processing starts. response interrupt 16-bit address generated. This address accesses vector table memory obtain address which execution restarts. generates jump 0038h methods generation least significant byte table address different, vectors contents most significant byte table address. programming contents vector tables relocated bytes boundaries throughout logical address space. Note: that read/written with instructions rather than (IN, OUT) instructions. initialized during RESET.
Interrupt Vector Register (IL) Interrupt Vector Register (IL: Address 33H)
Programmable
Interrupt Source Dependent Code
This register determines most significant three bits order byte interrupt vector table address external interrupt INT1 INT2 internal interrupts (except TRAP). five least significant bits fixed each specific interrupt source. programming vector table relocated bytes boundaries. initialised during RESET.
INT/TRAP Control Register (ITC)
INT/TRAP Control Register (ITC Address 34H) TRAP ITE2 ITE1
used handle TRAP interrupts enable disable external maskable interrupt inputs INT0*, INT1* INT2*. TRAP (bit This when undefined up-code fetched. TRAP reset under program control writing with however cannot written with under program control. TRAP reset during RESET. UFO: Undefined Feth Object (bit When TRAP interrupt occurs (TRAP contents allow determination starting address undefined instruction. This necessary since TRAP occur either third byte op-code. allows stacked value (stacked response TRAP) correctly adjusted. first op-code should interpreted stacked first op-code address stacked PC-2. read-only. ITE2, 1,0: Interrupt Enable (bits 2-0) ITE2, ITE1, ITE0 enable disable external interrupt inputs INT2*, INT1* INT0* respectively. reset interrupt masked. During RESET, ITE0 initialised while ITE1 ITE2 initialised
Interrupt Enable Flag (IEF1,2) IEF1 controls overall enabling disabling internal external maskable interrupts (i.e. interrupts except TRAP). IEF1 maskable interrupts disabled. IEF1 reset (Disable Interrupts) instruction (Enable Interrupts) instruction. purpose IEF2 correctly manage occurance NMI. During prior interrupt reception state saved maskable interrupts automatically disabled (IEF1 copied IEF2 then IEF1 cleared interrupt service routine, execution RETN (Return from Non-maskable Interrupt) will automaticaly restore interrupt receiving state copying IEF2 IEF1) prior occurance NMI. IEF2 state reflected Status register execution instructions. Table shows state IEF1 IEF2.
Operation RESET RETN Interrupt except TRAP RET1 TRAP
IEF1 IEF2
IEF2 IEF1 affected
REMARKS Inhibits interrupt except TRAP Copies contents IEF1 IEF2 Returns from service routine Inhibits interrupt
affected affected affected affected Transfers contents IEF2 flag Transfers contents IEF2 flag
affected affected affected affected
Table
State IEF1 IEF2
TRAP Interrupt
AB181E-20 creates non-maskableTRAP interrupt when undefined op-code fetch occurs (This affected IEF1). This feature used increase software reliability, implement 'extended' instruction set, both. TRAP occur during op-code fetch cycles. When TRAP interrupt occurs AB181E-20 operates follows; TRAP Interrupt TRAP/Control (ITC) register
current (Program Counter) value, reflecting location after undefined op-code, saved stack. AB181E-20 vectors logical address logical address mapped physical address vector same RESET. Testing TRAP will reveal whether restart physical address caused RESET TRAP. state (Undefined Fetch Object) allows TRAP handling software correctly adjust stacked depending whether second third byte op-code generated TRAP. starting address invalid instruction equal stacked PC-2. starting address invalid instruction equal stacked PC-4. shows TRAP Timing.
op-code fetch cycle
op-code fetch cycle
stacking
Restart from 0000H
A0~A18 D0~D7
Undefined op-code op-code address op-code address SP-1 SP-2 0000H
Figure
TRAP Op-code Undefined
op-code fetch cycle
op-code fetch cycle
op-code fetch cycle
Memory read cycle
stacking
Restart from 0000H
A0~A18 D0~D7
Undefined op-code op-code address op-code address op-code address
Figure
TRAP Op-code Undefined
External Interrupts
AB181E-20 four external hardware interrupt inputs. Non-Maskable Interrupt INT0 Maskable Interrupt Level INT1 Maskable Interrupt Level INT2 Maskable Interrupt Level NMI, INT0, INT1 INT2 have fixed interrupt response modes. Non-Maskable Interrupt NMI* interrupt input edge sensitive cannot masked software. When NMI* detected, AB181E-20 operates follows: DMAC operation suspended clearing (DMA Main Enable) DCNTL. pushed onto stack. contents IEF1 copied IEF2. This saves interrupt reception state that existed prior NMI. IEF1 cleared This disables external internal maskable interrupts except TRAP). Execution commences logical address 66H. last instruction service routine should RETN (Return from Non-maskable Interrupt). This restores stacked allowing interrupted program continue, RETN causes IEF2 copied IEF1, restoring interrupt reception state that existed prior NMI. Note: since accepted during AB181E-20 on-chip DMAC operation, used externally interrupt transfer. service routine reactivate abort operation required application. Special care must taken insure that interrupt inputs over service routine. Unlimited NMI* inputs without corresponding number RETN instructions will eventually cause stack overflow. shows RETN Fig. details response timing. response sequence activated internally latched edge sensitive NMI* input detected rising edge
main program
IEF1
IEF2 IEF1 (SP-1) (SP-2) 0066H Interrupt Handling program
IEF1 IEF2 (SP) (SP+1)
RETN
Figure
Sequence
Acknowledge Cycle Push Stack Restart From 0066H Op-Code Fetch
A0-A18 SP-1 SP-2 0066H
D0-D7
Figure
Timing
INT0 Maskable Interrupt Level next highest priority external interrupt after INT0. interrupt masked either IEF1 flag ITE0 (Interrupt Enable reset Note that after RESET state follows: IEF1 INT0 masked. ITE0 INT0 enabled execution (Enable Interrupts) instruction. INT0 When INT0* received, stacked instruction execution restarts logical address 38H. Both IEF1 IEF2 flags reset disabling maskable interrupts. interrupt service routine normally terminates with (Enable Interrupts) instruction followed RETI (Return Interrupt) instruction, that interrupts re-enabled. shows INT0 RETI. shows INT0 Response Timing.
IEF1,2 (SP-1) (SP-2)
0038H
INT0 Interrupt Manipulation program
INT0 (Mode
(SP) (SP+1)
IEF1,2) RETI
Figure INT0 Interrupt Sequence Note that TRAP interrupt will occur invalid instruction fetched during interrupt acknowledge cycle.
INT0 Acknowledge Cycle Push Stack
Op-Code Fetch
INT0 INT1 INT2 A0~A18 SP-1 SP-2 0038H
D0~D
Figure
INT0 Timing
INT1, INT2 operation external interrupts INT1 INT2 vector mode. INT1 INT2 generate loworder byte vector table address using (interrupt Vector Low) register this also interrupt response used internal interrupts (except TRAP). low-order byte vector table address comprised most signficant three bits software programmable register while least significant five bits unique fixed value each interrupt (INT1, INT2 internal) source. This shown INT1* INT2* globally masked IEF1 Each also individually maskable respectively clearing ITE1 ITE2 (bits register During RESET, IEF1, ITE1 ITE2 bits reset
Internal Interrupts
Internal interrupts (except TRAP) same vectored response mode INT1 INT2. Internal interrupts globally masked Individual internal interrupts enabled/disabled programming each individual peripheral (ASCI, DMAC, PRT, FPAU, CSI/O) control register. Table summary lower vector INT1, INT2 internal interrupts.
Memory
16-bit Vector
Fixed Code bit)
Vector Vector
High-order starting address
Bytes
Low-order starting address
Offset
Figure
INT1, INT2 Internal Interrupts Vector Acquisition
Interrupt Source INT1 INT2 Timer channel Timer channel channel channel CSI/O ASCI channel ASCI channel Arithmetic Unit
Priority Highest Lowest
Fixed Code
*Programmable Table Interrupt Source Lower Vector
Interrupt Acknowledge Cycle Timing
Fig. shows interrupt acknowledge cycle timing internal interrupts, INT1 INT2.
Normal Programme Execution INT1, INT2, Internal Interrupt Acknowledge Cycle OpCode Vector Table Fetch Stacking Cycle Read
50NS
INT0 INT1 INT2 A0~A18 Vector Starting SP-1 SP-2 Vector Address
D0~D7 Start Start OpAdd code High
Machine Cycle
Figure
INT1, INT2 Internal Interrupts Timing
Interrupt Sources RESET
Register bits reset locates vector tables starting logical address vectored interrupts (INT0 INT1, INT2 internal interrupts) will overlap with fixed restart interrupts like RESET (0), (66H), INT0 Mode (38H) (00H 38H). vector table(s) built elsewhere memory located bytes boundaries reprogramming with instruction. Register Bits reset register programmed locate vector INT1, INT2 internal interrupts bytes sub-boundaries within bytes area spcified IEF1, IEF2 Flags Reset This disables Interrupts other than TRAP. Register ITE0 ITE1, ITE2 reset INT0* INT2* requires that ITE1 ITE2 bits respectively writing ITC. Control Registers Interrupt enable bits reset AB181E-20 on-chip peripheral interrupts disabled individually enabled writing each control register interrupt enable bit.
Asynchronous Serial Communication Interface (ASCI)
AB181E-20 on-chip ASCI contains independent full duplex channels. flexibility ASCI allows direct communication with wide variety standard UARTs (Universal Asynchronous Receiver Transmitter) functions ASCI shown below. Each channel independently programmable. Full duplex communication 8-bit data length stop bits Odd, even, parity Parity, overrun, framing error detection Programmable baud rate generator, modes Speed 125k bits second (CPU MHz) Modem control signals Channel DCD0*, CTS0* RTS0* Channel CTS1* Programmable interrupt condition enable disable Operation with on-chip DMAC Flexible prescaler allows standard baud rates with crystal frequency
ASCI Block Diagram
Transmit Data Register
Transmit Data Register
TDR0
Transmit Shift Register* TSR0
Transmit Shift Register* TSR1
Receive Data Register RDR0
ASCI
Receive Data Register RDR1
RXA0
Receive Shift Register* RSR0(8)
Receive Shift Register* RSR1
CNTLA0
Control Register
Control
Control Register CNTLA1
CTS0
Control Register CNTLB0(8)
Control Register CNTLB1(8)
Status Register STAT0(8)
Status Register STAT1(8)
CKA1 Figure
Baud Rate Generator
Baud Rate Generator
TDR1
Internal Address Data
Interrupt Request
RXA1
CTS1
ASCI Block Diagram
ASCI Register Description
Transmit Shift Register (TSRO, When Transmit Shift Register receives data from Transmit Data Register (TDR) data shifted pin. When transmission completed, next byte available) automatically loaded from into next transmission starts. outputs continuous High level data available transmission. This register program accessible. Transmit Data Register (TDR0,1: Address 06H, 07H) Data written Transmit Data Register transferred when empty. Data written while shifting previous byte data, making ASCI transmitter double buffered. Receive Shift Register (RSRO,1) This register receives data shifted pin. When full, data automatically transferred Receive Data Register (RDR) empty. empty when next incoming data byte shifted overrun error occurs. This register program accessible. Receive Data Register (RDRO, 1:I/O Address 08H, 09H) When complete incoming data byte assembled RSR, automatically transferred empty. next incoming data byte shifted into while contains previous received data byte, ASCI receiver double buffered. ASCI Status Register (STAT0, Each channel status register allows interrogation ASCI communication, error modem control signal status well enabling disabling ASCI interrupts. ASCI Status Register (STAT0 Address 04H)
TDRE
RDRF OVRN
ASCI Status Register (STAT1 Address 05H) CTSIE TDRE
RDRF OVRN
RDRF Receive Data Register Full (bit RDRF when incoming data byte loaded into RDR. framing parity error occurs, RDRF still received data (which generated error) still loaded into RDR. RDRF cleared reading RDR, when DCD* input HIGH, IOSTOP mode during RESET.
OVRN: Overrun Error (bit OVRN when full becomes full. OVRN cleared when (Error Flag Reset) CNTLA written when DCD* HIGH, IOSTOP mode during RESET. Parity Error (bit when parity error detected incoming data byte ASCI parity detection enable (the MOD1 CNTLA cleared when (Error Flag Reset) CNTLA written when DCD* HIGH, IOSTOP mode during RESET. Framing Error (bit receive data byte frame delimited invalid stop (i.e. should cleared when (Error Flag Reset) CNTLA written when DCD* HIGH, IOSTOP mode during RESET. RIE: Receive Interrupt Enable (bit should enable ASCI receive interrupt requests. When flags RDRF, OVRN, become interrupt request generated. channel interrupt will also generated transition external DCD0* input from HIGH. cleared during RESET. DCD0*: Data Carrier Detect (bit STAT0) Channel extenal DCD0* input pin. DCD0* when DCD0* input high. cleared first read STAT0 following DCD0* input transition from high during RESET. When DCD0* receiver unit reset receiver operation inhibited. CTS1E: Channel CTS* Enable (bit STAT1) Channel external CTS1* input (pin which multiplexed with receive data (RXS) CSI/O (Clocked Serial Port). Setting CTS1E selects CTs1* function clearing CTS1E selects function. TDRE: Transmit Data Register Empty (bit TDRE indicates that empty next transmit data byte written TDR. After byte written TDR, TDRE cleared until ASCI transfers bytes from TSR, which time TDRE again TDRS IOSTP mode during RESET. When external CTS* input HIGH, TDRE reset TIE: Transmit Interrupt Enable (bit should enable ASCI transmit interrupt requests. interrupt will requested when TDRE cleared during RESET. ASCI Control Register (CNTLA0, Each ASCI Channel Control Register configures major operating modes such receiver/transmitter enable disable, data format, multiprocessor communication mode. ASCI Control Register (CNTLA0 Address 00H) RTSO
MOD2 MOD1 MOD0
ASCI Control Register (CNTLA0 Address 01H) CKA1D
MOD2 MOD1 MOD0
Receiver Enable (bit When ASCI receiver enabled. When reset receiver disabled receive operation progress interrupted, RDRF error flags reset previous contents RDRF error flags held. cleared IOSTOP mode during RESET. Transmitter Enable (bit When ASCI transmitter enabled. When reset transmitter disabled transmit operation progress interrupted. However, TDRE flag reset previous contents TDRE held. cleared IOSTOP mode during RESET. RTSO* Request Send Channel (bit inCNTLA0) When RTS0* reset RTS0* output will low. When RTS0* RTS0* output immediately goes high. RTS0* during RESET. CKA1D: CKA1 Clock Disable (bit CNTLA1) When CKA1D multiplexed CKA1/TEND0* (pin used TEND0* function. When CKA1D used CKA1, external data clock input/output channel CKA1D cleared during RESET. EFR: Error Flag Reset (bit When written function selected reset error flags (OVRN, undefined during RESET. MOD2, 1,0: ASCI Data Format Mode (bits 2-0) These bits program ASCI data format follows MOD2 data data MOD1 MOD0 stop stop bits
Parity Parity enabled
data formats available based combinations MOD1 MOD0 shown follows. MOD2 MOD1 MOD0 Data Format Start data stop Start data stop Start data parity stop Start data parity stop Start data stop Start data stop Start data parity stop Start data parity stop
ASCI Control Register (CNTLB0, Each ASCI channel control register configures multiprocessor mode, parity baud rate selection. ASCI Control Register (CNTLB0 Address 02H) ASCI Control Register (CNTLB1 Address 03H) CTS*: Clearto Send When read, CTS* reflects state external CTS* input. CTS* input high, CTS* will read When CTS* input high, TDRE inhibited (i.e. held channel CTS1* input multiplexed with (Cloaked Serial Receive Data), CTS* only valid when read channel CTS1E CTS1* input function selected. read data CTS* affected RESET.
PEO: Parity Even (bit selects even parity. does affect enabling/disabling parity (MOD1 CNTLA). cleared even parity selected. parity selected. cleared during RESET. Divide Ratio (bit specifies divider used obtain baud rate from data sampling clock. reset divide used while divide used. cleared during RESET. SS2, Source/Speed Select (bits 2-0) Specify data clock source (internal external) baud rate prescale factor. SS2, SS1, during RESET. Table shows divide ratio corresponding SS2, SS0. Table Divide Ratio external clock Divide Ratio external ASCI channel data clock pins multiplexed with control lines (CKA0/DREQ0* CKA1/TEND0*). During RESET, these pins initialised ASCI data clock input. SS2, reprogrammed (any other value than SS2, these pins become ASCI data clock outputs. However, DMAC channel configured perform memory (and memory mapped transfers CKA0/DREQ0* pins revert control signals regardless SS2, SS1, programming. Also, CKA1D CNTLA register then CKA1/TEND0* reverts Control output function regardless SS2, programming.
Final data clock rates based PRSCALE, SS2, SS1, clock
ASCI Baud Rate Prescale Register PRSCALE
value written this location determines division ratio prescaler ASCI baud rate generators. This prescaler drives ASCI0 ASCI1. baud rate determined (XTAL frequency PRSCALE DR=0
DR=1
divide ratio Table
Zero invalid value, unpredictable behaviour result. Reading this register will return number from free-running counter.
Modem Control Signals
ASCI channel CTS0*, DCD0* RTS0* external modem control signals. ASCI channel aCTS1* modem signal which multiplexed with (Clocked Serial Receive Data). CTS0*: Clear Send (input) CTS0* input allows external control (start/stop) ASCI channel transmit operation. When CTS0* high, channel TDRE held regardless whether TDR0 (Transmit Data Register) full empty. When CTS0* low, TDRE reflects state TDR0. actual transmit operation disabled CTS0* HIGH, only TDRE inhibited. DCD0*: Data Carrier DEtect (input) DCD0* input allows external control (start/stop) ASCI channel receive operations. When DCD0* high, channel RDRF held regardless whether RDR0 (Receive Data Register) full empty. error flags (PE, OVRN bits) also held Even after DCD0* input goes low, these bits will resume normal operation until status register (STAT0) read. This first read STAT0, while enabling normal operation, will still indicate DCD0* input high (DCD0* even though gone low, STAT0 register should read twice ensure DCD0* reset RTS0*: Request Send (output) RTS0* allows ASCI start stop another communication device transmission (for example, connection that device CTS* input). RTS0* output port, having side effects other ASCI registers flags. CTS1*: Clear Send (input) Channel CTS1* input multiplexed with pins (Clocked Serial Receive Data). CTS1* function selected when CTS1E STAT1 When enabled, CTS1* operation equivalent CTS0*. Modem control signal timing shown
DCD0
DCD0 Flag Status Register Read
Figure
Instruction Write Cycle
DCD0 Timing
Flag RIS0
Figure
RTS0 Timing
ASCI Interrupts
Fig. shows ASCI interrupt request generation circuit.
DCD0 RDRF0 OVRN0 RDRF1 OVRN1 RIE1 TDRE1 TIE1 ASCI1 Interrupt Request RIE0 TDRE0 TIE0 ASCI0 Interrupt Request
Figure
ASCI Interrupt Request Circuit Diagram
ASCI DMAC Operation Operation ASCI with on-chip DMAC channel requires DMAC correctly configured utilise ASCI flags request signals. ASCI RESET During RESET, ASCI status controls registers initialised defined individual register descriptions. Receive Transmit operation stopped during RESET, contents transmit receive data register (TDR RDR) changed RESET.
Direct Memory Access (DMA)
Controller (DMAC) AB181E-20- contains channel (Direct Memory Access) controller which supports high speed data transfer. Both channels (channel channel have following capabilities. Memory Address Space Memory source destination addresses specified anywhere within bytes physical address space using 20-bit source destination memory addresses. Memory transfer also cross bytes physical address boundaries arbitrarily, without intervention. Address Space source destination addresses directly specified anywhere within bytes address space (16-bit source destination addresses). Transfer Length bytes transferred based 16-bit count register. DREQ* Length Level edge sense DREQ* input detection selectable. TEND* Output Used indicate completion external devices. Transfer Rate Each byte transfer occur every three cycles. Wait states inserted cycles slow memory devices. system clock 20MHz, transfer rate high megabytes/second wait states). Additional feature disc interrupt request END. Each channel additional specific capabilities. Channel Memory memory, memory I/O, memory memory mapped transfers Memory address increment, decrement, np-change from both ASCI channels Channel Higher priority then DMAC channel Memory transfer Memory address increment, decrement DMAC Registers Each channel DMAC (channel three registers specifically associated with that channel. Channel SAR0 DAR0 BCR0 Channel MAR1 IAR1 BCR1
Source Address Register Destination Address Register Byte Count Register
Memory Address Register Address Register Byte Count Register
channels share three additional registers common. DSTAT Status Register DMODE Mode Register DCNTL Control Register
Internal Address/Data
Source Address Register SARO (20) Destination Address Register DARO (20)
Status Register DSTAT
Priority Request
DREQ
Mode Register DMODE DMA/WAIT Control Register DCNTL
Control
DREQ
Byte Count Register BCRO(16) Memory Address Register MAR1 (20)
Address Register IARI (16) Byte Count Register BCR1 (16)
Control
Control
TEND0 TEND1 Interrupt Request Incrementer/Decrementer (19)
DMAC Block Diagram
DMAC Register Description
Channel Source Address Register (SARO: Address 22H) Specifies physical source address channel transfers. register contains bits specify bytes memory addresses bytes addresses. Channel source memory, memory mapped I/O. Channel Destination Address Register (DAR0: Address 25H) Specifies physical destination address channel transfers. register contains bits specify bytes memory addresses bytes addresses. Channel destination memory, memory mapped I/O. Channel Bytes Count Register (BCR0: Address 27H) Specifies number bytes transferred. This register contains bits specify bytes transfers. When byte transferred, register decremented one. bytes should transferred, must stored before operation. Channel Memory Address Register (MAR1: Address 2AH) Specifies physical memory address channel transfers. This destination source memory address. This register contains bits specify bytes memory addresses.
Channel Address Register (IAR1: Address 2CH) Specifies address channel transfers. This destination source address. This register contains bits specify bytes addresses. Channel Byte Count Register (BCR1: Address 2FH) Specifies number bytes transferred. This register contains bits specify bytes transfers. When byte transferred, register decremented one. Status Register (DSTAT) DSTAT used enable disable transfer termination interrupts. DSTAT also allows determining status transfer progress completed). Status Register (DSTAT Address 30H) DWE1 DWE0 DIE1 DIE0
DE1: Enable Channel (bit When channel enabled. When transfer terminates (BCR1 reset DMAC. When interrupt enabled (DIE1 interrupt request made CPU. perform software write DE1, DWE1* should written with during same register write access. Writing disables channel DMA, restartable. Writing enables channel automatically sets (DMA Main Enable) cleared during RESET. DEO: Enable Channel (bit When channel enabled. When transfer terminates (BCR0 reset DMAC. When interrupt enabled (DIE0 interrupt request made CPU. perform software write DEO, DWE0* should written with during same register write access. Writing disables channel DMA. Writing enables channel automatically sets (DMA Main Enable) cleared during RESET. DWE1*: Write Enable (bit When performing software write DE1, DWE1* should written with during same access. DWE1* write value held DWE1* always read DWE0*: Write Enable (bit When performaing software write DE0, DWE0* should written with during same access. DWE0* write value held DWE0* always read DIE1: Interrupt Enable Channel (bit When DIE1 termination channel transfer (indicated when causes interrupt request generated. When DIE1 channel termination interrupt disabled. DIE1 cleared during RESET.
DIE0: Interrupt Enable Channel (bit When DIE0 termination channel transfer (indicated when causes interrupt request generated. When DIE0 channel termination interrupt disabled. DIE0 cleared during RESET. DME: Main Enable (bit operation only enabled when (DE0 channel channel When occurs, reset thus disabling activity during interrupt service routine. restart DMA, and/or should written with (even contents already This automatically sets allowing operations continue. Note that cannot directly written. cleared indirectly setting cleared during RESET. Mode Register (DMODE) DMODE used addressing transfer mode channel Mode Register (DMODE Address 31H) MMOD
DM1, DM0: Destination Mode Channel (bits 5-4) Specifies whether destination channel transfers memory, memory mapped corresponding address modifier. cleared during RESET. Memory/ Memory Memory Memory Address Increment/Decrement fixed fixed
SM1, SM0: Source Mode Channel (bits 3-2) Specifies whether source channel transfers memory, memory mapped corresponding address modifier. cleared during RESET. Memory/ Memory Memory Memory Address Increment/Decrement fixed fixed
following Table shows transfer mode combinations DM0, DM1, SM0, SM1. Since transfers implemented, twelve combinations available.
Transfer Mode Address Increment/Decrement SAR+1, DAR+1 SAR-1, DAR+1 fixed, DAR+1 fixed, DAR+1 SAR+1, DAR-1 SAR-1, DAR-1 fixed, DAR-1 fixed, DAR-1 SAR+1, fixed SAR-1, fixed
Memory Memory Memory Memory Memory mapped Memory Memory Memory Memory Memory Memory Memory mapped Memory Memory Memory Memory mapped Memory Memory mapped reserved reserved Memory Memory reserved reserved
SAR+1, fixed SAR-1, fixed
channel with source destination, DREQ0* input times transfer. MMOD Mode When this written with takes available cycles memory-memory mode program execution paused until transfer (Burst Mode). When shared between execution engine permitting program execution continue whilst transfer takes place (Cycle Steal). DMA/WAIT Control Register (DCNTL) DCNTL controls insertion wait states into DMAC (and CPU) accesses request mode each DREQ* (DREQ* DREQ1*) input defined level edge sense. DCNTL also sets transfer mode channel which limited transfers.
DMA/WAIT Control Register (DCNTL Address 32H) IWII IWI0 DMS1 DMS0 DIM1 DIM0
IWI1, IWI0: Wait Insertion (bits 5-4) Specifies number wait states introduced into DMAC access cycles. IWI1 IWI0 during RESET (see Wait State Control section under Memory Management Unit details). DMS1, DMS0: Request Sense (bits 3-2) DMS1 DMS0 specify request sense channel (DREQ0*) channel (DREQ1*) respectively. When reset input level sense when input edge sense. DMS1 DMS0 cleared RESET. DIM1, DIM0: Channel Memory Mode (bits 1-0) Specifies source/destination address modifier channel memory transfer modes. cleared during RESET.
Table
Memory/ Memory Memory Memory Memory
Address Increment/Decrement MAR+1, fixed MAR-1, fixed fixed, MAR+1 fixed, MAR-1 Channel Transfer Mode
Operation
This section discusses three operation modes channel memory memory, memory memory memory mapped I/O. also describes operation channel with on-chip ASCI (Asynchronous Serial Communication Interface), well Channel DMA. Memory Memory Channel memory memory transfers, external DREQ0* input used transfer timing. operation will automatically proceed until termination shown byte count (BCR0)
Perform following operations initiate memory memory channel Load memory source destination addresses into SAR0 DAR0. Specify memory memory mode addresses increment/decrement SM0, SM1, bits DMODE. Load number bytes transfer BCR0. Program (with DWE0* same access) DSTAT operation will start machine cycle later. interrupt occurs same time, DIE0 should Memory (Memory Mapped I/O) Channel memory (and memory memory mapped I/O) DREQ0* input used time transfers. addition, TEND0* (transfer End) output used indicate last (byte count register, BCR0 transfer. DREQ0* input programmed level edge sensitive. When level sense programmed, operation begins when DREQ0* sampled low. DREQ0* sampled high, control relinquished AB181E-20-CPU after next byte transfer. When edge sense programmed, operation begins falling edge DREQ0*. another falling edge during write cycle, DMAC continues operating. edge detected, given control after current byte transfer completes. will continue operating until DREQ0* falling detected which time operation will (re) start During transfer channel TEND0* output will synchronous with write cycle last (BCR0 transfer DREQ0* TEND0* pins programmable multiplexed with CKA1 ASCI clock input/outputs. However, when channel programmed memory (and memory memory mapped I/O) transfers, CKA0/DREQ0* automatically functions input even been programmed output CKA0. CKA01/TEND0* functions output TEND0* setting CKA1D CNTLA1. initiate memory (and memory memory mapped I/O) transfer channel perform following operations. Load memory memory source destination addresses into SAR0 DAR0. addresses (not memory mapped I/O) limited bits (A0-A15). Make sure that bits (A18 don't care) correctly enable external DREQ0* input. Specify memory memory memory mapped mode address increment/decrement SM0, SM1, bits DMODE. Load number bytes transfer BCR0. Specify whether DREQ0* edge level sense programming DMS0 DCNTL. Enable disable termination interrupt with DIE0 DSTAT. Program (with DWE0* same access) DSTAT operation will begin under control DREQ0* input. Memory ASCI Channel Channel extra capability support transfer from on-chip channel ASCI. Here external DREQ0* input used timing, ASCI status bits used generate internal DREQ0*. TDRE (Transmit Data Register Empty) RDRF (Receive Data Register Full) used generate internal DREQ0* ASCI transmission reception respectively.
initiate memory ASCI transfer, perform following operations: Load source destination addresses into SAR0 DAR0. Specify (ASCI) address follows: Bits A0-A7 should contain address ASCI channel transmitter receiver (I/O addresses 6H9H). Bits A8-A15 should equal Bits A17-A16 should according following table enable appropraite ASCI status internal request.
SAR18
SAR17
SAR16
Transfer Request DREQ0 RDRF (ASCI channel RDRF (ASCI channel reserved
don't care DAR18 don't care Specify memory transfer mode address increment/decrement SM0, SM1, bits DMODE. Load number bytes BCR0. request sense mode (DMS0 DCNTL) must specified 'edge sense'. Enable disableDMA termination interrupt with DIE0 DSTAT. Program (with DWE0* same access) DSTAT operation with ASCI will begin under control ASCI generated internal request. ASCI receiver transmitter being used must initialised allow first transfer begin. ASCI receiver must empty shown RDRF ASCI transmitter must full shown TDRE first byte should written ASCI Transmit Data Register under program control. remaining byte will transferred using DMA. Channel channel perform memory transfers. Except different registers status/control bits, operation exactly same described channel memory DMA. DAR17 DAR16 Transfer Request DREQ0 TDRE (ASCI channel TDRE (ASCI channel reserved
initiate channel memory operation perform following operations: Load memory address bits) into MAR1. Load address bits) into IAR1. Program source/destination address increment/decrement mode using DIM1 DIM0 DCNTL. Specify whether DREQ1* level edge sense DMS1 DCNTL. Enable disable termination interrupt with DIE1 DSTAT. Program (with DWE1* same access) DSTAT operation with external device will begin using external DREQ1* input TEND1* output.
Timing
When memory (and memory mapped I/O) specified source destination, goes during memory access. When specified source destination, IOE* goes during access. When (and memory mapped I/O) specified source destination, timing controlled external DREQ* input TEND* output indicates termination. external devices overlap addresses with internal control register, even using DMA. Wait states inserted programming on-chip wait state generator using external WAIT* input. memory memory transfer (channel only), external DREQ0* input ignored.
DMAC Channel Priority
simultaneous DREQ* request, channel priority over channel When channel performing memory memory transfer, channel cannot operate until channel operation terminated. channel operating, channel cannot operate until channel releases control bus.
DMAC BUSREQ*, BUSACK*
BUSREQ* BUSACK* inputs allow another master take control AB181E-20 bus. BUSREQ* BUSACK* have priority over on-chip DMAC will suspend DMAC operation. DMAC releases external master breakpoint DMAC memory access. Since single byte DMAC transfer requires read write cycle, possible DMAC suspended after DMAC read, before DMAC write. Even this case, when external master releases AB181E-20 (BUSREQ* HIGH), on-chip DMAC will correctly continue suspended operation.
DMAC Internal Interrupts
DIE0
DMA0 interrupt interrupt Request Request
Figure32
DMAC Interrupt Request Circuit Diagram
automatically cleared AB181E-20 completion (byte count operation chanel channel respectively. They remain until written. Since level sense, interrupt will occur IEF1 termination interrupt service routine should disable further interrupt programming channel before enabling interrupts (i.e. IEF1 After reloading DMAC address count register, reenable channel interrupt, same time resume programming channel
DMAC
NMI, unlike other interrupts, automatically disables DMAC operation clearing DSTAT. interrupt service routine respond time critical events without delay DMAC usage effectively used external abort input, recognising that both channels suspended clearing DME. falling edge occurs before falling clock state prior Tw), DMAC will suspended will start response current cycle. setting channels that channels operation restarted will correctly resume from point which suspended NMI. DMAC RESET During RESET bits DSTAT, DMODE DCNTL initialised stated their individual register description. operation progress stopped allowing perform REST sequence address register (SAR0, DAR0, MAR1, IAR1) byte count register (BCR0, BCR1) contents stopped during RESET.
Programmable Reload Timer (PRT)
AB181E-20 contains 16-bit Programmable Reload Timers. Each channel contains 16bit down counter 16-bit reload register. down counter directly read written down counter overflow interrupt programmed enabled disabled. channel also TOUT output (pin multiplexed with A19) which high toggled, PRT1 programmed perform output waveform generation.
Block Diagram
shows block diagram. channels have separate timer data reload registers common status/control register. input clock both channels equal system clock divided Internal Address/Data
Timer Data Timer Data Register Register TMDR0L TMDR0H Timer Reload Timer Reload Register Register RLDR0L RLDR0H Timer Data Timer Data Register Register Tout TMDR1L TMDR1H Timer Reload Timer Reload Register Register TLDR1L TLDR1H Timer Control Register Interrupt Request
Figure
Block Diagram
Register Description
Timer Data Register (TMDR: Address CH0: ODH, CH1: 15H, 14H) PRT0 PRT1 each have 16-bit Timber Data Registers (TMDR). TMDR0 TMDR1 each accessed high byte registers (TMDR0H, TMDR0L TMDR1H, TMDR1L). During RESET, TMDR0 TMDR1 FFFFH. TMDR decremented once every twenty clocks. When TMDR counts down automatically reloaded with value contained Reload Register (RLDR). TMDR read written software using following procedures. read procedure uses internal temporary storage return accurate data without requiring timer stopped. write procedure requires that timer stopped. reading (without stopping timer), TMDR must read order lower byte higher byte (TMDRnL, TMDRnH). lower byte read (TMDRnL) will store higher byte value internal register. following higher byte read (TMDRnH) will access this internal register. This procedure ensures timer data validity eliminating problem potential 16-bit timer updating beween each read. Note that reading TMDR higher byte lower byte order result invalid data, that there implications TMDR higher byte internal storage applications which read only lower and/or higher bytes. normal operation TMDR read routines should access both lower higher bytes, that order.
writing, TMDR down counting must inhibited using TDE(Timber Down Count Enable) bits (Timer Control Register), following which both higher lower bytes TMDR freely written (and read) inany order. Reload Register (RLDR: Address CH0: OEH, CH1: 16H, 17H) PRT0 PRT1 each have timer Reload Registers (RLDR0). RLDR0 RLDR1 each accessed high byte registers (RLDE0H, RLDR0L RLDR1H, RLDR1L). During RESET RLDR0 RLDR1 FFFFH. When TMDR counts down automatically reloaded with contents RLDR. Timer Control Register monitors both channel (PRT0, PRT1) TMDR status controls enabling disabling both counting interrupts well controlling output (A19/TOUT-pin
Timer Control Register (TCR Address 10H) TIF1 TIF0 TIE1 TIE0 TOC1 TOC0 TDE1 TDE0
TIF1: Timer Interrupt Flag (bit When TMDR1 decrements TIF1 This generate interrupt request enabled TIE1 TIF1 reset when read higher lower byte TMDR1 read. During RESET, TIF1 cleared TIF0: Timer Interrupt Flag (bit When TMDR0 decrements TIF0 This generate interrupt request enabled TIE0 TIF0 reset when read higher lower byte TMDR0 read. During RESET, TIF0 cleared TIE1: Timer Interrupt Enable (bit When TIE1 TIF1 will generate interrupt request. When TIE1 reset interrupt request inhibited. During RESET, TIE1 cleared TIE0: Timer Interrupt Enable (bit When TIE0 TIF0 will generate interrupt request. When TIE0 reset interrupt request inhibited. During RESET, TIE0 cleared
TOC1, Timer Output Control (bits 3-2) TOC1 TOC0 control output PRT1 using multiplexed A19/TOUT shown below. During RESET, TOC1 TOC0 cleared This selects address function A19/TOUT. programming TOC1 TOC0, A18/TOUT forced HIGH, toggled TMDR1 decrements
TOC1
TOC0
OUTPUT Inhibited (A19/TOUT selected address output function) toggled (A19/TOUT selected Timer output function)
TDE1, Timer Down Count Enable (bits 1-0) TDE1 TDE0 enable disable down counting TMDR1 TMDR0 respectively. When TDEn down counting stopped TMDRn freely read written TDE1 TDE0 cleared during RESET TMDRn will decrement until TDEn
Time Register Write (0004H) Reset Time Data Register FFFFH 0004H Reload Register
o<t<20
0003H0002H0001H 0000H 0003H0002H0001H0000H 0003H Write (0003H) Reload Reload
FFFFH 0003H Write Reload Register
Flag Flag
Timer Data Register Read Timer Control Register Read
Figure
Timer Operation Timing
Clocked Serial Port (CSI/O)
AB181E-20 includes simple, high-speed clock synchronous serial port. CSI/O includes transmit/receive (half duplex), fixed 8-bit data internal external data clock selection. High-speed operation (baud rate high bits/second MHz) provided. CSI/O ideal implementing multiprocessor communication link between AB181E-20 single chip controllers well additional AB181E-20 CPUs. These secondary devices typically perform portion system processing such keyboard scan/decode, interface, etc.
CSI/O Block Diagram
CSI/O consists register Transmit/Receive Data Register (TRDR) Control Register Internal Address/Data
Transmit Receive Data Register TRDR Control Register CNTR Interrupt Request Baud Rate Generator
Figure
CSI/O Block Diagram
CSI/O Register Description
Transmit/Receive Data Register (TRDR: Address OBH) TRDR used both CSI/O transmission reception, system design must ensure that constraints half-duplex operations (Transmit receive operations can't occur simultaneously). example, CSI/O transmission attempted same time CSI/O receiving data, CSI/O will work. Because TRDR buffered, attempting perform CSI/O transmit while previous transmit data still being shifted causes shift data immediately updated, thereby corrupting transmit operation progress. Similarly, reading TRDR while transmit receive progress should avoided. Control/Status Register (CNTR: Address OAH) CNTR used monitor CSI/O status, enable disable CSI/O enable disable interrupt generation select data clock speed source.
Flag (bit CSI/O indicate completion data transmit receive operation. (End Interrupt Enable) when interrupt request will generated. Program access TRDR should only occur generate interrupt request. interrupt request inhibited reset cleared. during RESET.
Receive Enable (bit CSI/O receive operation started setting When data clock enabled. internal clock mode, data clock output from pin. external clock mode, clock input pin. either case, data shifted synchronisation with (internal external) data clock. After receiving bits data, CSI/O atuomatically clears interrupt enabled will generated. should never both same time. cleared during RESET IOSTOP mode. Note: (pin multiplexed with ASCI CTS1* modem control input. order enable function, CTS1E CNTA1 should reset Transmit Enable (bit CSI/O transmit operation started setting When data block enabled. internal clock mode, data clock output from pin. external clock mode, clock input pin. both cases, data shifted synchronous with (internal external) data clock. After transmitting bits data, CSI/O automatically clears interrupt enabled will generated. should never both same time. cleared during RESET IOSTOP mode. SS2,1, Speed Select (bits 2-0) SS2, select CSI/O transmit/receive clock source speed. SS2, during RESET. After RESET, configured external clock input (SS2, SS1, Changing these values causes become output selected clock will output when transmit receive operations enabled.
CSI/O Interrupts
CSI/O interrupt request circuit shown below
Clocked SI/O Interrupt Request
Figure
CSI/O Interrupt Circuit Diagram
CSI/O Operation
CSI/O operated using status polling interrupt driven algorithms. Transmit Polling Poll CNTR unitl Write transmit data into TRDR. CNTR Repeat each transmit data byte. Transmit Interrupts Poll CNTR until Write first transmit data byte into TRDR. bits CNTR When transmit interrupt occurs, write next transmit data byte into TRDR. CNTR Repeat each transmit data byte. Receive Polling Poll CNTR until CNTR Poll CNTR until Read receive data from TRDR. Repeat each receive data byte. Receive Interrupts Poll CNTR until CNTR When receive interrupts occur read receive data from TRDR. CNTR Repeat each receive data byte.
CSI/O Operation Notes
Disable transmitter receiver before initialising changing baud rate. When changing baud rate after completion transmission reception, delay least time required before baud rate modification. When cleared software, corresponding receive transmit operation immediately terminated. Other than exceptional circumstances, should only cleared when Simultaneous transmission reception possible, should both same time.
CSI/O RESET
During RESET each CNTR initialised defined CNTR register description. CSI/O transmit receive operations progress aborted during RESET contents TRDR changed.
CSI/O Operation Timing Notes
Note that transmitter clocking receiver sampling timings different from interntal external clocking modes. shows CSI/O Transmit/Receive Timing. transmitter receiver should disabled when initialising changing baud rate.
Transmit data outputs from falling edge clock until next falling edge.
Read Write Transmit/Receive Data Register
Figure
Transmit Timing Internal Clock
Read Write Transmit/Receive Data Register
Figure
Transmit Timing External Clock
Receive data latched rising edge clock
Sampling
Read Write Transmit/ Receive Data Register
Figure
Receive Timing Internal Clock
Sampling
Read Write Transmit/Receive Data Register
Figure
Receive Timing External Clock
Arithmetic Unit
AB181E-20 contains fixed point arithmetic unit that perform multiplication accumulation. also capable evaluating expression: yn+1 Bxn-1 +Cxn-2 This type expression common control systems incorporating loop filters feedback path. values results bits wide, flag indicating overflow condition either accumulator multiplier available. Multiply-accumulate operations take clock cycles expression evaluation takes clock cycles. status flag maskable interrupt availabe signal completion current operation.
Arithmetic Registers
There 32bit arithmetic registers, these directly accessible read written through indirect mechanism. These contain signed numbers complement form.
Register Description Accumulator register Mult-Acc mode Expr Eval mode Xn-1) Xn-2) This register read, preloaded with value register cleared. Current value, loaded reset Last value, reset preloaded. Last value, reset preloaded. Coefficient Coefficient Coefficient
Xn+1 Xn+2
After each full expression evaluation Xn+1 copied into Xn+2 copied into Xn+1. This does occur after multiply-accumulate cycle.
AUCNTRL
START OVERFLOW/ CLEAR-Y Busy/ CLEAR-X INTEN SELECT WORD SELECT
START Writing this will start calculation. This will have effect unit already performing calculation this inadvisable. OVERFLOW/CLEAR-Y When read this returns logical multiplier accumulator overflow flags. either these units overflowed will returned. Writing this position will clear register.
BUSY/CLEAR-X When read this returns unit performing calculation idle. Writing this position will clear Xn+1 Xn+2 registers. Note: Setting CLEAR-Y CLEAR-X simultaneously will perform LOAD-Y Operation where contents copied into INTEN When interrupt will generated calculation, writing Prevents unit from generating interrupts. calculation interrupts enabled. Write this clear this flag. SELECT These bits determine which registers read written through AUREGLO AUREGHI ports.
REGSEL[1] REGSEL[0] Register
WORD SELECT When this low, AUREGLO AUREGHI will allow reads writes bytes selected register. When high bytes available. This also used determine type operation carried unit. Starting calculation with this will perform full expression evaluation this high multiply-accumulate only will performed.
RP_LO
This port used write A,B,C registers depending upon setting SELECT bits AUCNTRL register. When read will return value register. WORD SELECT Writes byte selected arithmetic register. Reads return value byte WORD SELECT Writes byte selected arithmetic register. Reads return value byte RP_HI
This port used write A,B,C registers depending upon setting SELECT bits AUCNTRL register. When read will return value register. WORD SELECT Writes byte selected arithmetic register. Reads return value byte WORD SELECT Writes byte selected arithmetic register. Reads return byte
Timing Information
Basic Timing
Op-code fetch Execute cycle
PC+1
code WAIT
Figure
Read Cycle Timing
wait states
Symbol Tmea Tmed Tioa Tiod Trsa Trsd Tdsu
Meaning Clock Period time high time high address valid high asserted high deasserted asserted high deasserted asserted high deasserted Data setup time Data hold time
Figure
asserted memory space read cycles, asserted space reads.
Write Cycle Timing
wait states
Symbol Tmea Tmed Tioa Tiod Twsa Twsd
Meaning Clock Period time high time high address valid high asserted high deasserted high asserted high deasserted asserted high deasserted Data valid delay time Data hold time
Figure
asserted memory space write cycles, asserted space writes.
Refresh Cycle Timing
clock
Symbol Trav Trah Trmea Trmed Trd1 Trd2
Meaning refresh address valid Refresh address hold high asserted deasserted asserted deasserted cycle refresh) high deasserted cycle refresh)
Trav Trah
A[19:0]
Refresh Address Trmed
Trmea Trd1
D[7:0]
Three clock
A[19:0]
Refresh Address
Figure
Grant Timing
Symbol Trba Traz Trcz Trdz Tsbd Tsad Tscd
Meaning high BUSACK asserted high address tristate high control tristate high data tristate BUSACK deasserted address drive control drive
BUSREQ
Trba
BUSACK
Traz
A[19:0]
Trcz
D[7:0]
Trdz
Figure
Wait State Generation
Symbol Twsu
Meaning WAIT setup time WAIT hold time
ME/IOE RD/WR
Twsu
WAIT
Clock generation
AB181E-20 provided with on-chip crystal oscillator phase locked loop (PLL) which provides frequency multiplication. external clock directly input on-chip crystal oscillator utilised. multiplies oscillator clock frequency factor maximum internal operating frequency 40MHz. external clock source crystal should used which maximum frequency 5MHz. Direct Clock Input Crystal Oscillator
EXTAL
EXTAL
XTAL
Open
XTAL
Figure
Figure
Crystal Oscillator
AB181E-20 contains oscillator circuit designed used with crystal. this circuit load capacitances required. When using crystal important ensure that noise induced traces between crystal package kept minimum. This will require siting crystal physically electrically close processor possible. Trace lengths should short power supplies (VCC) other signals routed near them. Interference with clock frequency electrical noise will cause watchdog reset processor.
Filter Network
on-chip requires filter network made three components shown Figure
ohms
Figure
important that these components close package pin, that traces short near other signals. Electrical noise cause spurious resets watchdog.
External Clock
externally generated clock applied EXTAL with XTAL left open frequency will four times frequency into this pin. Note: varying frequency this waveform will cause lose lock watchdog will reset processor.
Appendicies
OP-code Instruction
symbols instruction explained follows: Register specify 8-bit register. specify pair 16-bit registers. symbols registers correspond follows:
Note: suffixed (eg. wwH, IXL) indicate upper lower 8-bit 16-bit register respectively. specifies manipulated manipulation instruction. Bits correspond follows:
Condition specifies condition program control instructions. conditions correspond follows:
Condition zero zero carry carry parity parity even sign plus sign minus
Restart Address specifies restart address. restart addresses correspond follows:
Address
Flag flag conditions are:
affected undefined reset Parity overflow
Others
data address data address 8-bit data 16-bit data 8-bit register 16-bit register b.gr content address register 8-bit signed d'placement source addressing destination mode operation
(HI=ALL)
Appendices: OP-code Table Op-code Instruction Format
NOTE
LO=0~7
ww(LO=ALL) 0000 0000 0001 0010 0001 0100 0101 0110 (HL) 0111 1000 1001 1010 1011 1100
(HL) replaces (HL) replaces supplemented op-code instructions which have (HL) operand Table instructions executed replacing with (HL) with (IX+d). Example. (mn), (mn),
1101
1110
(LO=0~7) 0010 (HL) 0011
1111
DJNZ NOTE1)
supplemented op-code instructions which have (HL) operand Table instructions executed replacing with (HL) with (IY+d). Example (HL) (IY+d)
LD(ww),
(mn) (mn) NOTE1) NOTE1) NOTE1) NOTE2) HALT
EX(SP)
0011
RLCA
0100 0101
CALL PUSH
However, (HL) exception note followings. supplemented op-code (HL), (IX) replaces (HL) operand (IX) executed. supplemented as1st op-code (HL), (IY) replaces (HL) operand (IY) executed. Even supplemented opcode replaced instruction regarded illegal instruction.
(HL) 0110 0111
NOTE2) NOTE2) NOTE2) NOTE2) (HL)
EXDE,HL
1000 1001 1010
EXAF,AF'
(WW) (mn) (mn)
1011 1100 1101
RRCA
Table2
CALL
CALL NOTE3)
Table3 NOTE3)
(HL) 1110 1111
NOTE2)
NOTE2) NOTE2) NOTE2) NOTE2)
LO=8~F
g(LO=8~F)
Table
Op-code Instruction Format
(LO=0~7) 0000 0000 0001 0010 0011 0001 0010 0011
0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0100 0101
NOTE
NOTE
NOTE
(HL) 0110
NOTE1) NOTE1) NOTE1)
(HI=ALL)
0111
1000 1001 1010 1011 1100 1101 NOTE1) NOTE1) NOTE1) NOTE1)
NOTE
NOTE
NOTE
(HL) 1110 1111
(LO=8~F)
Note
supplemented op-code instructions which have (HL) operand Table instructions executed replacing (HL) with (IX+d). supplemented op-code instructions which have (HL) operand Table instructions executed relacing (HL) with (IY+d).
Table
Op-code Instruction Format
ww(LO=ALL) 0000 0000 0001 0010 0011 (HL) RETN 0001 0010 0011 (LO=0~7) 0100 0101 (C), (mn), TSTIO OTIM 0110 0111 1000 1001 1010 OTIMR OUTI 1011 LDIR CPIR INIR OUTIR 1100 1101 1110 1111 OTDM OTDMR OUTD LDDR CPDR INDR OTDR
OUTO (m),
0100 0101 0110 0111
OUTO (m), (C), (mn) RETI
1000 1001 1010 1011 1100 1101 1110 1111
g(LO=8~F)
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