CMOS GATE ARRAYS OVERVIEW With KZ400GH/KZ400EH CMOS Series,
|
|
|
Top Searches for this datasheet
HIGH-D ENSITY HIGH-PERFORMANCE
CMOS GATE ARRAYS
OVERVIEW
With KZ400GH/KZ400EH CMOS Series, Kawasaki offers advanced generation 0.35 micron gate arrays embedded arrays. Series provides cost-effective solutions high-speed, highly integrated, voltage applications today's networking, computer multimedia markets. Appropriate product applications include high-speed data routers/switches, graphics video encoders/decoders. satisfy these requirements, KZ400GH/KZ400EH Series uses Kawasaki LSl's 0.35 DLM, process technologies advanced cell architecture. This achieves high density, high speed power dissipation-comparable standard cell products-while maintaining quick turnaround gate arrays. KZ400GH/KZ400EH Series supports complex designs million gates system clock frequency high 200MHz. variety buffers available, including LVTTL, GTL+, HSTL, SSTL, LVDS, PCI, USB, Pseudo-ECL OSC.
KZ400GH/KZ400EH Series offers wide selection compilable memories such metal-programmable RAMs all-layer RAMs/ROMs. This helps optimize designs, because best compilable memory specific application chosen. Also, ASIC-DRAM under development graphics, image processing networking applications which require large capacity memory buffers. high-performance fast time-to-market designs, KZ400GH/KZ400EH Series offers various high-performance cores such (and peripherals), JPEG, (Content Addressable Memory), analog functions (PLL, Converter, Converter). also maximize chip-level system-level performance complex designs using Kawasaki LSl's design methodology. includes rich libraries accurately characterized cells, timing-driven synthesis, clock distribution schemes, test insertion, floor planner with interaction synthesis industry-standard tools.
FEATURES
0.35 drawn channel length (0.29 effective) Double/triple/quadruple layer metal CMOS technologies High-density high-performance cell architecture comparable standard cell solutions Gate array architecture with masterslices fastest time-to-market designs Embedded arrays offered high-speed complex designs Customized array options available high volume designs Wide selection buffers: LVTTL, GTL+, HSTL, SSTL, LVDS, PCI, USB, PECL, 3.3V 2.5V operation voltage drive: 2~24 power dissipation: 0.63 µW/MHz/gate 3.3V
Propagation delay (2NAND power gate, F.O.= Clock skew management: clock distribution methodologies types metal-programmable SRAM High-density (22K bits/mm all-layer SRAM 256K bits Testability tools such SCANTEST, IDDQ JTAG Design system with open various front-end platforms ISO9001 certified manufacturing design quality since 1994
CORE LIBRARY
KZ400GH/KZ400EH Series library offers more than robust macrocells, providing variety high-performance synthesis options. macrocells composed different sized transistors, enabling optimize design speed, power density. macrocells have input slew-rate-dependent loading offset
delay, non-linear output load-dependent delay parameters produce accurately characterized timing. This results maximum performance achievable from process technology. core library supplied many industry-standard tools HDL's, including Verilog HDL, VHDL, Synopsys, Mentor, ViewLogic others.
KZ400GH/KZ400EH CMOS SERIES
LIBRARY
I/Os KZ400GH/KZ400EH Series powered 2.5V supplies. Kawasaki also provides 5V-tolerant I/Os, which receive signals from 5V-powered device, output 2.5V. Slew-rate controlled buffers, input with pull-up, pull-down resistors open drain outputs also available. KZ400GH/ KZ400EH Series also supports high-speed low-voltage swing I/Os such LVTTL, GTL+, Pseudo-ECL (PECL), High-Speed Transceiver Logic (HSTL), Stub Series Terminated Logic (SSTL) Low-Voltage Differential Signal (LVDS). computer peripheral applications, Kawasaki support industry-standard buses with buffers buffers.
MEMORIES
Metal-Programmable Memory
KZ400GH/KZ400EH Series types compiled metal-programmable memory: High-Density (HD) Low-Power (LP) RAM. RAMs feature high performance high density 7.13K bits/mm2. RAMs suitable applications that need high-performance, high-density memories. total capacity bits block.
RAMs feature high-performance very low-power. total capacity bits. application example, RAMs suitable register files. Table shows performance specifications RAMs.
Table KZ400GH/KZ400EH Metal-Programmable Memories
HIGH-DENSITY Async. Async. Sync Sync. Async. Async. TOTAL BITS 64~36K 32~36K 64~36K 32~36K 1~16K 1~16K WORD 64~4K 32~4K 64~4K 32~4K 1~128 1~128 1~36 1~36 1~36 1~36 1~128 1~128 DENSITY ~7,125 bits/mm2 ~3,454 bits/mm2 ~6,890 bits/mm2 ~3,402 bits/mm2 ~3,369 bits/mm2 ~3,369 bits/mm2 ACCESS TIME 2.6ns* 3.1ns* 2.9ns* 3.2ns* 2.4ns** 2.4ns**
LOW-POWER
*Access time 512-word 8-bit configuration typical condition. **Access time 32-word 8-bit configuration typical condition.
All-Layer Memory
KZ400EH Series, higher density embedded memories generated all-layer memory compilers. All-layer memories feature extremely high-density, large-capacity, high-performance, while offering low-power dissipation. largest memory capacity 256K bits SRAM, ROM. density bits/mm2 single-port SRAM extremely high ASIC memory. These Kawasaki all-layer memories tuned highperformance, memory-intensive applications such image processing, Aswitches, etc. lower power required, Address Transition Detection (ATD) circuit optionally added.
ATDdetects address transition, then starts accessing memory. After certain period time, turns entire memory operation current prepare next address transition automatically. This option very effective power reduction when operating frequency less than 100MHz SRAMs, less than 50MHz ROM. Kawasaki developing ASIC-DRAM all-layer memories offered; size 256K block targeted that all-layer single-port RAM, with density about bits/mm2. 100MHz high-speed page mode operation achieved. Table shows performance specifications all-layer memories.
Table KZ400EH All-Layer Memories
SRAM Async. Sync. Sync. Sync. Sync. TOTAL 16~256K 16~256K 16~64K 64~1M 2K~256K WORD 16~16K 16~16K 16~4K 64~128K 1K~64K 1~64 1~64 1~64 1~128 1~64 DENSITY ACCESS TIME ~22,000 bits/mm 3.4ns* ~22,000 bits/mm 2.4ns* ~8,500 bits/mm2 3.8ns* ~100,000 bits/mm2 4.1ns* 35,000 bits/mm 20ns (RAS)/4ns(CAS)**
DRAM***
*The numbers 512-word 8-bit configuration typical condition. **The numbers access time/column access time under worst case conditions. ***Under development
ARRAY ARCHITECTURE
core cell cluster KZ400GH/KZ400EH Series shown Figure based CMOS-CBA® architecture licensed Synopsys, Inc. consists different unit cells: compute cell drive cell. compute cell contains four small PMOS four small NMOS that optimized building logic memory. drive cell contains large PMOS large NMOS that provide sufficient drive global nets large fanout. Statistical analysis determined that cluster three compute cells drive cell provides optimal density many design styles. conventional
gate array, other hand, size core cell uniformly large provide sufficient drive large fanout. this results gate density, most nets have small number fanouts require high drive. With CBA, smaller gate load smaller wire load significantly improves performance, power density compared conventional gate arrays. These features comparable same generation standard cell architecture. With this optimized cell architecture, KZ400GH/KZ400EH arrays achieve gate density 9,500 usable gates/mm2.
Compute Section Drive Section
Figure CMOS-CBA Array Core Architecture
Cluster
ARRAY FAMILY
Table shows base arrays KZ400GH/KZ400EH Series. Array utilization depends design, typically varies from (Double Layer Metal) technology, from (Triple Layer Metal) technology, from
(Quadruple Layer Metal). compute cell drive cell counted gate. Kawasaki offers option compile fabricate custom sized array high-volume designs.
Table KZ400GH/KZ400EH Masterslice Selection
ARRAY INDEX STANDARD COUNT PITCH) FINE GATES 61,500 87,600 126,700 156,800 190,100 266,300 309,100 355,200 404,500 462,400 501,300 577,600 640,000 685,600 774,400 1,081,600 1,440,000 2,073,600 2,624,400 3,069,500 28,100 38,200 52,600 63,100 74,400 99,000 112,300 126,100 140,600 157,100 167,900 190,600 211,200 226,200 255,500 356,000 475,200 684,200 866,000 1,012,900 USABLE GATES 42,200 55,300 57,400 76,500 78,900 105,200 94,700 126,300 111,600 148,900 148,500 198,100 168,400 224,600 189,200 252,300 210,900 281,200 235,700 314.200 251,900 335,900 288,800 381,200 320,000 422,400 342,700 452,400 387,200 511,100 540,800 713,800 720,000 950,400 1,036,800 1,368,500 1,312,200 1,732,100 1,534,700 2,025,800
Typical design both compute cell drive cell counted gate.
KZ400GH/KZ400EH CMOS SERIES
MEGAFUNCTIONS ANALOG FUNCTIONS
Kawasaki supports number megafunctions other than compiled memories KZ400GH/KZ400EH Series. These megafunctions minimize design time maximize performance complex system chips. KC80 very high-performance core that binary-compatible with Zilog Z80®. JPEG core also available imaging data compression applications. Kawasaki also offers Address Processor Core Content Addressable Memory (CAM) high-performance broadband network internetworking applications. There number analog functions under development video signal processing applications, system clock management frequency synthesis. These functions include 10-bit converters, 8-bit converters, operational amplifiers, comparators, Phase Locked Loops (PLL) Voltage Controlled Oscillators (VCO).
CLOCK DISTRIBUTION
maximum system performance, important minimize only board-level system clock skew, also chip-level clock skew die. Kawasaki provides several clocking methodologies minimize on-chip clock skew.
Clock Tree Synthesis (CTS)
Clock Tree Synthesis automatic build clock tree balancing delay with local buffers most appropriate physical location. clock tree synthesized with driving inverters buffers. Clock Tree Synthesis (CTS) efficient when number clocked instances very large clock skew requirement stringent.
Clock Buffer
This method most popular been well utilized older technologies. simple effective cases where number clocked elements less than hundred, clock skew requirement stringent. KZ400GH/KZ400EH Series, flip-flops (depending frequency) driven single stage, with special buffers clocking.
Clock Trunk with
clock trunk wide metal line which connected special clock driver. provides lower skew shorter delay than clock buffer CTS. KZ400GH/KZ400EH Series, strong clock driver built with multiple special buffers clocking, configured with clock driver, which typically uses pads.
PACKAGES
Kawasaki internal ceramic packaging capabilities, enabling accelerated prototype deliveries. Subcontractors used most cost-effective plastic packages that popular high volume designs. Kawasaki also maintains close development relationships
with vendors, ensuring that next generation industry standard Ball Grid Arrays (BGA) will offered customers whose designs exceed pins. Package offerings shown Table
Table KZ400GH/KZ400EH Package Selection
PACKAGE Skinny PQFP LQFP (1.4 thick body) PBGA TBGA
*Drop-in heat spreader vailable high power dissipation
COUNT 120* 144* 160* 208* 240* 304*
TEST METHODOLOGY
ensure high-quality device, important implement test strategy with high fault coverage. Kawasaki LSI's test methodology KZ400GH/KZ400EH Series includes following test solutions.
JTAG (IEEE 1149.1 Boundary Scan Testing)
JTAG supported inserting boundary scan circuits into system logic providing test vectors BSDL boundary scan logic. controller associated logic transparently inserted into customer's netlist.
Internal Full Scan Testing
Internal Full Scan Testing most powerful test methodologies automatic development test vectors, achieving more than stuck-at fault coverage large synchronous designs. Synopsys Test Compiler, which automatically performs testability rule checking, scan chain insertion ATPG (Automatic Test Pattern Generation).
Process Monitoring
Process monitoring performed adding measurement circuit into device measuring delay. This measurement verifies that device operate required frequency.
IDDQ Testing
IDDQ Testing effective methodology which detects various types silicon defects without area performance overhead. This methodology supported measuring device's quiescent power-supply current functional vectors selected CM-iTest® from CrossCheck, part Duet Technologies, Inc. This test provides easy improve fault coverage ad-hoc test strategy.
Fault Simulation
Fault simulation supported using Cadence Verifault-XL simulator, which allows rapidly obtain fault coverage information applied test vectors.
KZ400GH/KZ400EH CMOS SERIES
DESIGN SYSTEM
Kawasaki LSI's integrated top-down design flow shown Fig. allows start either with VHDL Verilog-HDL, from gate-level, choose from wide assortment schematic capture programs. Kawasaki supports popular tools, from companies such Synopsys, Cadence, Mentor Graphics ViewLogic. Kawasaki LSI's Design Rule Checker Delay Calculator read EDIF netlists. Thus have choice either VSS, Verilog, QuickSim ViewSim, V-System IKOS Voyager, read delay files generated Delay Calculator gate-level simulation. accurate delay calculation method provided, accounting only output-load-dependent delay, also input-slew-rate-dependent offset delay, input-slew-rate-dependent loading delay interconnect delay caused wire resistance. This advanced calculation methodology, coupled with control physical layout, results implementation highest performance most accurate designs. interfaces these tools industry-standard formats such Verilog-HDL, VHDL, EDIF, SDF, PDEF WGL, making very easy designers migrate their designs Kawasaki LSI's technologies. design sign-off golden simulator Verilog.
Figure Kawasaki LSI's Design Flow
Verilog HDL,VHDL Vector
Functional Simulation Memory Megafunction JTAG
Logic Synthesis Test Synthesis
Schematic Capture
Timing Analysis
EDIF
Test Vector Fault Simulation
Design Rule Checker
Delay Calculator
Gate-Level Simulation
Floorplanner
Placement Clock Tree Synthesis
Test Program
Routing
Tester Verification
Fabrication
ELECTRICAL CHARACTERISTICS
Tables through show electrical characteristics KZ400GH/KZ400EH Series.
Table Recommended Operating Conditions
PARAMETER Power Supply Voltage Ambient Temperature SYMBOL RATING 3.0~3.6 2.3~2.7 -40~+85 UNITS
Table Absolute Maximum Ratings
PARAMETER Power Supply Voltage Input Voltage Output Current Storage Temperature SYMBOL IOUT TSTG RATING UNITS -0.3~+3.6 -0.3~VDD+0.3 0.3~+6.3 -55~+125
Table Characteristics
SYMBOL PARAMETER High-Input Voltage CONDITIONS LVTTL 5V-tolerant LVTTL 3.3V LVTTL 5V-tolerant LVTTL 3.3V LVTTL-Schmitt LVTTL-Schmitt LVTTL-Schmitt VIN=VDD VIN=VSS loh=-2~-24mA lol=2~24mA Voh=VSS Vol=VDD VIN=VSS VIN=VDD MIN. LIMITS TYP. UNITS MAX. -160 450*
ldds
Low-Input Voltage High-Input Voltage Low-Input Voltage Hysteresis Voltage High-Input Current Low-Input Current High-Output Voltage Low-Output Voltage 3-State Lead Current Active Pull-Up Current Active Pull-Down Current Static Stand-By Current
*The number design-dependent. ESDProtection:=2000V using STD-883D 3015.6 EIAJ:ED4701 C-111 standards Lock-up immunity:300mA injection current (room temp) using JEDEC standard
Silicon Valley Office Kawasaki U.S.A., Inc. 4655 Ironsides Drive, Suite Santa Clara, 95054 Tel: (408) 654-0180 Fax: (408) 654-0198
Eastern Area Office Kawasaki U.S.A., Inc. Edgewater Drive, Suite Wakefield, 01880 Tel: (617) 224-4201 Fax: (617) 224-2503
Kawasaki logoregistered Kawasaki Inc. brand, names,company registered their companies. themake anyproductsservices anywithout Kawasaki LSI'sdesign trademark product names USA,other trademarks trademarksrespective Kawasaki right changes reserves herein notice. assume time does responsibility arising liability outapplicationofproduct described leaseof from license rights, orany service herein;doespurchase, service Kawasakiconvey underpatent copyrights, rights,otherintellectual rights parties. Kawasaki reserved. U.S.A. product trademark property Kawasakiof 1997 LSI.rights Printed 1/97. third
Other recent searches
TEA2114 - TEA2114 TEA2114 Datasheet
STX826 - STX826 STX826 Datasheet
REJ03D0350 - REJ03D0350 REJ03D0350 Datasheet
0300Z - 0300Z 0300Z Datasheet
ICS8422004I-01 - ICS8422004I-01 ICS8422004I-01 Datasheet
ADS62P25 - ADS62P25 ADS62P25 Datasheet
ADS62P24 - ADS62P24 ADS62P24 Datasheet
ADS62P23 - ADS62P23 ADS62P23 Datasheet
ADS62P22 - ADS62P22 ADS62P22 Datasheet
ADG1636 - ADG1636 ADG1636 Datasheet
856665 - 856665 856665 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
