Kbit (32Kb Parallel EEPROM with Software Data Protection FAST ACC
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M28256
Kbit (32Kb Parallel EEPROM with Software Data Protection
FAST ACCESS TIME: 90ns 120ns SINGLE SUPPLY VOLTAGE: M28256 2.7V 3.6V M28256-xxW POWER CONSUMPTION FAST WRITE CYCLE: Bytes Page Write Operation Byte Page Write Cycle ENHANCED WRITE DETECTION: Data Polling Toggle STATUS REGISTER HIGH RELIABILITY DOUBLE POLYSILICON, CMOS TECHNOLOGY: Endurance >100,000 Erase/Write Cycles Data Retention Years JEDEC APPROVED BYTEWIDE ADDRESS DATA LATCHED ON-CHIP SOFTWARE DATA PROTECTION
PDIP28 (BS)
PLCC32 (KA)
SO28 (MS) mils
TSOP28 (NS) x13.4mm
Figure Logic Diagram
DESCRIPTION M28256 M28256-Ware power Parallel EEPROM fabricatedwith STMicroelectronics proprietary double polysilicon CMOS technology. Table Signal Names
A0-A14 DQ0-DQ7 Address Input Data Input Output Write Enable Chip Enable Output Enable Supply Voltage Ground
A0-A14
DQ0-DQ7
M28256
AI01885
January 1999
This preliminary information product developmentor undergoing evaluation Detail subject change without notice.
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M28256
Figure Connections Figure Connections
AI01886 AI01887
Warning: Connected, Don't Use.
Figure Connections
Figure TSOP Connections
M28256
AI01888
M28256
AI01889
M28256
M28256
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M28256
Table Absolute Maximum Ratings
Symbol VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model)
Value +0.6 4000
Unit
Notes: Except rating "Operating Temperature Range", stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents. Depends range. 100pF through 1500; MIL-STD-883C, 3015.7
Figure Block Diagram
RESET
CONTROL LOGIC
DECODE
A6-A14 (Page Address)
ADDRESS LATCH
256K ARRAY
A0-A5
ADDRESS LATCH
DECODE
SENSE DATA LATCH
BUFFERS
PAGE LOAD TIMER STATUS TOGGLE DATA POLLING
AI01697
DQ0-DQ7
3/21
M28256
Table Operating Modes
Mode Read Write Standby Write Inhibit Write Inhibit Write Inhibit Output Disable
Notes: VIL.
Data Data Hi-Z Data Hi-Z Data Hi-Z Hi-Z
DESCRIPTION (Cont'd) devices offer fast access time with power dissipation requires power supply. circuit been designed offer flexible microcontroller interface featuring both hardware software handshaking with Data Polling Toggle access status register. devices support byte page write operation. Software Data Protection (SDP) also possible using standard JEDEC algorithm. DESCRIPTION Addresses (A0-A14). address inputs select 8-bit memory location during read write operation. Chip Enable (E). chip enable input must enable read/write operations.When Chip Enable high, power consumption reduced. Output Enable (G). Output Enable input controls data output buffers used initiate read operations. Data (DQ0- DQ7). Data written read from memory through pins. Write Enable (W). Write Enable input controls writing data memory. OPERATIONS Write Protection order prevent data corruption inadvertent write operations; internal comparatorinhibits Write operations below (see Table andTable 9).Access memoryin write mode allowed after power-up specified Table Table
Read device accessed like static RAM. When with high, data addressed presented pins. pins high impedance when either high. Write Write operations initiated when both high.The device supports both controlled write cycles. Address latched falling edge which ever occurs last Data rising edge which ever occurs first. Once initiated write operation internally timed until completion status Data Polling Toggle functions controlled accordingly. Page Write Page write allows bytes within same page consecutively latched into memory prior initiating programming cycle. bytes must located single page address, that A14-A6 must same bytes; not, Page Write instruction executed. page write initiated byte write operation. page write composed successive Write instructions which have sequenced with specific period time between consecutive Write instructions, period time which smaller than tWHWH value (see Table Table 13). this period time exceeds tWHWH value, internal programmingcycle will start. Once initiated write operation internally timed until completion status Data Polling Toggle functions controlled accordingly.
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M28256
Status Register devices provide several Write operation status flags that used minimize application write time. These signals available port bits during programming cycle only. Data Polling (DQ7). During internal write cycle, attempt read last byte written will produce complementary value previously latched bit. Once write cycle finished true logic value appears read cycle. Toggle (DQ6). devices offer another determining when internal write cycle completed. During internal Erase/Write cycle, will toggle from (the first read value "0") subsequent attempts read byte memory. When internal cycle completed toggling will stop data read DQ7-DQ0 addressed memory byte. device accessible Read Write operation. Page Load TimerStatus bit(DQ5). Duringa Page Write instruction, devices expect receive stream data with minimum period time between each data byte. This period time (tWHWH) defined on-chip Page Load timer which running/overflow status available DQ5. indicates that timer running, High indicates time-out after which internal write cycle will start. Figure Status Assignment
PLTS
Data Polling Toggle PLTS Page Load Timer Status
Software Data Protection devices offer software controlled write protection facility that allows user inhibit write modes device. This useful protecting memory from inadvertent write cycles that occur uncontrolledbus conditions. devices shipped standardin "unprotected" state meaning that memory contents changed required user. After Software Data Protection enable algorithm issued, device enters "Protect Mode" operation where further write commands have effect memory contents. devices remain this mode until valid Software Data Protection (SDP) disable sequence received whereby device reverts "unprotected" state. Software Data Protection fully non-volatile changed power on/off sequences. enable Software Data Protection (SDP) device requires user write (with Page Write addressing three specific data bytes three specific memorylocations,each location different page) Figure Similarly disable Software Data Protection user write specific data bytes into different locations Figure (with Page Write adressing different bytes different pages). This complexseries ensures that userwill never enable disable Software Data Protection accidentally. write into devices when set, sequence shown Figure must used. This sequence provides unlock enable write action, same time continues set. extension this where required set, data written. Using same sequence above, data written same time, giving both these actions same Write cycle (tWC).
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M28256
Figure Software Data Protection Enable Algorithm Memory Write
WRITE Address 5555h Page Write Instruction
WRITE Address 5555h
WRITE Address 2AAAh Page Write Instruction
WRITE Address 2AAAh
WRITE Address 5555h
WRITE Address 5555h WRITE enabled WRITE Data Written Address
ENABLE ALGORITHM
Write Memory
Write Data after
AI01698B
Figure Software Data Protection Disable Algorithm
WRITE Address 5555h
WRITE Address 2AAAh
Page Write Instruction
WRITE Address 5555h
WRITE Address 5555h
WRITE Address 2AAAh
WRITE Address 5555h
Unprotected State after (Write Cycle time)
AI01699B
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M28256
Table Measurement Conditions
Input Rise Fall Times Input Pulse Voltages (M28256) Input Pulse Voltages (M28256-W) Input Output Timing Ref. Voltages (M28256) Input Output Timing Ref. Voltages (M28256-W) 20ns 0.4V 2.4V -0.3V 0.8V 2.0V
Figure Testing Input Output Waveforms
4.5V 5.5V Operating Voltage 2.4V 2.0V 0.8V
Figure Testing Equivalent Load Circuit
0.4V
DEVICE UNDER TEST 100pF
2.7V 3.6V Operating Voltage 0.3V
AI02101B
includes capacitance
AI02102B
Table Capacitance
Symbol Parameter Input Capacitance Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested.
Table Read Mode Characteristics M28256 70°C 85°C; 4.5V 5.5V)
Symbol
Parameter Input Leakage Current Output Leakage Current Supply Current (TTL inputs) Supply Current (CMOS inputs)
Test Condition VIL, VIL, -0.3V
Unit
ICC1 ICC2
Supply Current (Standby) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage
-400
Note: I/O's open circuit.
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M28256
Table Power Timing M28256 70°C 85°C; 4.5V 5.5V)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Unit
Note: Sampled only, 100% tested.
Table Read Mode Characteristics M28256-W 70°C 85°C; 2.7V 3.6V)
Symbol ICC2
Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage
Test Condition VIL, VIL, MHz, 3.3V VIL, VIL, MHz, 3.6V
Unit
-0.3V -400
Note: I/O's open circuit.
Table Power Timing M28256-W 70°C 85°C; 2.7V 3.6V)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Unit
Note: Sampled only, 100% tested.
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M28256
Table Read Mode Characteristics 70°C 85°C; 4.5V 5.5V)
M28256 Symbol Parameter Test Condition tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tACC Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition VIL, VIL, Unit
Note: Output Hi-Z defined point which data longer driven.
Table Read Mode Characteristics 70°C 85°C; 2.7V 3.6V)
M28256-W Symbol Parameter Test Condition tAVQV tELQV tGLQV tEHQZ
Unit
tACC
Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
VIL, VIL,
tGHQZ tAXQX
Note: Output Hi-Z defined point which data longer driven.
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M28256
Table Write Mode Characteristics 70°C 85°C; 4.5V 5.5V)
Symbol Parameter Test Condition M28256 tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWHWH tWHRH tEL, tDVWH tDVEH tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Input Filter Pulse Width Data Valid before Write Enable High Data Valid before Chip Enable High Note VIL, VIH, 0.15 VIL, VIH, Unit
Note: Characterized only tested production.
10/21
M28256
Table Write Mode Characteristics 70°C 85°C; 2.7V 3.6V)
Symbol Parameter Test Condition M28256-W tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWHWH tWHRH tEL, tDVWH tDVEH tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Input Filter Pulse Width Data Valid before Write Enable High Data Valid before Chip Enable High Note VIL, VIH, VIL, VIH, Unit
Note: Characterized only tested production.
11/21
M28256
Figure Read Mode Waveforms
A0-A14 tAVQV tGLQV tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA Hi-Z
AI01700
Note: Write Enable High.
Figure Write Mode Waveforms Write Enable Controlled
A0-A14 tAVWL tELWL tGHWL
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWLDV DQ0-DQ7 DATA tDVWH
tWHWL
tWHDX
AI01701
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M28256
Figure Write Mode Waveforms Chip Enable Controlled
A0-A14 tAVEL tGHEL tWLEL
VALID tELAX
tELEH
tEHGL
tELDV DQ0-DQ7 DATA tDVEH tEHDX
tEHWH
AI01702
Figure Page Write Mode Waveforms Write Enable Controlled
A0-A14
Addr
Addr
Addr
Addr
tWHWL tWLWH DQ0-DQ7 Byte Byte tWHWH Byte tWHWH Byte tWHRH
Byte
AI01703B
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M28256
Figure Software Protected Write Cycle Waveforms
tWLWH tAVEL A0-A5 tWHDX A6-A14 5555h tDVWH DQ0-DQ7 Byte Byte Byte
AI01704
tWHWL
tWHWH
tWLAX Byte Address
2AAAh
5555h
Page Address
Note: through must specify same page address during each high transition after software code been entered. must high only when both low.
Figure Data Polling Waveform Sequence
A0-A14
Address last byte Page Write instruction
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI01705
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M28256
Figure Toggle Waveform Sequence
A0-A14
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI01706
Note: First Toggle forced '0'.
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M28256
ORDERING INFORMATION SCHEME
Example:
M28256
Speed
Operating Voltage blank 4.5V 5.5V 2.7V 3.6V
Package PDIP28 PLCC32 SO28 mils TSOP28 13.4mm
Temperature Range
Option Tape Reel Packing
90ns 120ns 150ns 200ns 250ns
Notes: available operating voltage. Available operating voltage only. Temperature Range request only.
Devices shipped from factory with memory content "1's" (FFh). list available options (Speed, Package, etc.) further informationon aspect this device, please contact STMicroelectronics Sales Office nearest you.
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M28256
PDIP28 Plastic DIP, mils width
Symb 2.54 14.99 33.02 15.24 1.52 0.38 3.56 0.38 0.20 36.83 13.59 15.24 3.18 1.78 5.08 4.06 0.51 0.30 37.34 13.84 17.78 3.43 2.08 0.100 0.590 1.300 0.600 0.060 inches 0.015 0.140 0.015 0.008 1.450 0.535 0.600 0.125 0.070 0.200 0.160 0.020 0.012 1.470 0.545 0.700 0.135 0.082
PDIP
Drawing scale.
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M28256
PLCC32 lead Plastic Leaded Chip Carrier, rectangular
Symb 0.89 1.27 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 0.00 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 0.25 0.035 0.050 inches 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 0.000 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 0.010
0.51 (.020)
D2/E2
1.14 (.045)
PLCC
Drawing scale.
18/21
M28256
SO28 lead Plastic Small Outline, mils body width
Symb 1.27 2.46 0.13 0.35 0.23 17.81 7.42 10.16 0.61 0.10 2.64 0.29 0.48 0.32 18.06 7.59 10.41 1.02 0.050 inches 0.097 0.005 0.014 0.009 0.701 0.292 0.400 0.024 0.004 0.104 0.011 0.019 0.013 0.711 0.299 0.410 0.040
SO-b
Drawing scale.
19/21
M28256
TSOP28 lead Plastic Thin Small Outline, 13.4mm
Symb 0.55 0.95 0.17 0.10 13.20 11.70 7.90 0.50 0.10 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 0.70 0.022 0.037 0.007 0.004 0.520 0.461 0.311 0.020 0.004 inches 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 0.028
TSOP-c
Drawing scale.
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M28256
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Spec ifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics 1999 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. http://www.st.com
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