Frequency Timing Generator PENTIUM Systems Recommended Applicatio
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ICS9248-97
Frequency Timing Generator PENTIUM Systems
Recommended Application: Camino chipset Output Features: CPUs 2.5V, 180MHz. IOAPIC 2.5V, PCI/2 3V66MHz 3.3V. PCIs 3.3V 48MHz, 3.3V fixed 24/48MHz, 3.3V CPU/2, 2.5V. Features: 180MHz frequency support Support power management: Power down Mode from programming. Spread spectrum control 0.25% center spread). Uses external 14.318MHz crystal pins frequency select
Configuration
GNDREF REF0 *SEL24_48#/REF1 VDDREF GNDPCI *FS0/PCICLK_F *FS1/PCICLK0 VDDPCI *FS2/PCICLK1 *FS3/PCICLK2 GNDPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 GNDPCI PCICLK7 PCICLK8 PCICLK9 VDDPCI VDDLAPIC IOAPIC0 IOAPIC1 GNDLAPIC IOAPIC2 VDDLCPU/2 CPU/2 GNDLCPU/2 CPUCLK0 VDDLCPU CPUCLK1 CPUCLK2 GNDLCPU VDD66 3V66_0 3V66_1 3V66_2 GND66 SDATA SCLK VDD48 48MHz/FS4* 24_48MHz GND48
48-pin SSOP
*120K pull-up indicated inputs.
Specifications: Output Jitter: <250ps CPU/2 Output Jitter. <250ps IOAPIC Output Jitter: <500ps 48MHz, 3V66, Output Jitter: <500ps Output Jitter. <1000ps Output Skew: <175ps IOAPIC Output Skew <250ps 3V66 Output Skew <250ps 3V66 Output Offset: 1.5ns (CPU leads) 3V66 Output Offset: 4.0ns (3V66 leads) IOAPIC Output Offset 4.0ns (CPU leads)
SEL24_48# SDATA SCLK (4:0) Control Logic Config. Reg.
3V66 DIVDER IOAPIC DIVDER
Block Diagram
PLL2 XTAL PLL1 Spread Spectrum 48MHz 24_48MHz
ICS9248-97
(1:0)
DIVDER
CPUCLK (2:0) CPU/2 IOAPIC (2:0)
DIVDER
PCICLK (9:0) PCICLK_F 3V66 (2:0)
9248-97 08/18/00
reserves right make changes device data identified this publication without further notice. advises customers obtain latest version device data verify that information being relied upon customer current accurate.
ICS9248-97
General Description
ICS9248-97 main clock synthesizer chip Pentium based systems using Rambus Interface DRAMs. This chip provides clocks required such system when used with Direct Rambus Clock Generator(DRCG) chip such ICS9212-01. Spread Spectrum enabled driving SPREAD# active. Spread spectrum typically reduces system 10dB. This simplifies qualification without resorting board design iterations costly shielding. ICS9248-97 employs proprietary closed loop design, which tightly controls percentage spreading over process temperature variations. CPU/2 clocks inputs DRCG.
Descriptions
number name REF0 REF1 SEL24_48 PCICLK_F PCICLK0 PCICLK1 PCICLK2 Type OUT/IN Description Ground pins 14.318MHz reference clock outputs 3.3V 14.318MHz reference clock outputs 3.3V Logic input select 48MHz output Power pins 3.3V XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output Free running clock 3.3V. Synchronous clocks. affected PCI_STOP# input. Logic input frequency selection clock output 3.3V. Synchronous clocks. Logic input frequency selection clock output 3.3V. Synchronous clocks. Logic input frequency selection clock output 3.3V. Synchronous clocks. Logic input frequency selection clock outputs 3.3V. Synchronous clocks. This asynchronous input powers down chip when drive active(Low). internal PLLs disabled output clocks held state. 48MHz output selectable SEL24_48# (0=48MHz 1=24MHz) Fixed 48MHz clock output. 3.3V Logic input frequency selection Clock input input Data input serial input. 3.3V clock outputs. These outputs stopped when CPU_STOP# driven active. Ground CPUCLKs Host clock output 2.5V. Power CPUCLKs. 2.5V Ground CPU/2 clocks. 2.5V clock outputs frequency. Power CPU/2 clocks. 2.5V Ground IOAPIC outputs. IOAPIC clocks 2.5V. Synchronous with CPUCLKs. Power IOAPIC outputs. 2.5V.
PCICLK (9:3) 24_48MHz 48MHz SCLK SDATA 3V66 (2:0) GNDLCPU CPUCLK (2:0) VDDLCPU GNDLCPU/2 CPU/2 VDDLCPU/2 GNDLAPIC IOAPIC (2:0) VDDLAPIC
ICS9248-97
Functionality
103.0 105.0 100.3 100.9 107.0 109.0 112.0 114.0 116.1 118.0 133.3 120.0 122.0 125.1 128.2 130.0 133.9 159.1 CPU/2 51.50 52.50 50.15 50.45 53.50 54.50 56.00 57.00 58.50 59.00 66.65 60.00 61.00 62.55 64.10 65.00 66.5 66.95 76.5 79.55 82.5 85.5 88.5 34.33 35.00 33.43 33.63 35.67 36.33 37.33 38.00 38.70 39.33 33.33 40.00 40.67 41.70 42.73 43.33 44.33 33.48 34.5 35.5 36.5 37.5 38.25 39.78 40.5 41.25 42.75 43.5 44.25 68.67 70.00 66.87 67.27 71.33 72.67 74.67 76.00 77.40 78.67 66.65 80.00 81.33 83.40 85.47 86.67 88.67 66.95 76.5 79.55 82.5 85.5 88.5 IOAPIC 17.17 17.50 16.72 16.82 17.83 18.17 18.67 19.00 19.35 19.67 16.66 20.00 20.33 20.85 21.37 21.67 22.17 16.74 17.25 17.75 18.25 18.75 19.13 19.5 19.89 20.25 20.63 21.38 21.75 22.13 22.5
ICS9248-97
Serial Configuration Command Bitmap
Byte Functionality frequency select register (Default
Description 103.0 105.0 100.45 100.9 107.1 109.0 112.0 114.0 116.1 118.0 133.3 120.0 122.0 125.1 128.21 130.0 133.0 133.9 138.0 142.0 146.0 150.0 153.0 156.0 159.1 162.0 165.0 168.0 171.0 174.0 177.0 180.0 CPU/2 51.50 52.50 50.23 50.45 53.55 54.50 56.00 57.00 58.50 59.00 66.65 60.00 61.00 62.55 64.11 65.00 66.50 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.55 81.00 82.50 84.00 85.50 87.00 88.50 90.00 34.33 35.00 33.48 33.63 35.70 36.33 37.33 38.00 38.70 39.33 33.33 40.00 40.67 41.70 42.74 43.33 44.33 33.48 34.50 35.50 36.50 37.50 38.25 39.00 39.78 40.50 41.25 42.00 42.75 43.50 44.25 45.00 3V66 68.67 70.00 66.97 67.27 71.40 72.67 74.67 76.00 77.40 78.67 66.65 80.00 81.33 83.40 85.47 86.67 88.67 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.55 81.00 82.50 84.00 85.50 87.00 88.50 90.00 IOAPIC 17.17 17.50 16.74 16.82 17.85 18.17 18.67 19.00 19.35 19.67 16.66 20.00 20.33 20.85 21.37 21.67 22.17 16.74 17.25 17.75 18.25 18.75 19.13 19.50 19.89 20.25 20.63 21.00 21.38 21.75 22.13 22.50
7:4)
Reserved Note
Frequency selected hardware select, latched inputs Frequency selected Normal Spread spectrum enabled Running Tristate outputs
Note Default power-up will latched logic inputs define frequency.
ICS9248-97
Byte CPU, Active/Inactive Register enable, disable)
Description CPUCLK CPUCLK CPUCLK CPU/2 IOAPIC0 IOAPIC1 IOAPIC2 (Reserved)
Byte Active/Inactive Register enable, disable)
Description
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCICLK_F
Notes: Inactive means outputs held disabled from switching.
Notes: Inactive means outputs held disabled from switching.
Byte 3V66 Active/Inactive Register enable, disable)
Description 3V66_0 3V66_1 3V66_2 FS1# REF1 REF0 FS3# FS2#
Byte Active/Inactive Register enable, disable)
Description 24_48MHz 48MHz FS0# (Reserved) PCICLK9 PCICLK8 PCICLK7 FS4#
Notes: Inactive means outputs held disabled from switching. Byte Active/Inactive Register enable, disable)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Description
Notes: Inactive means outputs held disabled from switching. Byte6: Active/Inactive Register enable, disable)
Description
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note)
Notes: Inactive means outputs held disabled from switching.
Note: Dont write into this register, writing into this register cause malfunction
ICS9248-97
Absolute Maximum Ratings
Supply Voltage Logic Inputs Ambient Operating Temperature Storage Temperature Case Temperature +0.5 +70°C 65°C +150°C 115°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation device these other conditions above those listed operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Electrical Characteristics Input/Supply/Common Output Parameters
+/-5%; VDDL +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage Input Voltage Input High Current Input Current IIL1 Inputs with pull-up resistors Input Current IIL2 Inputs with pull-up resistors Operating IDD3.3OP100 Select Supply Current IDD3.3OP133 Select Input frequency Input Capacitance Logic Inputs pins CINX Transition Time Ttrans crossing target Freq. Settling Time1 From crossing target Freq. Stabilization1 TSTAB From target Freq.
VSS-0.3 -200
UNITS VDD+0.3 -100 14.318
Guaranteed design, 100% tested production.
Electrical Characteristics Input/Supply/Common Output Parameters
+/-5%; VDDL +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Operating IDD2.5OP100 Select Supply Current IDD2.5OP133 Select PWRDWN# Power Down IDD2.5PD Supply Current
14.5 17.5
UNITS
Guaranteed design, 100% tested production.
ICS9248-97
Group Offset
Group 3V66 3V66 IOAPIC Offset 0.0-1.5ns leads 1.5-4.0ns 3V66 leads 1.5-4.0ns leads Measurement Loads 20pF, 3V66 30pF 3V66 30pF, 30pF 20pF, IOAPIC 20pF Measure Points @1.25V, 3V66 1.5V 3V66 1.5V, 1.5V @1.25V, IOAPIC 1.5V
Note: offsets measured rising edges.
Electrical Characteristics CPUCLK
+/-5%, VDDL +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS UNITS
Output Impedance Output Impedance Output High Voltage Output Voltage Output High Current Output Current Rise Time Fall Time
Duty Cycle Skew Jitter, Cycle-to-cycle
RDSP2B
VDD*(0.5) VDD*(0.5) -12.0 12.0 1.25 Frequencies: 159MHz 1.25 Frequencies: 180MHz 1.25 1.25
13.5 13.5
2.24 0.31 1.47 1.51 50.5 47.5
RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1
dt2B1 tsk2B1
tjcyc-cyc2B1
Guaranteed design, 100% tested production.
Electrical Characteristics CPU/2
+/-5%, VDDL +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Voltage Output High Current Output Current Rise Time Fall Time Duty Cycle Jitter, Cycle-to-cycle
0.31 1.21 1.17 48.6
UNITS
RDSP2B
VDD*(0.5) VDD*(0.5) -12.0 12.0 1.25 1.25
13.5 13.5
RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tjcyc-cyc2B1
Guaranteed design, 100% tested production.
ICS9248-97
Electrical Characteristics 3V66
+/-5%, VDDL +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Voltage Output High Current Output Current Rise Time1 Fall Time1 Duty Cycle1 Skew1 Jitter, Cycle-to-cycle1
24.19 23.08 0.17 1.49 1.52
UNITS
RDSP1
VDD*(0.5) VDD*(0.5)
RDSN1 VOH1 VOL1 IOH1 IOL1
tsk1 Tjcyc-cyc1
Guaranteed design, 100% tested production.
Electrical Characteristics PCICLK
+/-5%, VDDL +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Voltage Output High Current Output Current Rise Time Fall Time Skew
0.16 1.87 1.57
UNITS
RDSP1
VDD*(0.5) VDD*(0.5) PCICLK(5:All) PCICLK(5: PCICLK(7:
RDSN1 VOH1 VOL1 IOH1 IOL1 tsk1
Duty Cycle
49.8
Jitter, Cycle-to-cycle1
Tjcyc-cyc1
Guaranteed design, 100% tested production.
ICS9248-97
Electrical Characteristics
+/-5%; +/-5%; (unles otherwis tated) ETER Output Impedance Output Impedance Output High Voltage Output Voltage Output High Current Output Current Time Fall Time
CONDITIONS *(0.5) *(0.5)
2.62 2.33 2.42
UNITS
Duty Cycle
Jitter, Cycle-to-cycle
c-cy
Guaranteed ign, 100% production.
Electrical Characteristics
+/-5%, VDDL +/-5%; (unless otherwise stated) METER Output Impedance Output Impedance Output High Voltage Output Voltage Output High Current Output Current Time Fall Time
CONDITIONS *(0.5) *(0.5)
47.6 2.28 2.24
UNITS 1000
Duty Cycle
Jitter, Cycle-to-cycle
c-cy
51.9
Guaranteed ign, 100% production.
ICS9248-97
Electrical Characteristics IOAPIC
+/-5%, VDDL +/-5%; (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Voltage Output High Current Output Current Rise Time Fall Time
2.24 0.31 1.62 1.57
UNITS
RDSP4B
VDD*(0.5) VDD*(0.5) -12.0 12.0 1.25 1.25 1.25
13.5 13.5
RDSN4B VOH4B VOL4B IOH4B IOL4B Tr4B Tf4B Dt4B tsk4B
Duty Cycle Skew Jitter, Cycle-to-cycle1
Tjcyc-cyc4B
48.6
Guaranteed design, 100% tested production.
ICS9248-97
Power Management Features:
CPUCLK CPU/2 IOAPIC 3V66 PCI_F REF. 48MHz VCOs
Note: means outputs held static latency requirement next page. means active. pulled Low, impacts outputs including outputs.
Power Management Requirements:
Latency Signal Signal State (normal operation) (power down) rising edges PCICLK 2max.
Note: Clock on/off latency defined number rising edges free running PCICLKs between clock disable goes low/ high first valid clock comes device. Power latency when PWR_DWN# goes inactive (high when first valid clocks dirven from device.
ICS9248-97
General serial interface information
information this section assumes familiarity with programming. more information, contact programming application note.
Write:
Controller (host) sends start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends dummy command code clock will acknowledge Controller (host) sends dummy byte count clock will acknowledge Controller (host) starts sending first byte (Byte through byte clock will acknowledge each byte time. Controller (host) sends Stop
Read:
Controller (host) will send start bit. Controller (host) sends read address clock will acknowledge clock will send byte count Controller (host) acknowledges clock sends first byte (Byte through byte Controller (host) will need acknowledge each byte Controller (host) will send stop
Write:
Controller (Host) Start Address D2(H) Dummy Command Code Dummy Byte Count Byte Byte Byte Byte Byte Byte Stop
Stop Byte Byte Byte Byte Byte Byte
(Slave/Receiver)
Read:
Controller (Host) Start Address D3(H) (Slave/Receiver)
Byte Count
Notes:
clock generator slave/receiver, component. read back data stored latches verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. data transfer rate supported this clock generator 100K bits/sec less (standard mode) input operating 3.3V logic levels. data byte format bytes. simplify clock generator interface, protocol only "Block-Writes" from controller. bytes must accessed sequential order from lowest highest byte with ability stop after complete byte been transferred. Command code Byte count shown above must sent, data ignored those bytes. data loaded until Stop sequence issued. power-on, registers default condition, shown.
ICS9248-97
Timing Diagram
power down selection used part into very power state without turning power part. asynchronous active input. This signal needs synchronized internal device prior powering down clock synthesizer. Internal clocks running after device power down. When active clocks need driven value held prior turning VCOs crystal. power latency needs less than power down latency should short possible conforming sequence requirements shown below. 48MHz clocks expected stopped state soon possible. state internal logic, stopping holding clock outputs state require more than clock cycle complete.
Notes: timing referenced Internal CPUCLK (defined inside ICS9248 device). shown, outputs Stop next falling edge after goes low. asynchronous input metastable conditions exist. This signal synchronized inside this part. shaded sections Crystal signals indicate active clock. Diagrams shown with respect 133MHz. Similar operation when 100MHz.
ICS9248-97
MBOL
Millimeters COMMON DIMENSIONS 2.413 0.203 0.203 2.794 0.406 0.343
Inches COMMON DIMENSIONS .095 .008 .008 .110 .016 .0135
TIONS
0.127 0.254 TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 TIONS .395 .291 .015 .420 .299 .025
0.635 0.508 1.016 TIONS
0.025 .020 .040 TIONS
9.398 11.303 15.748 18.288 20.828 9.652 11.557 16.002 18.542 21.082 .370 .445 .620 .720 .820
(inch) .380 .455 .630 .730 .830
6/1/00
DOC# 0034
Ordering Information
ICS9248yF-97-T
Example:
XXXX
Designation tape reel packaging Pattern Number digit number parts with code patterns) Package Type F=SSOP
Revision Designator (will correlate with datasheet revision)
Device Type (consists digit numbers) Prefix ICS, Standard Device
reserves right make changes device data identified this publication without further notice. advises customers obtain latest version device data verify that information being relied upon customer current accurate.
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