Interface Considerations Document Number: X16-AN-003-06 Copy
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S5U13502 Matrix Graphics Controller
Interface Considerations
Document Number: X16-AN-003-06
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S1D13502 X16-AN-003-06
Interface Considerations Issue Date: 01/01/29
Epson Research Development Vancouver Design Center
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Table Contents
INTRODUCTION
Reference Material
16-BIT INTERFACE
Equations Additional Discrete Logic Description S1D13502 Default Setup 1.4.1 Configuration Options 1.4.2 Register Setting
8-BIT INTERFACE
S1D13502 Default Setup 1.5.1 Configuration Options 1.5.2 Register Setting
List Figures
Figure 16-Bit Implementation Figure 8-Bit Implementation
Interface Considerations Issue Date: 01/01/29
S1D13502 X16-AN-003-06
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S1D13502 X16-AN-003-06
Interface Considerations Issue Date: 01/01/29
Epson Research Development Vancouver Design Center
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INTRODUCTION
S1D13502 general purpose controller capable interfacing variety microprocessors. This interface accomplished through minimal external circuitry. This application note describes interface between S1D13502 Bus.
Reference Material
Refer S1D13502 Hardware Functional Specification (X16-SP-001-xx) complete timing details. This document makes attempts describe operation Bus, please refer appropriate documentation complete information.
Interface Considerations Issue Date: 01/01/29
S1D13502 X16-AN-003-06
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Epson Research Development Vancouver Design Center
16-BIT INTERFACE
purpose example shown below, following conditions default: Indexing with addresses 0310h 0311h (see Configuration Options) 128Kbytes display memory occupying segments (see Configuration Options)
Note This memory configuration will conflict with card installed same bus, therefore either serial terminal monochrome display adapter recommended primary console. This section provides necessary equations settings complete interface between S1D13502 16-bit Bus. Note used instead discrete logic reduce external component count.
16-Bit
REFRESH SA1-15 SA0-19 SBHE# SD0-15 SMEMW# SMEMR# IOW# IOR# IOCHRDY IOCS16# LA17-23 MEMCS16#
S1D13502
IOCS#
MEMCS#
AB0-19 BHE# DB0-15 MEMW MEMR IOW# IOR# READY VD0,VD7, VD11-12, VD14-15
IOCS16EN
LA23-17 (p0-6) 0000110 (q0-6)
74LS09 74LS688
Figure 16-Bit Implementation
S1D13502 X16-AN-003-06
Interface Considerations Issue Date: 01/01/29
Epson Research Development Vancouver Design Center
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Equations
programmed with following equations: stated above, default address from 0310h 0311h. S1D13502 provides internal decoding address bits therefore minimal external circuitry necessary provide signals IOCS# IOCS16# IOCS# required S1D13502 indicate valid cycle. environment, valid decoding must include addresses A15-A0. Given this example, addresses A10-15 must must also '0'. IOCS# !(!AEN !A15 !A14 !A13 !A12 !A11 !A10) S1D13502 capable 16-bit access, IOCS16# signal must driven externally indicate such cycle. stated specification, IOCS16# straight address decode without qualification. IOCS16EN# !(!IOCS# !A1) With 128Kbytes display memory decoded internally S1D13502; MEMCS# !REFRESH
Additional Discrete Logic Description
shown Figure 74LS688 configured memory decoder with valid addresses between 0Cxxxxh 0Dxxxxh. 74LS09 used simply provide Open-Collector outputs necessary IOCS16# MEMCS16# signals.
S1D13502 Default Setup 1.4.1 Configuration Options
VD15 VD13 VD12 110001000 memory decoding locations segments decoding locations 1100010000b 1100010001b byte swap high bytes interface, i.e. non- MC68K interface indexing 16-bit interface
Where pull-up with resistor; pull-up resistor Note states these data pins internally latched during RESET.
1.4.2 Register Setting
AUX[1] 16-bit memory interface (must 16-bit with 16-bit bus).
Interface Considerations Issue Date: 01/01/29
S1D13502 X16-AN-003-06
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Epson Research Development Vancouver Design Center
8-BIT INTERFACE
purpose example shown below, following conditions default: Indexing with partial decoding, i.e. address lines decoded cycles
Note Partial decoding quite safe most systems addresses above 03FFh rarely used. addresses xxxxxx1100000000b xxxxxx1100000001b 64Kbytes display memory occupying segment
Note 74LS00 simply used detect segment invalidate MEMCS# input. Note This memory configuration will conflict with card installed same bus, therefore either serial terminal monochrome display adapter recommended primary console. This section provides necessary settings complete interface between S1D13502 8-bit Bus. Since addresses partially decoded, there need decoding.
8-Bit
REFRESH SA16 SA0-19
S1D13502
IOCS# BHE#
MEMCS# VD11-13, VD15
74LS00 AB0-19
SD0-7 SMEMW# SMEMR# IOW# IOR# IOCHRDY
DB0-7 MEMW MEMR IOW# IOR# READY
Figure 8-Bit Implementation
S1D13502 X16-AN-003-06
Interface Considerations Issue Date: 01/01/29
Epson Research Development Vancouver Design Center
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S1D13502 Default Setup 1.5.1 Configuration Options
VD15 VD13 VD12 110000000 memory decoding locations segment decoding locations 1100000000b 1100000001b byte swap high bytes interface, i.e. non- MC68K interface Indexing 8-bit interface
Where pull-up with resistor; pull-up resistor Note states these data pins internally latched during RESET.
1.5.2 Register Setting
AUX[1] 16-bit memory interface AUX[1] 8-bit memory interface.
Interface Considerations Issue Date: 01/01/29
S1D13502 X16-AN-003-06
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Epson Research Development Vancouver Design Center
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S1D13502 X16-AN-003-06
Interface Considerations Issue Date: 01/01/29
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