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S5U13502 Dot Matrix Graphics LCD Controller

ISA Bus Interface Considerations

S5U13502 Dot Matrix Graphics LCD Controller
ISA Bus Interface Considerations
Document Number: X16-AN-003-06
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Epson Research and Development Vancouver Design Center
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S1D13502 X16-AN-003-06
ISA Bus Interface Considerations Issue Date: 01 / 01 / 29
Epson Research and Development Vancouver Design Center
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Table of Contents
8-BIT ISA BUS INTERFACE
List of Figures
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1 INTRODUCTION
The S1D13502 is a general purpose LCD controller capable of interfacing to a variety of microprocessors. This interface is accomplished through the use of minimal external circuitry. This application note describes the interface between the S1D13502 and the ISA Bus.
1.1 Reference Material
Refer to the S1D13502 Hardware Functional Specification (X16-SP-001-xx) for complete AC timing details. This document makes no attempts to describe the operation of the ISA Bus, please refer to the appropriate ISA Bus documentation for complete information.
ISA Bus Interface Considerations Issue Date: 01 / 01 / 29
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Epson Research and Development Vancouver Design Center
2 16-BIT ISA BUS INTERFACE
Note This memory configuration will conflict with a VGA card installed on the same bus, therefore either a serial terminal or monochrome display adapter is recommended as the primary console. This section provides the necessary equations and settings to complete the interface between the S1D13502 and the 16-bit ISA Bus. Note A PAL was used instead of discrete logic to reduce external component count.
16-Bit ISA Bus
AEN REFRESH SA1-15 SA0-19 SBHE# SD0-15 SMEMW# SMEMR# IOW# IOR# IOCHRDY 1 IOCS16# LA17-23 4 MEMCS16# 6 3
S1D13502
IOCS#
MEMCS#
AB0-19 BHE# DB0-15 MEMW MEMR IOW# IOR# READY VD0, VD7, VD11-12, VD14-15
IOCS16EN
LA23-17 (p0-6) 0000110 (q0-6)
74LS09 G 74LS688
Figure 8: 16-Bit ISA Bus Implementation
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1.2 PAL Equations
1.3 Additional Discrete Logic Description
1. 2. As shown in Figure 1, the 74LS688 is configured as a memory decoder with valid addresses between 0Cxxxxh and 0Dxxxxh. The 74LS09 is used simply to provide the Open-Collector outputs necessary for the IOCS16# and MEMCS16# signals.
1.4 S1D13502 Default Setup 1.4.1 Configuration Options
1.4.2 Register Setting
ISA Bus Interface Considerations Issue Date: 01 / 01 / 29
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Epson Research and Development Vancouver Design Center
3 8-BIT ISA BUS INTERFACE
For the purpose of the example shown below, the following conditions are set by default: 1. Indexing I / O with partial decoding, i.e. address lines A10 to A15 are not decoded for I / O cycles
8-Bit ISA Bus
AEN REFRESH SA16 SA0-19 1 4 5 3
S1D13502
IOCS# BHE#
MEMCS# VD11-13, VD15
74LS00 AB0-19
SD0-7 SMEMW# SMEMR# IOW# IOR# IOCHRDY
DB0-7 MEMW MEMR IOW# IOR# READY
Figure 9: 8-Bit ISA Bus Implementation
S1D13502 X16-AN-003-06
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Epson Research and Development Vancouver Design Center
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1.5 S1D13502 Default Setup 1.5.1 Configuration Options
1.5.2 Register Setting
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