Ultra Low-Power Mbps Ethernet Media Converter GENERAL DESCRIPTION

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Ultra Low-Power Mbps Ethernet Media Converter GENERAL DESCRIPTION

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AL2100
Ultra Low-Power Mbps Ethernet Media Converter
GENERAL DESCRIPTION AL2100 designed media converter applications. intended Mbps Fast Ethernet fiber optic-totwisted pair media converter designs. device provides PECL interface with media connectors such 1300 fiber optic module. AL2100 compatible with IEEE 802.3 100Base-FX 100Base-TX standards. AL2100 provides additional functionality such fault propagation, redundancy fault-tolerant system design, remote loopback diagnostic support. Power supply: 2.5V Mbps media converter: fiber-to-fiber fiber-totwisted pair Full duplex half duplex Auto-negotiation twisted pair 48-pin TQFP Industrial temp (-40°C +85°C) Power consumption 0.25µm CMOS Fully compliant with IEEE 802.3 802.3u Baseline wander compensation Multifunction outputs auto-MDI/MDIX Diagnostic register Fault propagation Redundancy fault tolerant system design Remote loop back diagnostic support
Clock Recovery
Descrambler
Elastic Store
100Base-TX Transceceiver
Transceiver
Fiber Module
Clock Recovery
Scrambler
Elastic Store
Figure System Block Diagram
AL2100-DS00-R 16215 Alton Parkway P.O. 57013 Irvine, 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710 2/22/02
AL2100
Preliminary Data Sheet
2/22/02
REVISION HISTORY
REVISION
AL2100-DS00-R
DATE
2/22/02
CHANGE DESCRIPTION
Initial Release
Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, 92619-7013 2002 Broadcom Corporation rights reserved Printed U.S.A.
Broadcom®, pulse logo, QAMLink registered trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
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Preliminary Data Sheet 2/22/02
AL2100
TABLE CONTENTS
Section Overview. Section Descriptions Section Functional Description.
100Base-TX 100Base-FX Conversion 100Base-FX 100Base-TX Conversion Full Duplex Application Elastic Store Fault Propagation. Fiber-to-Fiber Fiber-to-Twisted Pair. Twisted Pair-to-Fiber. Redundant Function. Redundant Link Receive Link Fault Transmits Link Fault. Remote Loop Back Function. Local Side Operation Remote Side Operation Indicators Configuration. Serial Management Interface Addresses. Clock Source. Power Source 100Base-Twisted Pair General Description Encoder/Decoder Link Monitor Selection. Analog Adaptive Equalizer. Clock Recovery
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Document AL2100-DS00-R Page
AL2100
Preliminary Data Sheet
2/22/02
Baseline Wander Correction.14 Multi mode Transmitter.15 Stream Cipher Scrambler/Descrambler.15 HP-Auto MDI/MDIX 100Base Fiber Encoder/Decoder.15 Link Monitor Clock Recovery Transmitter Fault (FEF).16 Transmit Driver
Section Register Descriptions
100base-Tx Registers Control Register.18 Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message.21 Auto-Negotiation Expansion Register.22 Auto-Negotiation Next Page Transmit Register.22 Diagnostic Register Power/Loopback Register Cable Measurement Capability Register Receive Error Counter.25 Power Management Register Operation Mode Register Recent Received Packet 100Base-FX Registers.27 Control Register.27 Status Register Identifier Register Identifier Register Receive Error Counter.29
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Preliminary Data Sheet 2/22/02
AL2100
Power Management Register Operation Mode Register Recent Received Packet. Common Registers Mode Control Register Common Register Blink Rate Register LED0 Setting1 Register LED0 Setting2 Register LED1 Setting1 Register LED1 Setting2 Register LED2 Setting1 Register LED2 Setting2 Register LED3 Setting1 Register LED3 Setting2 Register LED4 Setting1 Register LED4 Setting2 Register LED5 Setting1 Register LED5 Setting2 Register Configuration State Register.
Section 4B/5B Code-Group Table Section Read/Write Sequence. Section Electrical Specifications
Absolute Maximum ratings Recommended Operating Conditions. Electrical Characteristics
Section Timing Characteristics
Clock Timing. Reset Timing. Management Data Interface Timing.
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AL2100
Preliminary Data Sheet
2/22/02
Section Application Termination Section Application Termination Section Power Ground Filtering. Section Package Dimensions (48-Pin TQFP) Section Packaging Thermal Characteristics
48-TQFP Package
Section Ordering Information
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Preliminary Data Sheet
2/22/02
AL2100
LIST FIGURES
Figure System Block Diagram Figure AL2100 Figure State Machine Redundant Function. Figure Redundant Link Figure Reset Timing Figure Management Interface Timing. Figure Application Figure Application Figure Power Ground Filtering Figure Quad Flat Pack Outline
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AL2100
Preliminary Data Sheet
2/22/02
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Preliminary Data Sheet
2/22/02
AL2100
LIST TABLES
Table Descriptions. Table Formats Table Events LED's Operation Table SPD100 Setting Table Registers through Table Register Control Register Table Register Status Register. Table Register Identifier Register. Table Register Identifier Register. Table Register Auto-Negotiation Advertisement Register Table Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Table Register Auto-Negotiation Expansion Register Table Register Auto-Negotiation Next Page Transmit Register Table Register Diagnostic Register Table Register Power/Loopback Register Table Register Cable Measurement Capability Register. Table Register Receive Error Counter Table Register Power Management Register. Table Register Operation Mode Register Table Register Recent Received Packet. Table 100Base-FX Registers Table Register Control Register Table Register Status Register. Table Register Identifier Register. Table Register Identifier Register. Table Register Receive Error Counter Table Register Power Management Register. Table Register Operation Mode Register Table Register Recent Received Packet. Table Common Register Mode Control Register (Map TP_PHY, Reg. 28). Table Common Register Blink Rate (Map TP_Phy, Reg. Page [15:12] 0001) Table Common Register LED0 Setting1 (Map TP_Phy, Page a28[15:12] 0001)
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AL2100
Preliminary Data Sheet
2/22/02
Table Common Register LED0 Setting2 (Map TP_Phy, Reg. Page [15:12] 0001).32 Table Common Register LED1 Setting1 (Map TP_Phy, Reg. Page [15:12] 0010).32 Table Common Register LED1 Setting2 (Map TP_Phy, Reg. Page [15:12] 0010).33 Table Common Register LED2 Setting1 (Map TP_Phy, Reg. Page [15:12] 0010).33 Table Common Register LED2 Setting2 (Map TP_Phy, Reg. Page [15:12] 0011).33 Table Common Register LED3 Setting1 (Map TP_Phy, Reg. Page [15:12] 0011).34 Table Common Register LED3 Setting2 (Map TP_Phy, Reg. Page [15:12] 0011).34 Table Common Register LED4 Setting1 (Map TP_Phy, Page [15:12] 0100).34 Table Common Register LED4 Setting2 (Map TP_Phy, Page a28[15:12] 0100).35 Table Common Register LED5 Setting1 (Map TP_Phy, Reg. Page a28[15:12] 0100).35 Table Common Register LED5 Setting2 (Map TP_Phy, Reg. Page [15:12]=0101).35 Table Common Register Configuration State Register.35 Table 4B/5B Code-Group Table Table Read/Write Sequence Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Electrical Characteristics.41 Table Clock Timing Table Reset Timing Table Management Interface Timing Table 48-TQFP Package Thermal Characteristics Table
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Preliminary Data Sheet
2/22/02
AL2100
Section Overview
AL2100 (Figure contains physical layer interface (PHY) 100BASE-TX 100BASE-FX networks. contains necessary functions such elastic store, quantizer, driver circuits complete
media converter design. device converts MLT3 scrambled symbols from twisted-pair (TP) input port into 4B5B NRZI encoded data, transmits over fiber media. 4B5B NRZI encoded data from fiber-input port converted scrambled MLT3 symbol stream transmission. device also supports far-end fault detection (fiber-only) link status propagation. port link-fail state, device ceases transmit data, disables appropriate output port. device transparent regard connecting links. media converter uses elastic store retime received signal. AL2100 supports redundant link applications. redundant link formed either switch with 100BASE-FX transceiver that supports far-end fault signaling AL2100s. event link failure, redundant link established automatically.
PHYAD2/LED5_RMT_LPBK
PHYAD4/FX_DIS
PHYAD3/LED4_FDX
PHYAD1/LED_FX_SD
MDIO
RST#
SD_BF/XEN_B FEF_DIS FX2TP_DIS
VCCPLL RBIAD SD_A/FXEN_A
AL2100
48TQFP_7x7mm
RMT_LPBK_DIS/DATA_OFF
PHYAD0/LED_TP_SD
LED1 LED2/DUPLEX
REDUN#
TP2FX_DIS
RMT_LPBK_EN
LED3/ANEN
LED0
Figure AL2100
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Document AL2100-DS00-R Section Overview Page
PDOWN#
AL2100
Preliminary Data Sheet
2/22/02
Section Descriptions
Signal Types: Power Ground Analog Input Analog Output Digital Pull-Down Digital Pull-Up Active Bi-directional digital
Table Descriptions Name
SD_B/FXEN_B
Type
Description
2.5V supply. PECL input PECL input SD_B/FXEN_B: multilevel threshold input. When input level module disabled. When input module enabled, this used input with PECL threshold. PECL output PECL output Ground. Ground. (reset-read Input): pull high isolate PHY. Digital Ground. 2.5V supply. FEF_DIS (reset-read input): pull high disable remote fault function fiber PHY, i.e. fiber-to-fiber fault propagation disable. Output function reserved. FX2TP_DIS (reset read Input): pull high disable fiber-to-twisted-pair fault propagation. Output function reserved. REDUN#: redundancy function input. Input activate chip; input high chip backup mode. primary chip, this pulled low. secondary chip, this connected DATA_OFF primary chip. Output function reserved.
GNDFX FEF_DIS/(Reserved)
FX2TP_DIS/ (Reserved)
REDUN#/(Reserved)
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Preliminary Data Sheet
2/22/02
AL2100
Table Descriptions Name
RMT_LPBK_DIS/ DATA_OFF
Type
Description
RMT_LPBK_DIS (reset read Input): pull high disable detection remote loopback command packet. DATA_OFF: (output) high secondary chip backup mode. primary chip, this connected REDUN# secondary chip. TP2FX_DIS (reset read Input): pull high disable twisted pair-to-fiber fault propagation. Output function reserved. RMT_LPBK_EN (input): high force chip send special remote loopback command packet fiber port, compare receiving packet fiber port with remote loopback command packet. fault propagation features (F2F, F2T, T2F) disabled, twisted pair fiber port isolated from each other. Ground. 2.5V supply. PHYAD0 (reset read Input): pull high address serial management function. LED_TP_SD (output): indicates energy detected twisted-pair input. active level invert reset read value. Pull this high. LED0 (output): active. default behavior blinks when twistedpair port detects receive activity. Pull this high. LED1 (output): active. default behavior when twistedpair port link-up condition. DUPLEX (reset read Input): sets duplex capability twisted-pair port auto-negotiation function. LED2 (output): active value invert DUPLEX input level. default behavior blinks when fiber port detects receive activity. ANEN (reset read input): auto-negotiation enable twisted pair port. LED3 (output): active value invert ANEN input level. default behavior when link-up condition detected fiber port, blinks when remote fault condition detected fiber port. PDOWN# (low active input): pull both fiber ports into power-down mode. This regular input, reset read signal. 2.5V supply. Receive port mode. Transmit port MDIX mode. Receive port mode. Transmit port MDIX mode.
TP2FX_DIS/ (Reserved)
RMT_LPBK_EN
PHYAD0/ LED_TP_SD
LED0
LED1
DUPLEX/LED2
ANEN/LED3
PDOWN#
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AL2100
Preliminary Data Sheet
2/22/02
Table Descriptions Name
SD_A/FXEN_A
Type
Description
SD_A/FXEN_A: (multithreshold input): pull disable function twisted pair (TP) port. PECL input level enable function port. PECL high level indicate signal detect from connected fiber module. Ground. Ground. Bias resister connection. Connect resister Analog Bias, modules. Ground transmit circuit. Transmit mode. Receive MDIX mode. Transmit mode. Receive MDIX mode. 2.5V supply. Ground Ground (Output): crystal output. (Input): crystal input. pins designed connect MHz, 50-PPM crystal. When using oscillator, connect oscillator, leave unconnected. 2.5V supply. Reset input active low. MDIO (input/output): management data I/O. This serial input/output used read from write register. data value MDIO valid, latched rising edge MDC. This requires resistor pull-up. (Input): management data clock. clock input must provided allow serial management functions. This SCHMTTtrigger input. PHYAD1 (reset-read input): pull high address serial management functions. LED_FX_SD (output): output fiber signal detects. active level invert reset read value. PHYAD2 (reset-read input): pull high address serial management functions. LED5_RMT_LPBK (output): default behavior blinks when remote loopback command packet received. This programmable. active level invert reset read value.
RBIAD VCCPLL
RST# MDIO
PHYAD1/LED_FX_SD
PHYAD2/ LED5_RMT_LPBK
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Page Section Descriptions Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
Table Descriptions Name
PHYAD3/LED4_FDX
Type
Description
PHYAD3 (reset-read input): pull high address serial management functions. LED4_FDX (output): default behavior when result auto-negotiation twisted pair port full duplex. This fully programmable. active level invert reset read value. PHYAD4 (reset-read input): pull high address serial management functions. FX_DIS (output): disable fiber output. active level invert reset read value.
PHYAD4/FX_DIS
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Document AL2100-DS00-R Section Descriptions Page
AL2100
Preliminary Data Sheet
2/22/02
Section Functional Description
AL2100 contains physical layer interface (PHY) 100BASE-TX, 100BASE-FX networks. contains necessary functions, such elastic store, quantizer, driver circuits, complete media converter design. device converts MLT3 scrambled symbols from twisted-pair (TP) input port into 4B5B NRZI encoded data, transmits over fiber media. 4B5B NRZI encoded data from fiber-input port converted scrambled MLT3 symbol stream transmission. device also supports far-end fault detection (fiber-only), links status propagation. port link-fail state, device cease transmitting data, disables appropriate output port. essence, device transparent regard connecting links. media converter uses elastic store retime received signal. AL2100 supports redundant link applications. redundant link formed either switch with 100BASE-FX transceiver that supports far-end fault signaling AL2100s. event link failure, redundant link automatically established.
100BASE-TX 100BASE-FX CONVERSION
AL2100's 100BASE-TX receiver receives scramble MLT3 signals, passes them clock recovery circuit data/clock extraction.The device de-scrambles signals, decodes them into data stream. signal then passed through elastic-store circuitry retiming. resulting signal converted into serial NRZI data stream, sent 100Base-FX transmitter.
100BASE-FX 100BASE-TX CONVERSION
AL2100's 100BASE-FX receiver receives NRZI data stream through PECL receiver inputs, passes them clock recovery circuit data/clock extraction. device feeds signals through elastic-store circuitry retiming encoding NRZI data, conversion scramble MLT3 signals. signals sent 100BASE-TX transmitter.
FULL DUPLEX APPLICATION
ideal function media converter chip provides full-duplex transparent media link. AL2100 supports full IEEE 802.3-compliant auto-negotiation functions. Auto-negotiation enabled negotiate with link partner fullduplex applications.
ELASTIC STORE
AL2100 provides on-chip elastic store. With elastic store place, device retimes received signal, removes jitter. order reduce latency, preambles inserted packet.
FAULT PROPAGATION
Three types fault propagation provided using following logic: TP_RCVR_ACTIVE Wait_For_Link TP_Link_Up; TP_OUTPUT_EN (FX_LINK_UP FX2TP_DIS) DATA_ENABLE; FX_OUTPUT_EN TP_RCVR_ACTIVE TP2FX_DIS;
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Page Section Functional Description Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
FIBER-TO-FIBER
This same remote fault function. When remote fault disabled, AL2100 disables transmission received fails.
FIBER-TO-TWISTED PAIR
This operation controlled FX2TP_DIS signal. This signal only defined AL2100 normal operation mode, RMII testing mode. This reset read signal. When this type fault propagation enabled, failure link shuts down twisted pair output.
TWISTED PAIR-TO-FIBER
This operation controlled TP2FX_DIS signal. This signal only defined AL2100 normal operation mode. This reset read signal. When this type fault propagation enabled, absence receiving energy shuts down fiber transmission inform fiber link partner about link failure. AL2100 propagates idle signals from media-to-media. After reception idle signal (all ones), device transmits idle signal opposite ports, i.e. TP-to-fiber fiber-to-TP. There types link failure-receive remote fault- also known far-end fault.
Receive Link Failure. event TP-receive-link failure, AL2100 ceases transmit idle signal fiber-optic driver. valid link signal either 10BASE-T link pulse 100BASE-TX idle signal. Fiber Receive Link Failure. event fiber-receive-link failure, AL2100 ceases transmit idle signal driver, puts driver into high-impedance mode. device also sends remote fault signal fiber-optic driver addition asserting REDUN# signal. Transmit Link Failure. event transmit link failure, far-end transceiver ceases transmit idle
signal, starts transmitting AL2100. Because AL2100 does understand FLP, continues transmit idle signal fiber-optic driver.
Fiber Transmit Link Failure. event fiber-transmit-link failure, far-end transceiver, with remote fault signaling capability, transmits signal AL2100. result, AL2100 performs tasks: ceases transmit idle signal driver, puts driver into high-impedance mode, asserting REDUN# signal.
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AL2100
Preliminary Data Sheet
2/22/02
REDUNDANT FUNCTION
FAULT_OUT DATA_ENABLE !FX_LINK; logic above uses TP_RCVR_ACTIVE signal gate output. When receiver disconnected, forces side drop link, causes remote side drop link well. When both sides receive activity side, port each side enabled, link-up occurs. link status port enables output, causes them link remote fault condition generated standard FEF_DETECT state machine. Three timers generate TP_RCVR_ACTIVE signal. first activity_timer; second link_up_timer; third tx_disable_timer. When using activity_timer determine whether there signal wire, start link_up_timer, wait complete. link_up_timer expires, start tx_disable_timer, disable FX_OUPUT_EN TX_OUTPUT_EN predefined period time. Figure more details.
Reset
TP_Quite
Idle
!Activity_Timer_Done Wait_ For_Link Start Link_Up_Timer TP_LINK_UP
Activity_Timer _Reset
Link_Up_Timer_Done !TP_LINK_UP Activity_Timer_Done Link_Disable Start TX_Disable_Timer
Link_Pulse Sigdet
TP_Link_Up !TP_LINK_UP
TX_Disable_Timer_Done
Figure
State Machine Redundant Function
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Page Section Functional Description Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
REDUNDANT LINK
AL2100 supports redundant links through DATA_OFF REDUN# signals. redundant link function only available fiber port. implementation redundant link shown Figure redundant link also configured with fiber switch-ports, far-end fault signaling support required, AL2100s. There scenarios: either redundant link transmits link fault receive link fault triggers redundant link.
Redun#
Redun#
Local Primary AL2100
Data_off Redun#
Primary
Primary AL2100
Data_off Redun#
Local Back AL2100 Transformer Back
Back AL2100 Transformer
Redundant Link
Figure
Redundant Link
RECEIVE LINK FAULT
event receive-link failure, receiver goes into link-down mode. AL2100 takes following actions: Starts transmitting remote fault signal Puts pins high-impedance mode Asserts REDUN# signal
far-end primary transceiver normally link-up state, back-up transceiver link-fail state. During receivelink failure, local AL2100 enables data transmission backup transceiver asserting REDUN# signal. backup AL2100 starts sending copies transmit signal. primary far-end receiver that receives signal enters link-fail state. back-up transceiver exits link-fail state upon receiving signal from local AL2100, reestablishing link. When primary link repaired, REDUN# de-asserted.
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Preliminary Data Sheet
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TRANSMITS LINK FAULT
100BASE-FX specification provides detect transmit-link failure. Whenever fiber receiver experiences receive-link failure, transmits far-end fault signal. far-end fault signal indicated far-end fault IDLE signal ones followed zero). When AL2100 receives far-end fault signal, notified far-end station that transmit-fault occurred. device goes into link-down state, takes following actions: Puts pins high-impedance mode Asserts REDUN# signal
data transmission assumed backup AL2100, starts sending copies signals. Upon re-establishment primary fiber, REDUN# de-asserted, backup data link turned off.
REMOTE LOOP BACK FUNCTION
This feature enabled RMT_LPBK_EN signal. This regular signal, reset-read pin, debounce logic. AL2100 uses special in-band packet remote loopback. packet recognized AL2100 remote loopback command packet. packet invalid code, reported RX_ER layer. packet uses following format: minimal bytes preamble, special pattern, reason using invalid code make sure when connect repeater. loopback command packet forwarded unwanted ports.
LOCAL SIDE OPERATION
Assertion RMT_LPBK_EN signal, reset read, puts AL2100 into remote loopback mode, does following: Disables TP2FX, FX2TP fault propagation. Forces fiber-port link-up that remote side links even during fault propagation enabled mode, receive activity detected side. Disables data path from TP2FX FX2TP. Generates bursts loopback control packet fiber port; sufficient guaranteed allow remote side establish link condition. Monitors receiving side fiber port loopback control packet. Turns LED5_RMT_LPBK when loop back control packet received; makes blink.
REMOTE SIDE OPERATION
AL2100 configured ignore remote loopback command packet. When IGNORE mode enabled, AL2100 chip receives loopback control packet from port. AL2100 chip will perform following operation: Disables TP2FX FX2TP fault propagation Disables traffic forcing TXEN signal, RXDV, signal ground Enables fiber Rx-> fiber loopback Starts emote loopback timer. value timer packet time, including Turns LED5_RMT_LPBK when loopback control packet received; makes blink Restarts remote loopback timer whenever remote loopback command packet received; when remote loopback timer expires, exits from remote loopback mode.
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Page Section Functional Description Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
INDICATORS
Output. pins AL2100 multifunction I/Os. Their input used reset-read operation secondary definition. pins have internal pull-ups. output value depends reset-read value pin. When reset-read value high, default pins, output value
low. When reset read value low, output value high. Default formats given Table
Table Formats
LED0 LED1 LED2 LED3 LED4 LED5
Format
RxAct_TP (Blink) Link_TP (ON) RxAct_FX (Blink) Link_FX (ON) Remote_Fault (Blink) DUPLEX_TP (ON) RMT_LPBK_PKT_RX (Blink)
These LEDs configured into different modes. configure LEDs work with other operation mode other than default mode, Configuration section.
Note
connections source/sink current depend default setting.
AL2100 also support following LEDs: LED4_FDX: default defined full-duplex auto-negotiation resulting port. LED5_RMT_LPBK: when remote loopback mode; blinks when remote loopback command packet received. This hardware programmable. LED_FX_SD: signal detects Fiber PHY. This hardware cannot programmable. LED_TX_SD: receiving energy detects port. This hardware cannot programmable
CONFIGURATION
interface fully configurable common register setting. Table
Table Events LED's Operation [5:0] Bit#
Events Description
RxAct_FX Link_FX
Link_TP
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AL2100
Preliminary Data Sheet
2/22/02
Table Events LED's Operation [5:0] Bit#
Events Description
DUPLEX_TP TxAct_TP Remote_fault Remote_LPBK RxAct_TP
Each 16-bit registers that define operation. "Common Registers" page details.
SERIAL MANAGEMENT INTERFACE
management access performed MDIO. input SCHMTT triggered avoid noise this bused signal. PHY's internal registers accessible only through 2-wire Serial Management Interface (SMI). clock input PHY, which used latch data instructions PHY. clock speed from MHz. MDIO bi-directional connection used write instructions write data read data from PHY. Each data latched either rising edge MDC. required maintain speed duty cycle, provided half cycle less than that data presented synchronous MDC. MDIO common signal pair PHYs design. Therefore, each must have unique physical address. physical address using pins defined PHYAD[4:0]. These input signals strapped externally, sampled reset negated. idle, responsible pull MDIO line high state. Therefore, resistor required connect MDIO line VCC.
ADDRESSES
addresses taken under AL2100 mode. PHYAD [4:0], other PHYAD [4:0] first twisted-pair PHY; second fiber PHY. addresses PHYAD4, PHYAD3, PHYAD2, PHYAD1, PHYAD0 signals.
CLOCK SOURCE
clock source this chip from signal. normal operation mode (media converter), signal connected Mhz, Oscillator signals connected MHz, Crystal.
POWER SOURCE
single supplied digital analog operations.
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Page Section Functional Description Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
100BASE-TWISTED PAIR
GENERAL DESCRIPTION
twisted pair performs physical layer interface functions 100Base-TX full half-duplex CAT5 twisted pair cable. 100Base-TX performs encoder/decoder, link monitor, auto-negotiation selection, adaptive equalization, clock/data recovery, baseline wander correction, multimode transmitter, scrambler/descrambler, far-end fault (FEF), auto-MDI/MDIX. fully compliant with IEEE 802.3 803.3u standards.
ENCODER/DECODER
100Base-TX mode, AL2100 transmits receives data streams twisted pair. When transmit enable asserted, nibble wide (4-bit) data from transmit data pins encoded into 5-bit code groups, inserted into transmit data stream. 4B5B encoding shown 4B/5B CODE-GROUP table. transmit packet encapsulated replacing first nibbles preamble with start-of-stream delimiter (J/K codes), appending end-of-stream delimiter (T/R codes) packet. When transmit error input asserted during packet, error code group sent place corresponding data code group. transmitter repeatedly sends idle code group between packets. 100Base-TX mode, encode data stream scrambled stream cipher block, serialized encoded into MLT3 signal level. multimode transmit (digital analog converter) used drive MLT3 data onto twisted pair cable. Following baseline wander correction, adaptive equalization, clock/data recovery 100Base-TX mode. receive data stream converted from MLT3 serial data. data descrambled stream cipher block, deserialized aligned into 5-bit code groups.
LINK MONITOR
100Base-TX mode, receive signal energy detected monitoring receive pair transitions signal level. signal levels qualified using squelch detect circuits. When signal, certain valid signal, detected receive pair minimum period time, link monitor enters link-pass state, transmit receive functions enabled.
SELECTION
Auto-negotiation selection 100Base-T twisted-pair only; operating 100Base-Fiber PHY. 100Base-TX mode, auto-negotiation enabled disabled hardware software control. When autonegotiation function enabled, 100Base-TX automatically chooses mode operation advertising abilities, comparing them with those received from link partner. 100Base-TX configured advertise 100Base-TX full-duplex 100BaseTX half-duplex. default auto-negotiation mode configured reset read value LED3/ANEN, LED2/DUPLEX. SPD100 signal always defaulted When SPD100 undefined, result unexpected.
Table SPD100 Setting Register
0.13
Name
Speed Select
Description
100Mbps normal operation. prohibited. Enable auto-negotiation Disable auto-negotiation
0.12
ANEN Enable
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AL2100
Preliminary Data Sheet
2/22/02
Table SPD100 Setting Register
4.8/1.14 4.7/1.13
Name
Duplex 100Base-TX Full Duplex 100Base-TX
Description
default value !ANEN DUPLEX default value this DUPLEX default value this ANEN ||!DUPLEX
ANALOG ADAPTIVE EQUALIZER
analog adaptive equalizer removes inter-symbol interference (ISI) created transmission channel media. designed accommodate maximum meters CAT-5 cable. AT&T 1061 CAT-5 cable this length typically attenuation 31dB MHz. typical attenuation 100-meter cable 21dB. worst case cable attenuation around 24-26dB, defined TP-PMD specification. amplitude phase distortion from cable cause ISI, which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer ability change equalizer frequency response according cable length. equalizer tunes itself automatically cable, compensating amplitude phase distortion introduced cable.
CLOCK RECOVERY
equalized MLT-3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary mixed-signal phase locked loop (PLL) extract clock information from incoming NRZI data. extracted clock used retime data stream, data boundaries. transmit clock locked clock input, while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. recovered clock also used generate RX_CLK signal. requires external components operation, high noise immunity jitter. provides fast phase alignment, locks data transition. data/clock acquisition time after power-on less than transitions. maintain lock run-lengths data bits absence signal transitions. When valid data present, i.e. when de-asserted, switches locks onto TX_CLK. This provides continuously running RX_CLK. interface, 5-bit data RXD[4:0] synchronized RX_CLK.
BASELINE WANDER CORRECTION
100Base-TX data stream always balanced because receive signal must pass through transformer. offset differential receive input wander. This effect, known baseline wander, greatly reduce noise immunity receiver. 100Base-TX automatically compensates baseline wander removing offset from input signal, thereby significantly reduces chance receive symbol error.
Note
baseline wander circuit required 100Base-FX PHY.
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Preliminary Data Sheet
2/22/02
AL2100
MULTI MODE TRANSMITTER
multimode transmitter transmits MLT3 coded symbols in100Base-TX mode, NRZI coded symbols 100Base-FX mode. uses current drive output, which well balanced, produces very noise transmit signals. PECL voltage levels produced with resistive terminations 100base-FX mode.
STREAM CIPHER SCRAMBLER/DESCRAMBLER
100Base-TX mode, transmit data stream scrambled reduce radiated emissions twisted pair cable. data scrambled exclusive ORing signal with output 11-bit wide linear feed back shift register (LFSR), which produces 2047-bit repeating sequence. scrambler reduces peak emission randomly spreading signal energy over transmit frequency range, eliminating peaks certain frequencies. receiver descrambles incoming data stream exclusive ORing with same sequence generated transmitter. descrambler detects state transmit LFSR looking sequence representing consecutive idle codes. descrambler locks scrambler state after detecting sufficient number consecutive idle code groups. receiver does attempt decode data stream unless descrambler locked. When locked, descrambler continuously monitors data stream make sure that lost synchronization. receive data stream expected contain interpacket idle periods. descrambler does detect enough idle code within becomes unlocked, receive decoder disabled. descrambler always forced into unlock state when link failure condition detected.
Note
stream cipher descrambler used 100Base-FX mode.
HP-AUTO MDI/MDIX
This feature detects required cable connection type straight through crossed over, makes corrections automatically.
100BASE FIBER
AL2100 includes fiber PHY. transmit receive data over fiber-optic cable when paired with external fiberoptic line driver receiver. mode, receive data stream differential PECL level sampled from fiber-optic receiver. NRZI decoding used instead MLT3. Baseline wander, adaptive equalization, stream cipher descrambler functions bypassed.
ENCODER/DECODER
decoded data driven onto receive data pins. When invalid code group detected data stream, fiber asserts RXER signal. fiber also asserts RXER several other error conditions that improperly terminate data stream. While RXER asserted, receive data pins driven with 4-bit code, indicating type error detected. error codes listed Table page
LINK MONITOR
100Base-FX mode, external fiber-optic receiver performs signal energy detection function, communicates this information directly signal,
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CLOCK RECOVERY
digital clock recovery creates internal transmit receive clocks. transmit clock locked clock input, while receive clock lock incoming data stream. clock recovery circuit optimized MLT3, NRZI. input data stream sampled recovery clock, synchronously adaptive equalizer.
TRANSMITTER
Serialized data bypasses scrambler 4B/5B encoder mode. output data from NRZI PECL signals. PECL level signals used drive fiber-transmitter.
FAULT (FEF)
Auto-negotiation provides mechanism inform link partner that remote fault occurred. However, autonegotiation disabled 100Base-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive followed logic This pattern repeated three times. FEFI signals only under following conditions: When activity received from link partner When clock recovery circuit detects signal error lock error When management entity sets transmit
FEFI mechanism enabled default 100Base-FX mode, disabled 100Base-TX 10Base-T modes. register setting changed software after reset.
TRANSMIT DRIVER
transmit driver does perform filtering. uses current drive output, which well balanced, produces noise PECL signal. PECL voltage levels produced with resistive terminations.
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AL2100
Section Register Descriptions
first seven registers register defined specification. addition these required registers several Altima Communications, Inc. specific registers. There reserved registers and/or bits that Altima internal only. following standard registers supported. Register numbers decimal format. values hexadecimal binary format. When writing registers, recommended that read/modify/write operation performed because unintended bits unwanted states. This applies registers, including those with reserved bits. Legend: Read write access Self-clearing Latch until cleared reading Read-only Cleared read Latch high until cleared reading
Note
100BASE-TX REGISTERS
Table Registers through Register
8-15 18,19
Description
Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register Reserved Interrupt Level Control Register Interrupt Control/Status Register reserved because there hardware support. Reserved Cable Measurement Capability Register
Default
3000 7849 0022 5523 01E1 0001 0004 2001 XXXX 03C0 0000 XXXX XXXX
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Table Registers through Register
22-31
Description
Receive Error Counter Register Reserved
Default
0000 XXXX
CONTROL REGISTER
Table Register Control Register Register
0.15
Name
Reset
Description
reset. This self-clearing. Enable loopback mode. This loops back RXD, ignores activity cable media. Normal operation. normal operation; prohibited. Enable auto-negotiation process (overrides 0.13 0.8) Disable auto-negotiation process. Mode selection controlled 0.8, 0.13 through mode pins. Power-down blocks. While power-down state, responds management transactions. Setting PDOWN#, same result. Normal operation. Electrically isolate from MII. still responds SMI. Normal operation. Restart auto-negotiation process. Normal operation. Full duplex. Half duplex. Enable collision test, which issues signal response assertion TX_EN signal. Collision test disabled when PCSBP high. Collision test enabled regardless duplex mode. Disable test.
Mode
RW/SC
Default
0.14
Loop back
0.13 0.12
Speed Select ANEN Enable
ANEN
0.11
Power Down
0.10
Isolate
Restart ANEN Duplex Mode
RW/SC
mode
Collision Test
0.[6:0]
Reserved
0000000
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AL2100
STATUS REGISTER
Table Register Status Register Register
1.15 1.14
Name
100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Preamble Suppression ANEN Complete
Description
Permanently tied indicates 100BaseT4 capability. 100BaseTX full-duplex capable. 100BaseTX full-duplex capable. 100BaseTX half-duplex capable. half-duplex capable. 10BaseT full-duplex capable. 10BaseT-full duplex capable. 10BaseT half-duplex capable. 10BaseT half-duplex capable.
Mode
Default
DUPLEX DUPLEX
1.13
1.12
1.11
1.[10:7]
able perform management transactions without MDIO preamble. management interface needs minimum bits preamble after reset. Auto-negotiation process completed. Registers valid after this set. Auto-negotiation process complete. Remote fault condition detected. remote fault. This remains until cleared reading Register Able perform auto-negotiation function; default value determined ANEN pin. Unable perform auto-negotiation function. Link established. link fails, this cleared, remains until register read again. Link gone down. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently
0000
Remote Fault
RO/LH
ANEN Ability
ANEN
Link Status
RO/LL
Jabber Detect
RO/LH
Extended Capability
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IDENTIFIER REGISTER
Table Register Identifier Register Register
2.[15:0]
Name
Description
Composed third through 18th bits Organizationally Unique Identifier (OUI), respectively. Note below.
Mode
Default
0022(H)
Note
Based 0010A9 (hex)
IDENTIFIER REGISTER
Table Register Identifier Register Register
3.[15:10] 3.[9:4] 3.[3:0]
Name
Model Number Revision Number
Description
Assigned 19th through 24th bits OUI. Note below. manufacturer's model number. 4-bit manufacturer's revision number.
Mode
Default
010101 010010 0001
Note
Based 0010A9 (hex)
AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Table Register Auto-Negotiation Advertisement Register Register
4.15
Name
Next Page
Description
Next Page enabled. Next Page disabled. This internally after receiving three consecutive consistent bursts.
Mode
Default
4.14 4.[13:11]
Acknowledge Reserved
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AL2100
Table Register Auto-Negotiation Advertisement Register Register
4.10
Name
FDFC
Description
Full-Duplex Flow Control Advertise that (MAC) implemented both optional control sublayer pause function specified Clause Annex 802.3u. does support flow control. Technology supported. This always 100BaseTX full-duplex capable. 100BaseTX full-duplex capable. 100BaseTX half-duplex capable. half-duplex capable. 10BaseT full-duplex capable. 10BaseT full-duplex capable. 10BaseT half-duplex capable. 10BaseT half-duplex capable. Protocol Selection [00001] IEEE 802.3.
Mode
Default
100Base-T4 100Base-TX Full Duplex 100Base-TX
DUPLEX DUPLEX
10Base-T Full Duplex 10Base-T
4.[4:0]
Selector Field
00001
AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER/LINK PARTNER NEXT PAGE MESSAGE
Table Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Register
5.15
Name
Next Page
Description
Link partner desires Next Page transfer. Link partner does desire Next Page transfer. Link Partner acknowledges reception words. acknowledged Link Partner.
Mode
Default
5.14
Acknowledge
5.[13:10]
Reserved 100Base-T4 100BaseT4 supported Link Partner. 100BaseT4 supported Link Partner. 100BaseTX full-duplex supported Link Partner. 100BaseTX full-duplex supported Link Partner. 100BaseTX half-duplex supported Link Partner. 100BaseTX half-duplex supported Link Partner. 10Mbps full-duplex supported Link Partner. 10Mbps full-duplex supported Link Partner. 10Mbps half-duplex supported Link Partner. 10Mbps half-duplex supported Link Partner.
100Base-TX Full Duplex 100Base-TX
10Base-T Full Duplex 10Base-T
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Table Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Register
5.[4:0]
Name
Selector Field
Description
Protocol Selection [00001] IEEE 802.3.
Mode
Default
00001
Note
When this register used Next Page Message, definition same Register
AUTO-NEGOTIATION EXPANSION REGISTER
Table Register Auto-Negotiation Expansion Register Register
6.[15:5]
Name
Reserved Parallel Detection Fault
Description
Mode
Default
Fault detected parallel detection logic. This fault more than technology detecting concurrent link-up condition. This only cleared reading Register using management interface. fault detected parallel detection logic. Link Partner supports next page function. Link Partner does support next page function. Next page supported. This when link code word been received into Auto-Negotiation Link Partner Ability Register. This cleared upon read this register. Link partner auto-negotiation capable. Link partner auto-negotiation capable.
RO/LH
Link Partner Next Page Able Next Page Able Page Received
Link Partner ANEN-Able
AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER
Table Register Auto-Negotiation Next Page Transmit Register Register
7.15
Name
Description
Another Next Page desired. other Next Page Transfer desired.
Mode
Default
7.14 7.13
Reserved Message page. Unformatted page.
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Table Register Auto-Negotiation Next Page Transmit Register Register
7.12
Name
ACK2
Description
Complies with message. Does comply with message. Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Unformatted Code Field.
Mode
Default
7.11
TOG_TX
7.[10:0]
CODE
DIAGNOSTIC REGISTER
Table Register Diagnostic Register Register
18.[15] 18.[14] 18.[13] 18.[12]
Name
Reserved Reserved Reserved Force link pass DPLX
Description
Mode
Default
Enable Force Link Base-T. Disable. This indicates result auto-negotiation duplex. Full duplex. Half duplex. This indicates result auto-negotiation speed. 100Base-T. 10Base-T. 100BT mode, this indicates that valid signal received necessarily locked onto. This indicates that receive locked onto received signal selected speed operation (100Base-TX). This whenever cycle-slip occurs, remains until read.
18.11
18.10
Speed
18.9 18.8
RX_PASS RX_LOCK
RO/RC
18.[7:0]
Reserved
POWER/LOOPBACK REGISTER
Table Register Power/Loopback Register Register
19.[14:7] 19.6
Name
Reserved Reserved
Description
Mode
Default
00000000
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Table Register Power/Loopback Register Register
19.5
Name
Disable watch timer decipher Power Mode disable Enable digital loopback Reserved Reserved Reserved
Description
Disable watchdog timer. Enable watchdog timer. Disable advance power saving mode. Enable advance power saving mode. Enable digital loopback. Disable digital loopback. Reserved Reserved. Reserved.
Mode
Default
19.4
19.3
19.1 19.0
CABLE MEASUREMENT CAPABILITY REGISTER
Table Register Cable Measurement Capability Register Register
20.15 20.14
Name
Reserved Reserved
Description
Mode
Default
Turn Turn off.
20.[13:9] 20.8
Reserved Adaptation disable Turn adaptation disable mode. Turn off. value 20.[7:4], turn 20.8, turn 20.14, this rejects receive packets. These bits used cable length indicator. bits incremented from 0000 1111 with increment approximately meters. equivalent 32dB with increment MHz. value read back from equalizer; measured value absolute.
20.[7:4]
Cable measurement capability
20.[3:0]
Reserved
XXXX
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AL2100
RECEIVE ERROR COUNTER
Table Register Receive Error Counter Register
21.[15:0]
Name
RX_ER Counter
Description
Count receive error events.
Mode
Default
POWER MANAGEMENT REGISTER
Table Register Power Management Register Register
22.[15:14 22.13 22.12 22.11 22.10 22.9 22.8 22.[7:6] 22.5 22.4 22.3 22.2 22.1 22.0
Name
Reserved PD_PLL PD_EQUAL PD_BT_RCVR PD_LP PD_EN_DET PD_FX Reserved MSK_PLL MSK_EQUAL MSK_BT_RCVR MSK_LP MSK_EN_DET MSK_FX
Description
Mode
Default
Power down circuit. Power down equalizer circuit. Power down base receiver. Power down link pulse receiver. Power down energy detect circuit. Power down circuit.
Force power circuit. Force power equalizer circuit. Force power base receiver. Force power link pulse receiver. Force power energy detect circuit. Force power circuit
OPERATION MODE REGISTER
Table Register Operation Mode Register Register
23.[15:14] 23.13 23.12
Name
Reserved Reserved Reserved
Description
Mode
Default
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Table Register Operation Mode Register Register
23.11
Name
Scramble disable Reserved Pcsbp
Description
Disable scrambler data. Enable scrambler data.
Mode
Default
23.10 23.9
Enable bypass mode. disable bypass mode.
23:8 23.[7:6] 23.5 23.[4:0]
Reserved Reserved Reserved Reserved
XXXXX
RECENT RECEIVED PACKET
Table Register Recent Received Packet Register
24.[15:0]
Name
CRC16
Description
CRC16 value displayed. system level test purpose.
Mode
Default
0000H
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AL2100
100BASE-FX REGISTERS
Table 100Base-FX Registers Register
4-20 22-31
Name
Control Register Status Register Identifier Register Identifier Register Reserved Receive Error Counter Register Reserved
Address
3000 7849 0022 5523 XXXX 0000 XXXX
CONTROL REGISTER
Table Register Control Register Register
0.15
Name
Reset
Description
reset. This self-clearing. Enable loopback mode. This loops back RXD, ignores activity cable media. Normal operation. 100Mbps. Default always This undefined. Enable auto-negotiation process (overrides 0.13 0.8) Disable auto-negotiation process. Mode selection controlled 0.8, 0.13 through mode pins. Power down. blocks except turned off. Setting PWRDN high achieves same result. Normal operation. Electrically isolate from MII. still able response SMI. Normal operation. Restart auto-negotiation process. Normal operation. Full duplex. Half duplex.
Mode
RW/SC
Default
0.14
Loopback
0.13
Speed Select
0.12
ANEN Enable
ANEN
0.11
Power Down
0.10
Isolate
Restart ANEN
RW/SC
Duplex Mode
DUPLEX
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Table Register Control Register Register
Name
Collision Test
Description
Enable collision test, which issues signal response assertion TX_EN signal. Collision test disabled when PCSBP high. Collision test enabled regardless duplex mode. Disable test.
Mode
Default
0.[6:0]
Reserved
0000000
STATUS REGISTER
Table Register Status Register Register
1.15 1.14
Name
100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Preamble Suppression ANEN Complete
Description
Permanently tied indicates 100BaseT4 capability. 100BaseTX full-duplex capable. 100BaseTX full-duplex capable. 100BaseTX half-duplex capable. half-duplex capable. 10BaseT full-duplex capable. 10BaseT full-duplex capable. 10BaseT half-duplex capable. 10BaseT half-duplex capable.
Mode
Default
1.13
1.12
1.11
1.[10:7]
able perform management transaction without MDIO preamble. management interface needs minimum bits preamble after reset. Auto-negotiation process completed. Registers valid after this set. Auto-negotiation process complete. Remote fault condition detected. remote fault. This remains until cleared reading Register Able perform auto-negotiation function; default value determined ANEN pin. Unable perform auto-negotiation function. Link established. link fails, this cleared, remains until register read again. Link gone down. Jabber condition detect. jabber condition detected.
0000
Remote Fault
RO/LH
ANEN Ability
Link Status
RO/LL
Jabber Detect
RO/LH
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Table Register Status Register Register
Name
Extended Capability
Description
Extended register capable. This tied permanently
Mode
Default
IDENTIFIER REGISTER
Table Register Identifier Register Register
2.[15:0]
Name
OUI*
Description
Composed third through 18th bits Organizationally Unique Identifier (OUI), respectively.
Mode
Default
0022(H)
Note
Based 0010A9 (hex).
IDENTIFIER REGISTER
Table Register Identifier Register Register
3.[15:10] 3.[9:4] 3.[3:0]
Name
Model Number Revision Number
Description
Assigned Bits through OUI. 6-bit manufacturer's model number. 4-bit manufacturer's revision number.
Mode
Default
010101 010010 0001
Note
Based 0010A9 (Hex). When this register used Next Page Message, definition same Register
RECEIVE ERROR COUNTER
Table Register Receive Error Counter Register
21.[15:0]
Name
RX_ER Counter
Description
Count receive error events.
Mode
Default
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POWER MANAGEMENT REGISTER
Table Register Power Management Register Register
22.[15:14] 22.13 22.12 22.11 22.10 22.9 22.8 22.[7:6] 22.5 22.4 22.3 22.2 22.1 22.0
Name
Reserved PD_PLL PD_EQUAL Reserved PD_LP PD_EN_DET PD_FX Reserved MSK_PLL MSK_EQUAL Reserved MSK_LP MSK_EN_DET MSK_FX
Description
Mode
Default
Power down circuit. Power down equalizer circuit.
Power down link pulse receiver. Power down energy detect circuit. Power down circuit.
Force power circuit. Force power equalizer circuit.
Force power link pulse receiver. Force power energy detect circuit. Force power circuit.
OPERATION MODE REGISTER
Table Register Operation Mode Register Register
23.[15:14] 23.13 23.12 23.11 23.10 23.9 23:8 23.[7:6] 23.5
Name
Reserved Clk_rclk_save Reserved Scramble disable Reserved Pcsbp Reserved Reserved Reserved
Description
Mode
Default
rclk save mode. Rclk shuts after cycles each packet.
Disable scrambler
Enable bypass mode.
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Table Register Operation Mode Register Register
23.[4:0]
Name
Reserved
Description
Mode
Default
XXXXX
RECENT RECEIVED PACKET
Table Register Recent Received Packet Register
24.[15:0]
Name
CRC16
Description
CRC16 value displayed. system level test purposes.
Mode
Default
0000H
COMMON REGISTERS
following registers mapped Registers through PHY. Register 28[15:12] used page select. There multiple pages Registers through depending value Register 28[15:12].
MODE CONTROL REGISTER
Table Common Register Mode Control Register (Map TP_PHY, Reg.
a.28.[15:12] a.28.[11:7] a.28.6 a.28.5 a.28.4
Page Selection Reserved Reserved Reserved RMII_enable
Select multiple common register pages.
0000 0000
chip reduce mode. Normal operation.
a.28.3 a.28.2
Reserved select event select. Receive activity. activity.
a.28.1 a.28.0
Reserved Reserved
COMMON REGISTER
Common Registers reserved.
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BLINK RATE REGISTER
Table Common Register Blink Rate (Map TP_Phy, Reg. Page [15:12] 0001) Register
A1.29 [15:8] A1.29.[7:0]
Name
Reserved Blink Rate
Description
Reserved blink rate. blink rate this number times Default
Mode
Default
00000000 00010000
LED0 SETTING1 REGISTER
default operation LED0 BLINK RX_ACT. default operation LED5 BLINK when Remote loopback packet received.
Table Common Register LED0 Setting1 (Map TP_Phy, Page a28[15:12] 0001) Register
A1.30.[15:13] A1.30.12 A1.30.[11:9] A1.30.8 A1.30.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Mode
Default
00000001
Force LED0
Force LED0 Off. Blink mask. When bits corresponding event causes blink.
LED0 SETTING2 REGISTER
Table Common Register LED0 Setting2 (Map TP_Phy, Reg. Page [15:12] 0001) Register
A1.31. [15:8] A1.31.[7:0]
Name
Description
mask. When bits one, corresponding events cause turn mask. When bits corresponding events cause turn
Mode
Default
00000000
00000000
LED1 SETTING1 REGISTER
default operation LED1 TP_LINK.
Table Common Register LED1 Setting1 (Map TP_Phy, Reg. Page [15:12] 0010) Register
A2.29 [15:13] A2.29.12 A2.29.[11:9]
Name
Reserved Force Reserved
Description
Reserved Force LED1 Reserved
Mode
Default
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AL2100
Table Common Register LED1 Setting1 (Map TP_Phy, Reg. Page [15:12] 0010) Register
A2.29.8 A2.29.[7:0]
Name
Force Blink
Description
Force LED1 Blink mask. When bits one, corresponding events cause blink.
Mode
Default
00000000
LED1 SETTING2 REGISTER
Table Common Register LED1 Setting2 (Map TP_Phy, Reg. Page [15:12] 0010) Register
A2.30. [15:8] A2.30.[7:0]
Name
Description
mask. When bits corresponding events cause turn mask. When bits corresponding events cause turn off.
Mode
Default
00100000
0000
LED2 SETTING1 REGISTER
default operation LED2 BLINK RxAct_FX.
Table Common Register LED2 Setting1 (Map TP_Phy, Reg. Page [15:12] 0010) Register
A2.31 [15:13] A2.31.12 A2.31.[11:9] A2.31.8 A2.31.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Reserved Force LED2 Reserved Force LED2 Off. Blink mask. When bits corresponding events cause blink
Mode
Default
10000000
LED2 SETTING2 REGISTER
Table Common Register LED2 Setting2 (Map TP_Phy, Reg. Page [15:12] 0011) Register
A3.29. [15:8] A3.29.[7:0]
Name
Description
mask. When bits corresponding events cause turn mask. When bits corresponding events cause turn off.
Mode
Default
00000000
00000000
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LED3 SETTING1 REGISTER
default operation LED3 FX_LINK, BLINK Remote_fault.
Table Common Register LED3 Setting1 (Map TP_Phy, Reg. Page [15:12] 0011) Register
A3.30. [15:13] A3.30.12 A3.30.[11:9] A3.30.8 A3.30.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Mode
Default
00000100
Force LED3
Force LED3 Off. Blink mask. When bits corresponding events cause blink
LED3 SETTING2 REGISTER
Table Common Register LED3 Setting2 (Map TP_Phy, Reg. Page [15:12] 0011) Register
A3.31. [15:8] A3.31.[7:0]
Name
Description
mask. When bits corresponding events cause turn mask. When bits corresponding events cause turn off.
Mode
Default
01000000
00000000
LED4 SETTING1 REGISTER
default operation LED4 when result auto negotiation twisted pair port full duplex.
Table Common Register LED4 Setting1 (Map TP_Phy, Page [15:12] 0100) Register
A4.29 [15:13] A4.30.12 A4.29.[11:9] A4.29.8 A4.29.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Mode
Default
00000000
Force LED4
Force LED4 Off. Blink mask. When bits corresponding events cause blink
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LED4 SETTING2 REGISTER
Table Common Register LED4 Setting2 (Map TP_Phy, Page a28[15:12] 0100) Register
A4.30. [15:8] A4.30.[7:0]
Name
Description
mask. When bits corresponding events cause turn mask. When bits corresponding events cause turn off.
Mode
Default
00010000
00000000
LED5 SETTING1 REGISTER
Table Common Register LED5 Setting1 (Map TP_Phy, Reg. Page a28[15:12] 0100) Register
A4.31 [15:13] A4.31.12 A4.31.[11:9] A4.31.8 A4.31.[7:0]
Name
Reserved Force Reserved Force Blink
Description
Mode
Default
0000 00010
Force LED5
Force LED5 Off. Blink mask. When bits corresponding events cause blink.
LED5 SETTING2 REGISTER
Table Common Register LED5 Setting2 (Map TP_Phy, Reg. Page [15:12]=0101) Register
A5.29. [15:8] A5.29.[7:0]
Name
Description
mask. When bits corresponding events cause turn mask. When bits corresponding events cause turn off.
Mode
Default
00000000
00000000
CONFIGURATION STATE REGISTER
Table Common Register Configuration State Register Register
Name
Reserved IOSLATE
Description
Mode
Default
Isolation. Normal operation. Far-end fault disable send remote fault signal out). Normal operation.
FEF_DIS
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Table Common Register Configuration State Register Register
Name
FX2TP_DIS
Description
link affected state. Normal operation. link affected state. Normal operation.
Mode
Default
TP2FX_DIS
Reserved PHYAD0 Reserved Reserved DUPLEX Full duplex. Half duplex. Turn auto-negotiation. Turn auto-negotiation. address setting address setting address setting address setting Reserved address setting
ANEN
PHYAD4 PHYAD3 PHYAD2 PHYAD1 Reserved
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Section 4B/5B Code-Group Table
Table Symbol Name
4B/5B Code-Group Table Description
Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
Code
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Code
11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101
Idle Control Code
0000 0101 0101 Undefined Undefined 11111 11000 10001 01101 00111 Idle Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol.
Invalid Code
Undefined Undefined 00100 00000 Transmit Error; used send HALT code-group Invalid code
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Table Symbol Name
4B/5B Code-Group Table Description
Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
Code
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Code
00001 00010 00011 00101 00110 01000 01100 10000 11001
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Section Read/Write Sequence
Table Read/Write Sequence Preamble Bits)
Read Write
Start Bits)
OpCode Bits)
PHYAD Bits)
AAAAA AAAAA
REGAD Bits)
RRRRR RRRRR
Turn Around Bits)
Data Bits)
Idle
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AL2100
Preliminary Data Sheet
2/22/02
Section Electrical Specifications
NOTE: following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings Parameter
SUPPLY VOLTAGE Input Voltage Input Current Supply AL2100 Storage Temperature Electrostatic Discharge
Symbol
VESD
GND-0.3 GND-0.3
2.75 2.75
Units
+125 1000
RECOMMENDED OPERATING CONDITIONS
Table Recommended Operating Conditions Parameter
Supply Voltage High-Level Input Voltage Low-Level Input Voltage PECL Low-Level Input Voltage PECL High-Level Input Voltage Differential Input Voltage Common Mode Input Voltage Common Mode Input Voltage Ambient Operating Temperature
Symbol
VIDIFF VICM VICM
Digital Inputs Digital Inputs FIP/FIN RXP/RXN FIP/FIN
Operating Mode
2.375
2.625
Units
100BaseFX 100BaseFX 100BaseFX 100BaseTX 100BaseFX
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Page Section Electrical Specifications Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics Parameter
Supply Current
Symbol
Pins
VCC,VCCPLL
Conditions
100BASE-TX 100BASE-FX 100BASE-TX 100BASE-FX
Units
Supply Current Power Down Mode High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Low-Level Output Voltage Differential Output Voltage Input Current Input Current Bias Voltage
VCC,VCCPLL
Digital Outputs
-12mA
2.5V Driving Load Magnetic Module
VCC-0.4
VODIFF VBIAS
TXP/TXN Digital Outputs TXP/TXN FOP/FON Digital Inputs w/PullUp Resistor Other Digital inputs RBIAD
VCC+ VCC-1.5 +200 1.18 1.30
Driving Load Magnetic Module 100BASE-FX
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Document AL2100-DS00-R Section Electrical Specifications Page
AL2100
Preliminary Data Sheet
2/22/02
Section Timing Characteristics
CLOCK TIMING
Table Clock Timing Parameter
XTAL Input Cycle Time XTAL Input High/Low Time XTAL Input Rise/Fall Time
Symbol
CK_CYCLE CK_HI CK_LO CK_EDGE
Units
RESET TIMING
Table Reset Timing Parameter
Reset Pulse Length Period with Stable XTAL Input Reset Rise/Fall Time
Symbol
RESET_LEN RESET_WAIT
Units
CK_EDGE
CK_EDGE
CK25
CK_HI CK_LO
Normal ctivit begin
CK_CYCLE RESET_EDGE
RESET#
RESET_LEN RESET_EDGE RESET_WAIT
Figure
Reset Timing
MANAGEMENT DATA INTERFACE TIMING
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Page Section Timing Characteristics Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
Table Management Interface Timing Parameter
Cycle Time High/Low Rise/Fall Time MDC_RISE MDC_FALL MDIO_SETUP MDIO_HOLD MDIO_DELAY
Symbol
MDC_CYCLE
Units
MDIO Input Setup Time Rising MDIO Input Hold Time from Rising MDIO Output Delay from Rising
MDC_CYCLE
MDC_RISE
MDC_FALL MIDO_HOLD MDIO_SETUP MIDO_HOLD MDIO_SETUP
MDIO (into AL2100) MDIO (from AL2100)
MDIO_DELAY
Figure
Management Interface Timing
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Document AL2100-DS00-R Section Timing Characteristics Page
AL2100
Preliminary Data Sheet
2/22/02
Section Application Termination
2.5V 49.9_1/16W_1% 49.9_1/16W_1% 49.9_1/16W_1% 49.9_1/16W_1% .1uF .1uF
Auto MDI/MDIX Magnetic
RJ45
AL2100
2.5V
4578
75_1/16W_5% 75_1/16W_5%
75_1/16W_5% 75_1/16W_5%
.1uF
.1uF
1000PF_2KV
Auto MDI/MDIX Magnetics: BEL: S558-5999-WD; Pulse: H1102; HALO: TG110-S050n2
Figure
Application
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Page Section Application Termination Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
Section Application Termination
Please contact Altima Communications, Inc. latest component value recommendation.
3_3V
2_5V
3_3V
3_3V
BLM11A601S
BLM11A601S
.1uF
.1uF .1uF
0.01UF
0.01UF
.1uF
Z=50 Z=50
.1uF .1uF
Z=50
Z=50 RDSD
AL2100
SD/FXEN_B
Z=50
RxVcc RxVee TxVcc TxVee
Z=50 Z=50
.1uF .1uF
Z=50 Z=50
HFBR-5903
Figure
Application
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Document AL2100-DS00-R Section Application Termination Page
AL2100
Preliminary Data Sheet
2/22/02
Section Power Ground Filtering
Power Connections AL2100 Place capacitor close possible each power pin.
AL2100
VCCPLL
2.2UF
.01UF
.1UF
.01UF
2.2UF
.1UF
.1UF
.1UF
.1UF
Place these capacitors next pins
Figure
Power Ground Filtering
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Page Section Power Ground Filtering Document AL2100-DS00-R
Preliminary Data Sheet
2/22/02
AL2100
Section Package Dimensions (48-Pin TQFP)
Figure
Quad Flat Pack Outline
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Document AL2100-DS00-R Section Package Dimensions (48-Pin TQFP) Page
AL2100
Preliminary Data Sheet
2/22/02
Section Packaging Thermal Characteristics
48-TQFP PACKAGE
Table 48-TQFP Package Thermal Characteristics Airflow (Feet/Minute
Theta (°C/W)
53.9 °C/W
51.2 °C/W
°C/W
48.6 °C/W
47.5 °C/W
Table Maximum Junction Temperature
Theta (°C/W) Junction Temperature
Temperature
24.7 °C/W
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Page Section Packaging Thermal Characteristics Document AL2100-DS00-R
AL2100
Preliminary Data Sheet
2/22/02
Section Ordering Information
Part Number
AL2100KQT
Package
48TQFP
Ambient Temperature
Broadcom Corporation
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
Broadcom Corporation reserves right make changes without further notice products data herein improve reliability, function, design. Information furnished Broadcom Corporation believed accurate reliable. However, Broadcom Corporation does assume liability arising application this information, application product circuit described herein, neither does convey license under patent rights rights others.
Document AL2100-DS00-R

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