Dual Voltage Video/Memory Clock Generator Integrated Circuit Syst

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Dual Voltage Video/Memory Clock Generator Integrated Circuit Syst

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ICS90C65
Dual Voltage Video/Memory Clock Generator
Integrated Circuit Systems ICS90C65 dual clock generator applications. simultaneously generates clocks. clock video memory, other video clock. ICS90C65 been specifically designed serve portable market with operation either 3.3V with comprehensive power-saving shut-down mode. This data sheet supplies sales order information, functional overview, signal details, block diagram, AC/DC characteristics, timing diagrams, package mechanical information.
Features
Specified dual voltage operation (VDD=3.3V 5V), operates continuously from 3.0V 5.25V Designed powered-down extended battery life Backward compatibility ICS90C64 ICS90C63 Dual Clock generator IBM-compatible Western Digital Imaging Video Graphics Array (VGA) devices, 8514/A chip sets Integral loop filter components, reduce cost phase jitter Generates fifteen video clock frequencies (including 25.175 28.322 MHz) derived from 14.318 system clock reference frequency On-chip generation eight memory clock frequencies Video clock selectable among internally generated clocks external clock CMOS technology Available 20-pin PLCC, SOIC packages
Description
Integrated Circuit Systems Video Graphics Array Clock Generator (ICS90C65) capable producing different output frequencies under firmware control. video output frequency derived from 14.318 system clock available PC/XT/AT Personal System/2 computers. designed work with Western Digital Imaging Video Graphics Array 8514/A devices optimize video subsystem performance. video clock output internallygenerated frequencies external input. selection video clock frequency done through four inputs. VSEL0 VSEL1 VSEL2 VSEL3
VSEL0 VSEL1 latched SELEN signal. VSEL2 VSEL3 used direct inputs VCLK selection. Table truth table VCLK selection. input truth table have been designed allow direct connection many Western Digital Imaging controllers 8514/A chip sets. MCLK output eight internally-generated frequencies shown Table 1-2. various VCLK MCLK frequencies derived from 14.318 input frequency. VCLKE MCLKE input tristate VCLK MCLK outputs facilitate board level testing.
Note:ICS90C65N (DIP) pin-out identical ICS90C65M (SOIC) pin-out.
90C65ARevA111095
ICS90C65
ICS90C65 Interface
ICS90C65 system interfaces: System Controller, well other programmable inputs. Figure shows Integrated Circuit Systems's Clock ICS90C65 connected controller. Western Digital Imaging controllers normally have status that indicates controller that working with clock chip. When working with clock chip controller changes inputs outputs. They theVCLK1/VCSLD/VCSEL VCLK2/VCSEL/VCSELH outputs they used select required video frequency. When power-down capabilities used, control signal PWRDN normally held group latches. power-down function used, PWRDN must tied VDD, otherwise internal pull-down will place chip power-down mode.
WD90C26
pull-up reset PR15(5)=0 AMD(3) LATCH VCSEL
VCKIN MCLK
ICS90C65
VSEL0 VSEL1 VSEL2 SELEN 14.318 CLK1 PWRDN VCLK
Figure
ICS90C65
System Inputs
system inputs are: CLKI VSEL0 VSEL1
User-Definable Inputs
user definable inputs are: EXTCLK VLCKE, MCLKE MSELO-2 VSEL2, VSEL3 PWRDN
ICS90C65 uses system 14.318 clock reference generate frequencies both video memory clocks. Data lines commonly used inputs VSEL0 VSEL1 video frequency selection.
EXTCLK additional input that internally routed VCLK output. This additional input useful supporting modes that require frequencies provided ICS90C65 during board test. VCLKE MCLKE output enable signals VCLK MCLK. When respective output tristated. MSEL0-2 memory clock (MCLK) select lines. Table shows MCLK frequencies selected. signals this group have internal pull-up resistors. VSEL2 VSEL3 video clock (VCLK) select lines that select additional VCLK frequencies. Table 1-1. VSEL2 VSEL3 have internal pull-ups. PWRDN place ICS90C65 power-down mode which drops supply current requirement below microamp. When placed this mode, digital inputs either high floating without causing increase ICS90C65 supply current. PWRDN must internal pull-down.) order place device power state. output pins (VCLK MCLK) driven high ICS90C65 when power state. CLKI being driven external source, driven high without power penalty. CLKI intermediate voltage (VSS+0.5 <VDD-0.5), there will small increase supply current. CLKI driven 14.318 while chip power-down, ICS90C65 supply current will increase approximately SELEN (pin used guard against inadvertent frequency changes during power-down/powerup sequences. holding SELEN during power-down power-up sequences, ICS90C65 will retain most recent video frequency selection.
Inputs from Controller
controller input ICS90C65 SELEN
ICS90C65 programmed generate different video clock frequencies using inputs VSEL0, VSEL1, VSEL2, VSEL3. signals VSEL2 VSEL3 supplied controller case Western Digital Imaging controllers. inputs VSEL0-1 latched with signal SELEN. SELEN input should active pulse. This active pulse generated Western Digital Imaging controllers during writes internal register 3C2h. Note: Only VSEL0 VSEL1 latched with signal SELEN.
Outputs Controller
outputs from ICS90C65 controller are: MCLK VCLK
MCLK VCLK clock outputs controller.
Analog Filters
analog filters integral ICS90C65 device. external components required. This feature reduces board space requirements component costs. Phase-jitter reduced externally-generated noise cannot easily influence phase-locked loop filter.
ICS90C65
Power Considerations
ICS90C65 product requires AVDD supply free fast rise time transients. This requirement several ways highly dependent characteristics host system. adapter card unique that must function unknown environment. volt power quality dependent only quality power supply resident host system, also other cards plugged into host's backplane. Power supply noise ranges from fair terrible. adapter manufacturer control over this, must assume worst. best solution create clean volts deriving from volt supply using zener diode dropping resistor. resistor volt Zener diode least costly accomplish this. .047 microfarad bypass capacitor tied from AVDD AvSS insures good high- frequency decoupling this point. Laptop notebook computers have entirely different problems with power. Typically they have volt supply; however, they much quieter electrically. Because designer complete control system architecture, place sensitive components systems such RAMDAC Dual Video/Memory Clock away from DRAM other noise-generating components. Most systems provide power that clean enough allow jitter-free Dual Video/Memory Clock performance volt supply decoupled with resistor microfarad Tantalum capacitor. Digital inputs that desired held static logical high level should tied volts this result excessive current drain through protection diode. internal pull-up resistors will adequately keep these inputs high.
ICS90C65
Descriptions
following table provides descriptions 20-pin ICS90C65 packages. NUMBER SYMBOL CLKI MSEL2 EXTCLK VSEL1 VSEL0 SELEN VSEL2 VSEL3 MSEL0 DVSS MSEL1 MCLK PWRDN MCLKE AVDD AVSS VCLKE VCLK DVDD
TYPE
DESCRIPTION Reference input clock from system. Select input MCLK selection. External clock input additional frequency. Control input VCLK selection. Control input VCLK selection. Strobe latching VSEL(0,1) (low enable). Control input VCLK selection. Control input VCLK selection. Select input MCLK selection. Ground Digital Circuit. Select input MCLK selection. Memory Clock Output. Power Down Control. Enable input MCLK output (high enables output). Power supply analog circuit. Ground analog circuit. connection. Enable input VCLK output (high enables output). Video Clock Output. Power supply Digital Circuit.
Note: CLKI, EXTCLK,VSEL0, VSEL1,VSEL2, VSEL3, SELEN, MSEL0, MSEL1, MSEL2, VCLKE, MCLKE input pins have internal pull-up resistors. PWRDN internal pull-down resistor.
ICS90C65
Absolute Maximum Ratings
Ambient Temperature under bias Storage temperature Voltage inputs outputs with respect 70°C -40°C 125°C volts
Standard Test Conditions
characteristics below apply following standard test conditions, unless otherwise noted. voltages referenced Ground). Positive current flows into referenced pin. Operating Temperature range Power supply voltage 70°C 5.25 volts
Note: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Timing Characteristics
following notes apply parameters presented this section: REFCLK 14.318 1/FC units nanoseconds (ns). Maximum jitter within range after triggering scope. Rise fall time between unless otherwise stated. Output loading 15pF Duty cycle measured VDD/2 unless otherwise stated.
SYMBOL
STROBE TIMING Strobe Pulse Width Setup Time Data Strobe Hold Time Data Strobe MCLK VCLK TIMINGS 5.0V Rise Time Fall Time Frequency Error Maximum Frequency Propagation Delay Pass Through Frequency Output Enable Tristate (into time MCLK VCLK TIMINGS 3.3V Rise Time Fall Time Frequency Error Maximum Frequency Propagation Delay Pass Through Frequency Output Enable Tristate (into time
PARAMETER
NOTES
Duty Cycle min. max.
Duty Cycle min. max.
ICS90C65
Characteristics Volts
SYMBOL Cout PARAMETER Operating Voltage Range Input Voltage Input High Voltage Input Leakage Current Output Voltage Output High Voltage Supply Current Internal Pull-up Resistors Input Capacitance Output Capacitance Power-down Supply Current Internal Pull-down Equivalent 4.75 5.25 UNITS ohms ohms CONDITIONS 0.0V VDD=3.3V VIN=VDD=5V
Characteristics Volts
SYMBOL Cout PARAMETER Operating Voltage Range Input Voltage Input High Voltage Input Leakage Current Output Voltage Output High Voltage Supply Current Internal Pull-up Resistors Input Capacitance Output Capacitance Power-down Supply Current Internal Pull-down Equivalent UNITS ohms ohms CONDITIONS 3.3V 3.3V 3.3V 0.0V =3.3V =VDD =3.3V
ICS90C65
ICS90C65 Timing
ICS90C65
Table VCLK SELECTION
VSEL VCLK FREQUENCY (MHz) Pattern 30.0 77.25 EXTCLK 80.0 31.5 36.0 75.0 50.0 40.0 50.0 32.0 44.9 25.175 28.322 65.0 36.0
Table MCLK SELECTION
MSEL MCLK FREQUENCIES (MHz) Pattern 33.0 49.218 60.0 30.5 41.612 37.5 36.0 44.296
ICS90C65
20-Pin Package
20-Pin SOIC Package
PLCC Package Ordering Information
ICS90C65N ICS90C65M ICS90C65V
Example:
XXXX-
Package Type
N=DIP (Plastic) M=SOIC V=PLCC
Pattern Number digit number parts with code patterns) Device Type (consists digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device

Dual Voltage Video/Memory Clock Generator Integrated Circuit Syst

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