Dual Video/Memory Clock Generator Integrated Circuit Systems ICS9

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Dual Video/Memory Clock Generator Integrated Circuit Systems ICS9

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ICS90C64A
Dual Video/Memory Clock Generator
Integrated Circuit Systems ICS90C64A dual clock generator applications. simultaneously generates clocks. clock video memory, other video clock. This data sheet supplies sales order information, functional overview, signal details, block diagram, AC/DC characteristics, timing diagrams, package mechanical information.
Features
Improved compatibility with Western Digital Controllers 100% backward compatible with ICS90C63 ICS90C64 Dual Clock generator compatible Western Digital Imaging Video Graphics Array (VGA) devices, 8514/A chip sets Integral loop filter components. Reduce cost phase-jitter Generates video clock frequencies (including 25.175 28.322 MHz) derived from 14.318 system clock reference frequency On-chip generation eight memory clock frequencies. Video clock selectable among fifteen internally generated clocks external clock CMOS technology Available 20-pin PLCC, SOIC, packages
Description
Integrated Circuit Systems Video Graphics Array Clock Generator (ICS90C64A) capable producing different output frequencies under firmware control. video output frequency derived from 14.318 system clock available PC/XT/AT Personal System/2 computers. designed work with Western Digital Imaging Video Graphics Array 8514/A devices optimize video subsystem performance. video clock output fifteen internallygenerated frequencies external input. selection video clock frequency done through four inputs. VSEL0 VSEL1 VSEL2 VSEL3
VSEL0 VSEL1 latched SELEN signal. VSEL2 VSEL3 used direct inputs VCLK selection. Table truth table VCLK selection. input truth table have been designed allow direct connection many Western Digital Imaging controllers 8514/A chip sets. MCLK output eight internally-generated frequencies shown Table 1-2. various VCLK MCLK frequencies derived from 14.318 Input frequency.
Note: ICS90C64AN (DIP) pin-out identical ICS90C64AM (SOIC) pin-out.
90C64ARevA111095
ICS90C64A
ICS90C64A Interface
ICS90C64A system interfaces: System Controller, well analog filters seven user programmable inputs. Figure shows Integrated Circuit Systems Clock ICS90C64A connected controller. Western Digital Imaging controllers normally have status that indicates controller that working with clock chip. When working with clock chip controller changes clock inputs, VCLK1 VCLK2, outputs. These outputs used select required video frequency.
Figure ICS90C64A Interface
Note: should placed close possible ICS90C64A AVDD pin.
ICS90C64A
System Inputs
system inputs are: CLK1 VSEL0 VSEL1 ICS90C64A uses system 14.318 clock reference generate frequencies both video memory clocks. Data lines commonly used inputs VSEL0 VSEL1 video frequency selection.
Analog Filters
analog filters integral ICS90C64A device. external components required. This feature reduces board space requirements component costs. Phase-jitter reduced externally-generated noise cannot easily influence phase-locked loop filter.
User-Definable Inputs
user-definable inputs are: EXTCLK VLCKE, MCLKE MSELO-2 VSEL2, VSEL3
Inputs from Controller
controller input ICS90C64A SELEN ICS90C64A programmed generate different video clock frequencies using inputs VSEL0, VSEL1, VSEL2, VSEL3. signals VSEL2 VSEL3 supplied controller case Western Digital Imaging controllers. inputs VSEL0-1 latched with signal SELEN. SELEN input should active pulse. This active pulse generated Western Digital Imaging controllers during writes internal register 3C2h. Note: Only VSEL0 VSEL1 latched with signal SELEN.
EXTCLK additional input that internally routed VCLK output. This additional input useful supporting modes that require frequencies provided ICS90C64A. VCLKE MCLKE output enable signals VCLK MCLK. When low, respective output tristated. MSEL0-2 memory clock (MCLK) select lines. Table shows MCLK frequencies selected. signals this group have internal pull-up resistors. VSEL2 VSEL3 video clock (VCLK) select lines that select additional VCLK frequencies. Table 1-1. VSEL2 VSEL3 have internal pull-ups.
Outputs Controller
outputs from ICS90C64A controller are: MCLK VCLK MCLK VCLK clock outputs controller.
ICS90C64A
Power Considerations
ICS90C64A product requires AVDD supply free fast rise time transients. This requirement several ways highly dependent characteristics host system. adapter card unique that must function unknown environment. volt power quality dependent only quality power supply resident host system, also other cards plugged into host's backplane. Power supply noise ranges from fair terrible. adapter manufacturer control over this, must assume worst. best solution create clean volts deriving from volt supply using zener diode dropping resistor. resistor volt Zener diode least costly accomplish this. .047 microfarad bypass capacitor tied from AVDD AVss insures good high-frequency decoupling this point. Laptop notebook computers have entirely different problems with power. Typically they have volt supply; however, they much quieter electrically. Because designer complete control system architecture, place sensitive components systems such RAMDAC Dual Video/Memory Clock away from DRAM other noise-generating components. Most systems provide power that clean enough allow jitter- free Dual Video/Memory Clock performance volt supply decoupled with resistor microfarad Tantalum capacitor. Digital inputs that desired held static logical high level should tied volts this will result excessive current drain through protection diode. internal pull-up resistors will adequately keep these inputs high.
ICS90C64A
Table VCLK Selection
ICS90C64A 30.0 77.25 EXTCLK 80.0 31.5 36.0 75.0 50.0 40.0 50.0 32.0 44.9 25.175 28.322 65.0 36.0 VCLK Frequency (MHz) ICS90C64A-903 ICS90C64A-907 30.250 30.0 77.25 77.25 EXTCLK EXTCLK 80.0 80.0 31.5 31.5 35.5 36.0 75.0 75.0 72.0 50.0 40.0 40.0 50.0 50.0 32.0 32.0 44.9 44.9 25.175 25.175 28.322 28.322 65.0 65.0 36.0 36.0 ICS90C64A-909 30.0 77.25 EXTCLK 80.0 31.5 36.0 75.0 50.0 40.0 50.0 32.0 44.9 25.175 28.322 65.0 36.0
Table MCLK Selection
ICS90C64A 33.0 49.218 60.0 30.5 41.612 37.5 36.0 44.296 MCLK Frequencies (MHz) ICS90C64A-903 ICS90C64A-907 65.0 33.0 49.218 49.218 60.0 60.0 62.5 30.5 41.612 41.612 37.5 37.5 55.0 36.0 44.296 44.296 ICS90C64A-909 75.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0
ICS90C64A
Figure
ICS90C64A Functional Block Diagram
ICS90C64A
Descriptions
following table provides descriptions 20-pin ICS90C64A packages. NUMBER SYMBOL CLK1 MSEL2 EXTCLK VSEL1 VSEL0 SELEN VSEL2 VSEL3 MSEL0 DGND MSEL1 MCLK MCLKE AVDD AGND VCLKE VCLK DVDD
TYPE
DESCRIPTION Reference input clock from system. Select input MCLK selection. External clock input additional frequency. Control input VCLK selection. Control input VCLK selection. Strobe latching VSEL(0,1) (low enable). Control input VCLK selection. Control input VCLK selection. Select input MCLK selection. Ground Digital Circuit. Select input MCLK selection. Memory Clock Output. connection. Enable input MCLK output (high enables output). Power supply analog circuit. Ground analog circuit. connection. Enable input VCLK output (high enables output). Video Clock Output. Power supply Digital Circuit.
Note: CLK1, EXTCLK,VSEL0, VSEL1,VSEL2, VSEL3, SELEN, MSEL0, MSEL1, MSEL2, VCLKE, MCLKE input pins have internal pull-up resistors.
ICS90C64A
Absolute Maximum Ratings
Ambient Temperature under bias Storage temperature Voltage inputs outputs with respect 70°C -40°C volts Operating Temperature range Power supply voltage 70°C 4.75 5.25 volts
Standard Test Conditions
characteristics below apply following standard test conditions, unless otherwise noted. voltages referenced Ground). Positive current flows into referenced pin.
Note: Stresses above those listed under Absolute Maximum Rating cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Characteristics
SYMBOL PARAMETER Input Voltage Input High Voltage Input Leakage Current Output Voltage Output High Voltage Output High Voltage Supply Current VDD-.4 UNITS CONDITIONS
4.0mA load VCLK MCLK load VCLK MCLK
Supply Current
Cout
Internal Pull-up Resistors Input Capacitance Output Capacitance
ohms
ICS90C64A
Timing Characteristics
following notes apply parameters presented this section: REFCLK 14.318 1/FC units nanoseconds (ns), unless labeled otherwise. Output loading 15pF
SYMBOL Tpwen Tsuen Thden
PARAMETER Enable Pulse Width Setup Time Data Enable Hold Time Data Enable Rise Time Fall Time
SELEN TIMING Reference Input Clock
NOTES
MCLK VCLK TIMINGS
Phase-Jitter max. Duty Cycle 42.5% min. 57.5% max. .8V-2.0V* 2.0V-.8V VDD-.7 VDD-.3 1.4V Switch Point VDD/2 Switch Point
Thigh Thigh
Rise Time Fall Time Rise Time Fall Time Duty Cycle Duty Cycle Frequency Error Maximum Frequency Propagation Delay Pass Through Frequency Output Enable Tri-State (into time
*WD90C11 Video Controller designed with level input thresholds inputs driven ICS90C64A VCLK MCLK outputs. later controllers (WD90C20, WD90C22, WD90C26, WD90C30, WD90C31) designed with input switch points VCC/2 (CMOS).
ICS90C64A
Figure
ICS90C64A Timing
ICS90C64A
20-Pin Package
20-Pin SOIC Package
Note: Package Dimensions inches.
PLCC Package
Ordering Information
ICS90C64AN ICS90C64AM ICS90C64AV
Example:
XXXX-
Package Type
N=DIP (Plastic) M=SOIC V=PLCC
Pattern Number digit number parts with code patterns) Device Type (consists digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device

Dual Video/Memory Clock Generator Integrated Circuit Systems ICS9

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