ATL35 Gate Array/Embedded Array Description. ATL35 Array Organiza
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ATL35 GateArray/Embedded Array-1.4-03/02
ATL35 Gate Array/Embedded Array
Description. ATL35 Array Organization: Table Design. Design Systems Supported Design Flow Tools Definition Requirements. Gate Array/Embedded Array Design Flow. Design Options Logic Synthesis. ASIC Design Translation. FPGA Conversion Macro Cores AVR(8-bit RISC) Microcontroller (8515). ARM7TDMIEmbedded Microcontroller Core OakDSPCore. LodeTMDSPCore. Volt Characteristics: Table. Volt Characteristics: Table. Volt Characteristics: Table. Buffer Characteristics: Table. 1-10 Buffers 1-10 Timing Derating Factors 1-10 ATL35 Volt Process Derating Factors: Table 1-10 ATL35 Volt Combined Derating Factors: Table. 1-10 Source CMOS Power Dissipation 1-10 Power Calculation. 1-11 Power Ground Pins 1-11 Power/Ground Rules. 1-11 Fixed Power/Ground Pads 1-11
ATL35 GateArray/Embedded Array-1.4-03/02
Description
ATL35 Series Gate Array Embedded Array families fabricated 0.35µ CMOS process, with levels metal. This family features arrays with million routable gates pins. high density high count capabilities ATL35 family, coupled with ability embed microcontroller cores, engines, memory, same silicon, make ATL35 series arrays ideal choice System Level Integration.
ATL35 Array Organization
Device Number ATL35/44 ATL35/68 ATL35/84 ATL35/100 ATL35/120 ATL35/132 ATL35/144 ATL35/160 ATL35/184 ATL35/208 ATL35/228 ATL35/256 ATL35/304 ATL35/352 ATL35/388 ATL35/432 ATL35/484 ATL35/540 ATL35/600 ATL35/700 ATL35/800 ATL35/900 ATL35/976 Routable Gates(1) 4,195 13,230 22,200 33,480 47,839 59,185 71,737 90,514 121,877 150,085 182,880 233,774 334,044 425,958 520,695 652,421 768,033 964,078 1,196,371 1,642,242 1,999,526 2,542,995 2,767,931 Routable Gates(1) 3,729 11,760 19,734 29,760 42,211 52,222 63,298 79,866 107,538 131,324 160,020 204,552 292,288 369,164 451,269 565,431 658,314 826,353 1,025,460 1,407,636 1,691,906 2,151,765 2,306,609 Available Routing Sites(2) 6,216 19,600 32,890 49,600 75,042 92,840 112,530 141,984 191,180 250,142 304,800 389,624 556,740 757,260 925,680 1,159,860 1,462,920 1,836,340 2,278,802 3,128,080 4,101,592 5,216,400 6,150,958 Count Count Gate Speed(3) 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps 150ps
Notes: gate NAN2 Routing site transistors Nominal 2-input NAND Gate 3.3V
ATL35 Gate Array/Embedded Array
ATL35 GateArray/Embedded Array-1.4-03/02
Design
Design Systems Supported
Atmel supports several major software systems design with complete cell libraries, well utilities following design systems supported:
System Version 4.4.3 2.1.p2 4.1-s051 3.4B 5.2e Later 98.08, 98.05 Synopsys5.0.1A Exemplar
netlist verification, test vector verification accurate delay simulations.
Tools Opus- Schematic Layout Verilog- Verilog SimulatorPearl- Static Path Verilog-XL- Verilog Simulator Logic Design Planner- Floorplanner BuildGates- Synthesis (Ambit) Modelsim Verilog VHDL (VITAL) Simulator QuickVHDLVSS- VHDL Simulator Design Compiler- Synthesis Test Compiler Scan Insertion ATPG Primetime- Static Path VCS- Verilog Simulator Leonardo Spectrum Synthesis TurboCheck Gate TurboScan TurboFault
1061D-9/99
Cadence®
Mentor/Model Tech
1998.2f V2.2 V2.2 V1.6
Syntest
Design Flow Tools
Atmel's Gate Array/Embedded Array design flow structured allow designer consolidate greatest number system components onto same silicon chip, using widely available third party design tools. Atmel's cell library reflects silicon performance over extremes temperature, voltage process, includes effects metal loading, inter-level capacitance edge rise fall times. design flow includes clock tree synthesis customer-specified skew latency goals. extraction performed final design database incorporated into timing analysis. Gate Array/Embedded Array Design Flow, shown following page, provides pictorial description typical interaction between Atmel's design staff customer. Atmel will deliver design kits support customer's synthesis, verification, floorplanning scan insertion activities. Tools such Synopsys Cadence®, Verilog-HDLTM, CTgenTM, Exemplar PathMILLand TimeMILLare used, many others available. Should design include embedded memory (SRAM, CAM) embedded core, Atmel will conduct design review with customer understand partition Gate Array/Embedded Array define location memory blocks and/or cores derlayer yout mode created. Following Database Acceptance, automated test pattern generation (ATPG) performed, required, scan paths using Synopsysor Sunrisetools, design routed, post-route data extracted. After postroute verification Final Design Review, design taped fabrication.
Definition Requirements
corner pads reserved Power Ground only. other pads fully programmable Input, Output, Bidirectional, Power Ground. When implementing design with compliant buffers, buffer site must reserved VDD5 pin, which used distribute power compliant buffers.
ATL35 GateArray/Embedded Array-1.4-03/02
Gate Array/Embedded Array Design Flow
Deliver Design
Kickoff Meeting
Embedded Array
Define Underlayer
Synthesis/ Translation/ Conversion
Scan/JTAG
Simulation/ Static Path
Floorplan
Embedded Array
Create Underlayer
Database Handoff
Tape Underlayer
Database Acceptance
Fabricate Underlayer
Place Route/ Clock Tree
Verification/ Resimulation
Final Design Review
Tape Personality Layers
Fabricate Personality
Customer Atmel Joint
Assembly Test
ATL35 Gate Array/Embedded Array
ATL35 GateArray/Embedded Array-1.4-03/02
Design Options
Logic Synthesis
Atmel accept netlists VHDL (MIL-STD-454, IEEE 1076) Verilog-HDL format. Atmel fully supports Synopsys VHDLsimulation well synthesis. VHDL Verilog-HDL Atmel's preferred database format Gate Array/Embedded Array design.
counter, 16-bit timer/counter, external internal interrupts programmable watchdog timer.
ARM7TDMIEmbedded Microcontroller Core
ARM7TDMI (Advanced RISC Machines) powerful 32-bit processor offered embedded core ATL35 series arrays. ARM7TDMI member Advanced RISC Machines (ARM) family general purpose 32-bit microprocessors, which offer high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective chip. Pipelining employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. memory interface been designed allow performance potential realized without incurring high costs memory system. Speed critical control signals pipelined allow system control functions implemented standard low-power logic, these control signals facilitate exploitation fast local access modes offered industry standard SRAMs. ARM7TDMI core includes several optional peripheral macros. options offered Real Time Clock, Controller, USART, External Interface, Interrupt, Timer Advanced Power Management Controller.
ASIC Design Translation
Atmel successfully translated existing designs from most major ASIC vendors (LSI Logic Motorola SMOS Fujitsu others) into Atmel ASICs. These designs have been optimized speed gate count modified logic memory, replicated pin-for-pin compatible, drop-in replacement.
FPGA Conversions
Atmel successfully translated existing FPGA/PLD designs from most major vendors (Xilinx Actel AlteraTM, AMDand Atmel) into Atmel ASICs. There four primary reasons convert from FPGA/PLD ASIC. Conversion high volume devices single combined design cost effective. Performance often optimized speed power consumption. Several FPGA/PLDs combined onto single chip minimize cost while reducing on-board space requirements. Finally, situations where FPGA/PLD used fast cycle time prototyping, ASIC provide lower cost answer long-term volume production.
Macro Cores
AVR(8-bit RISC) Microcontroller (8515)
RISC Microcontroller true 8-bit RISC architecture, ideally suited embedded control applications. offered gate level, soft macro ATL35 family. supports powerful instructions. pre-fetches instruction during prior instruction execution, enabling execution instruction clock cycle. Fast Access RISC register file consists general purpose working registers. These registers eliminate data transfer delay traditional program code intensive accumulator architectures. incorporate program memory (ROM) data memory (SRAM). Also included several optional peripherals: UART, 8-bit timer/
OakDSPCoreAtmel's embedded OakDSPCore 16-bit, generalpurpose low-power, low-voltage high-speed Digital Signal Processor (DSP). designed mid-to-high-end telecommunications consumer electronics applications, where lowpower portability major requirements. Among applications supported digital cellular telephones, fast modems, advanced facsimile machines hard disk drives. available core Atmel's Gate Array cell library, utilized
ATL35 GateArray/Embedded Array-1.4-03/02
engine DSP-based Gate Array/Embedded Array. specified with several levels modularity SRAM, ROM, blocks, allowing efficient DSP-based Gate Array/Embedded Array development. aimed achieving best cost-performance factor given (small) silicon area. element system-on-chip, takes into account such requirements program size, data memory size, glue logic power management. core consists three main execution units operating parallel: Computation/Bit-Manipulation Unit (CBU), Data Addressing Arithmetic Unit (DAAU) Program Control Unit (PCU). Core also contains SRAM addressing units, Program Control Logic (PCL). other peripheral blocks, which application specific, defined part user-specific logic implemented around core same silicon die. enhanced general microprocessor functions meet most application requirements.
programming model instruction aimed straightforward generation efficient compact code.
LodeDSPCore
LodeTMDSPCore currently development (12/97) will offered ATL35 series arrays embedded core. Lode advanced, 16-bit Digital Sign gned performance digital cellular, speech voice communications applications. Lode core architecture efficiently performs baseband functions speech compression, forward error correction, modem functions required digital cellular standards. Lode first general-purpose that provides multiplier-accumulators (MACs) that reduce power consumption effectively cutting cycle times half. Lode's suite user-friendly development tools easy learn, thus accelerating time takes your product market.
ATL35 Gate Array/Embedded Array
ATL35 GateArray/Embedded Array-1.4-03/02
Absolute Maximum Ratings*
Operating Ambient Temperature. -55°C +125°C Storage Temperature -65°C +150°C Maximum Input Voltage: Inputs +0.5V Tolerant/Compliant. VDD5 +0.5V Maximum Operating Voltage (VDD) 3.6V Maximum Operating Voltage (VDD5 5.5V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Volt Characteristics
Applicable over recommended operating temperature voltage range unless otherwise noted. Symbol Parameter
Operating Temperature Supply Voltage High-level Input Current CMOS Low-level Input Current High-impedance State Output Current Output Short-circuit Current PO11 CMOS High-level Input Voltage CMOS Schmitt CMOS Low-level Input Voltage CMOS Schmitt VHYS Hysteresis High-level Output Voltage PO11 Low-level Output Voltage CMOS Schmitt PO11 (min) -500 (min) 0.7V 0.9V 0.1V PO11 VSS, (max), pull-up VOUT VDD, (max) VOUT VSS, (max) 0.7V 0.475VDD 0.7V 0.3V 0.325VDD 0.3V VSS, (max)
Buffer
CMOS
Test Condition
Units
VDD, (max)
ATL35 GateArray/Embedded Array-1.4-03/02
Absolute Maximum Ratings*
Operating Ambient Temperature. -55°C +125°C Storage Temperature -65°C +150°C Maximum Input Voltage: Inputs +0.5V Tolerant/Compliant. VDD5 +0.5V Maximum Operating Voltage (VDD) 3.6V Maximum Operating Voltage (VDD5 5.5V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Volt Characteristics
Applicable over recommended operating temperature voltage range unless otherwise noted. Symbol Parameter
Operating Temperature Supply Voltage High-level Input Current CMOS Low-level Input Current High-impedance State Output Current Output Short-circuit Current PO11 CMOS, LVTTL High-level Input Voltage CMOS/TTL-level Schmitt CMOS Low-level Input Voltage CMOS/TTL-level Schmitt VHYS Hysteresis High-level Output Voltage PO11 Low-level Output Voltage TTL-level Schmitt PO11 (min) -500 (min) 0.7VDD 0.9VDD 0.1VDD PO11 (max), pull-up VOUT VDD, (max) VOUT VSS, (max) 0.475V 0.325V VSS, (max)
Buffer
CMOS
Test Condition
Units
VDD, (max)
ATL35 Gate Array/Embedded Array
ATL35 GateArray/Embedded Array-1.4-03/02
Absolute Maximum Ratings*
Operating Ambient Temperature. -55°C +125°C Storage Temperature -65°C +150°C Maximum Input Voltage: Inputs +0.5V Tolerant/Compliant. VDD5 +0.5V Maximum Operating Voltage (VDD) 3.6V Maximum Operating Voltage (VDD5 5.5V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Volt Characteristics
Applicable over recommended operating temperature voltage range unless otherwise noted. Symbol Parameter
VDD5 Operating Temperature Supply Voltage Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current PO11V PICV, PICV5 High-level Input Voltage CMOS/TTL Level Schmitt PICV, PICV5 Low-level Input Voltage CMOS/TTL Level Schmitt VHYS Hysteresis CMOS/TTL Level Schmitt PO11V High-level Output Voltage PO11V5 Low-level Output Voltage PO11V, PO11V5 -1.7 -1.7 0.7VDD 0.7VDD5
Buffer
Tolerant Compliant CMOS CMOS PO11V
Test Condition
Units
VDD, (max) VSS, (max) VSS, (max), pull VDD, (max) VSS, (max) 0.475VDD
0.5VDD 0.325VDD
ATL35 GateArray/Embedded Array-1.4-03/02
Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bi-Directional Test Condition 3.3V 3.3V 3.3V Units
Buffers
output drive (2mA 24mA) slew rate control Pullup/Pulldown/Keeper
Timing Derating Factors
Cell timing generated from comprehensive transistor level circuit simulation over temperature, voltage, process, loading, input slew rate. Cell Library section includes pin-to-pin timings. Delays represented mx+b form, where intrinsic delay through cell (zero load), output load load factor. delays expressed nanoseconds. Load factors nanoseconds picofarad output buffers nanoseconds unit load internal cells. unit load channel channel transistor gate. Capacitance numbers under nominal condition Volt, temperature 25°C, nominal process). hold times worst case numbers military environment (3.0 Volts, 125°C, worst case process). Timings measured from rising falling edge data (50% rising edge clock (50% VDD). hold times negative, value zero. Simulation libraries contain individual derating each cell providing most accurate delay numbers possible. Timing numbers cell library section used estimation comparison purposes under nominal conditions. tables below show total derating factors commercial, industrial military environments. Note that timing numbers cell library should used rough approximation relative comparison only. Atmel's simulation tools contain more sophisticated timing models.
ATL35 Volt Process Derating Factors
Best Case 0.672 Worst Case 1.412
ATL35 Volt Combined Derating Factors
Voltage, Temperature, Process
Conditions Commercial Industrial Military (3.0 Volts Volts) (0°C 70°C) (3.0 Volts Volts) (-40°C 85°C) (3.0 Volts Volts) (-55°C 125°C) Best Case 0.61 0.56 0.54 Worst Case 1.64 1.68 1.80
Source CMOS Power Dissipation
There primary components standard CMOS power consumption. major portion power dissipation related charging discharging gate interconnect capacitance during switching. directly varies with capacitance load, square supply voltage, frequency V**2 Quiescent stand-by power dissipation comes primarily from parasitic leakage paths. through reverse bias junctions inherent CMOS second subthreshold source drain current transistors their state.
Atmel provides methodology calculating both components separately. power factors given following calculations accurate within percent.
1-10
ATL35 Gate Array/Embedded Array
ATL35 GateArray/Embedded Array-1.4-03/02
Power Calculation
Switching power divided into sequential cell (FF) power, combinational cell power, POWER. Flip flops latches have internal clock buffering, therefore dissipate power when clock active, even data changing. This shown below (duty cycle). other power numbers assume 100% duty cycle, that cell output switches every time input switches.
Duty Cycle 100% Peak Current (Ip) Load Factor Gates 16-30 0.31 uW/MHz uW/MHz uW/MHz/pF Units
Power Estimation worksheet included Section Design, Appendix equations details. recommended that ASIC have least power ground each peak current.
Power Ground Pins
Simultaneous switching outputs result large transient currents. Since board, package chip ground wiring finite impedance, this current produces transient increase local ground voltage known ground bounce. buffer site containing input buffer experiences sufficient ground bounce, transition input erroneously detected buffer. Ground bounce also adversely affect switching performance both input output buffers.
Several steps taken help alleviate ground bounce problems. only minimum drive buffers necessary achieve required output switching speeds output drive Atmel buffers programmable increments from 2-24 Adding extra power ground pins will lessen ground bounce. Power ground distribution provided dedicated pins each corner die. Additional power ground pins placed location side. dedicated corner pins supply power ground both ring internal array. Corner pins either power ground. custom package designs, these pins connect inductance resistance power ground paths external package pins. maximum, power ground together handle simultaneous switching output current. example, buffers would require minimum power ground pin. Power ground pins supply both input output buffers, separate input output buffers specified. Generally, simultaneously switching inputs outputs should grouped separately with additional supply pins between groups. Choice input buffers also impacts number power ground pins required. buffer with switching point 2.0V more susceptible ground bounce noise than CMOS buffer. Unless other requirements dictate level inputs, CMOS buffer switching 2.5V will offer more noise immunity. excessively noisy environments, Schmitt Trigger input available. orou solution ground bounce problem requires simulation board, package chip together, with accurate models inductance, resistance capacitance power distribution buffer loads. Atmel will provide transistor level simulation results specific applications required.
Power/Ground Rules
simultaneous switching current between power ground pins maximum allowed Group inputs together outputs together, with supply pins between groups Group bi-directional buffers with common Tri-Statecontrol
Fixed Power/Ground Pads
corner pins fixed power ground.
other pins fully programmable
1-11
ATL35 Gate Array/Embedded Array
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