SST65P542R SST65P542RRemote Controller FEATURES: 8-bit

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SST65P542R SST65P542RRemote Controller FEATURES: 8-bit

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Remote Controller
SST65P542R
SST65P542RRemote Controller
FEATURES:
8-bit Core Enhanced 6502 Microprocessor Megacell emulating reduced 6805 instruction Typical Oscillator Clock Frequency Maximum Oscillator Clock Frequency Voltage Operation: 2.2-3.2V Re-configurable General Purpose pins SuperFlash Memory KByte Flash Memory Byte sectors SoftPartition 100,000 endurance cycles (typical) years data retention Fast Write: Chip-Erase: (typical) Sector-Erase: (typical) Byte-Program: (typical) In-Application Programming (IAP) External Host Programming Mode Programmer Support JEDEC Standard Command Sets Byte On-Chip SRAM In-System Programming (ISP) Support through Firmware Input Learning Mode Carrier Modulator Transmitter Supports Baseband, Pulse Length Modulator (PLM), Frequency Shift Keying (FSK) Core Timer Counter 14-stage multifunctional ripple counter Includes timer overflow, POR, RTI, External Reset Power Reset Pins Power Management Hardware enable bits programmable software entering STOP IDLE modes Package Available 28-lead SOIC
PRODUCT DESCRIPTION
SST65P542R member SST's 8-bit application specific microcontroller family targeted remote controller applications. SST65P542R microcontroller provides high functionality infrared remote controller products. device offers flexibility store different remote control configurations controlling multiple appliances. configurations either programmed factory during manufacturing process downloaded through firmware. Using SST's SuperFlash nonvolatile memory technology, SST65P542R enhances functionality reduces cost conventional universal remote controller devices integrating multiple functions remote controller system single chip solution. built-in ports directly drive indicators. transmitter port drives signals infrared transmitter, which, turn, remotely controls appliances. SoftPartition architecture allows seamless flash memory partitioning program code, protocol tables, user data small granularity Byte sectors. small sector size fast Write capability device greatly decreases time power when altering contents flash memory. highly reliable, patented SuperFlash technology provides significant advantage over conventional flash memory technology. These advantages translate into significant cost saving reliability benefits customers.
©2002 Silicon Storage Technology, Inc. S71170-04-000 2/02
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. In-Application Programming, IAP, SoftPartition trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Remote Controller SST65P542R
TABLE CONTENTS
PRODUCT DESCRIPTION LIST FIGURES LIST TABLES. FUNCTIONAL BLOCKS Functional Block Diagram ASSIGNMENTS. Descriptions REGISTERS MEMORY ORGANIZATION Registers SRAM. SuperFlash Memory. PARALLEL INPUT/OUTPUT PORTS. Port Port Port FLASH MEMORY PROGRAMMING In-Application Programming. 5.1.1 Chip-Erase 5.1.2 Sector-Erase 5.1.3 Byte-Program External Host Programming Mode 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 External Host Mode Read Operation External Host Mode Write Operation External Host Mode Byte-Program Operation External Host Mode Chip-Erase Operation. External Host Mode Sector-Erase Operation Operation Status Detection Program Timer Method Operation Status Detection RY/BY# Method Exiting External Host Programming Mode Flash Read Protection
RESET External Reset External Power Reset. Internal Power-on Brown-out Reset Watchdog Timer Reset Illegal Address Reset
©2002 Silicon Storage Technology, Inc. S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet INTERRUPTS Software Interrupt. External Interrupts Interrupt Core Timer Interrupt. OPERATION MODES. User Mode Learning Mode PERIPHERALS OTHERS Core Timer Carrier Modulator Transmitter (CMT). Clock Input Options Crystal/Ceramic Resonator External Clock Drive. 10.0 POWER SAVING MODES 10.1 STOP Mode 10.2 IDLE Mode 11.0 ELECTRICAL SPECIFICATION 11.1 Absolute Maximum Stress Ratings 11.2 Reliability Characteristics 11.3 Specifications. 11.4 Electrical Characteristics 11.5 Electrical Characteristics 12.0 PRODUCT ORDERING INFORMATION 12.1 Valid Combinations 13.0 PACKAGING DIAGRAMS
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
LIST FIGURES
FIGURE 2-1: Assignments 28-lead SOIC FIGURE 3-1: Memory Map. FIGURE 4-1: Port Interrupt Pull-Up Options FIGURE 6-1: Reset Block Diagram FIGURE 9-1: Using Crystal FIGURE 9-2: External Clock Drive FIGURE 10-1: Stop Mode Idle Mode. FIGURE 11-1: External Host Programming Mode Setup Cycle Timing Diagram. FIGURE 11-2: External Host Programming Mode Read Cycle Timing Diagram FIGURE 11-3: External Host Programming Mode Write Cycle Timing Diagram FIGURE 11-4: External Host Programming Mode Chip-Erase Timing Diagram FIGURE 11-5: External Host Programming Mode Sector-Erase Timing Diagram FIGURE 11-6: External Host Programming Mode Byte-Program Timing Diagram FIGURE 11-7: Input/Output Reference Waveform FIGURE 11-8: Test Load Example FIGURE 11-9: Byte-Program Command Sequence External Host Programming Mode FIGURE 11-10: Wait Options External Host Programming Mode. FIGURE 11-11: Chip-/Sector-Erase Command Sequence External Host Programming Mode
LIST TABLES
TABLE 2-1: Descriptions TABLE 3-1: Register Descriptions Definitions TABLE 3-5: Interrupt/Reset Sector. TABLE 5-1: SFFR Commands TABLE 5-2: External Host Programming Mode Descriptions. TABLE 5-3: External Host Programming Mode Assignment TABLE 5-4: Software Command Sequence. TABLE 8-1: Assignment Different Operation Modes TABLE 11-1: Reliability Characteristics TABLE 11-2: Recommended Operating Conditions TABLE 11-3: Electrical Characteristics TABLE 11-4: Control Timing TABLE 11-5: External Host Programming-Mode Timing Parameters
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
FUNCTIONAL BLOCKS
FUNCTIONAL BLOCK DIAGRAM
Core SuperFlash Memory Port Carrier Modulator Transmitter Port Port
Interrupt Control
IRQ#
352K
Timer/Counter Interrupt Real-Time Counter Core Timer Counter Watchdog Timer
B1.8
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
ASSIGNMENTS
28-lead SOIC View
28-soic P01.5
OSC1 OSC2 IRQ# RST# LPRST#
FIGURE
2-1: ASSIGNMENTS 28-LEAD SOIC
Descriptions
TABLE
Symbol PA[7:0] PB[7:0] PC[3:0] LPRST#
2-1: DESCRIPTIONS
Type I/O1 Name Functions Port state Port software programmable every line configured input during reset. Port state Port software programmable every line configured input during reset. Each line contains programmable interrupt/pull-up keyscan. Port Every Port high-current state software programmable. lines configured inputs during reset. IRO: Suitable driving biasing logic, high-current source sink output carrier modulator transmitter subsystem. Default state after reset. Low-Power Reset: active-low pin, LPRST# function sets low-power reset mode. Once device low-power reset mode, held reset with processor clocks crystal oscillator halted. internal Schmitt trigger included LPRST# improve noise immunity. Reset: setting RST# low, device reset default state. internal Schmitt trigger included RST# improve noise immunity. Oscillator 1,2: These pins interface with external oscillator circuits. crystal resonator, ceramic resonator, external clock signal used. Interrupt Request: IRQ# negative edge-sensitive triggered. internal Schmitt trigger included IRQ# improve noise immunity. Power Supply: Supply Voltage (2.2-3.2V) Ground: Circuit ground. reference)
T2-1.14
RST# OSC1 OSC2 IRQ#
Input, Output
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
REGISTERS MEMORY ORGANIZATION
SST65P542R total KByte addressable memory space. memory located Figure 3-1. on-chip memory consists Bytes registers, Bytes SRAM, KByte user flash memory Bytes user vectors.
0180H Reserved 3FEFH Reset 3FF0H 3FF1H Reserved Bytes SRAM Registers
0000H 001FH 0020H
017FH 0180H
BFFFH C000H BFFFH User Memory Sectors (128 Bytes sector)
Flash Memory (128 sectors)
16,256 Bytes
FFF6H Core Timer Vector (High Byte) FFF7H FFF8H FFF9H FFFAH FFFBH FFFCH FFFDH FFFEH FFFFH Core Timer Vector (Low Byte) Vector (High Byte) Vector (Low Byte) IRQ/Port Vector (High Byte) IRQ/Port Vector (Low Byte) Vector (High Byte) Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte)
Flash Memory Read Protection
FF80H FF81H
FF7FH FF80H User Vector FFFFH
Reserved FFF5H FFF6H
Reset Interrupt Vectors
FFFFH
F02.9
FIGURE
3-1: MEMORY
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Registers
Bytes registers occupy address locations from 0000H 001FH that include general purpose registers, SuperFlash Function Register, on-chip peripheral control registers. TABLE
Symbol1 PORTA PORTB PORTC DDRA
3-1: REGISTER DESCRIPTIONS
Description Port Data Register Port Data Register Port Data Register Reserved Port Data Direction Register Port Data Direction Register Port Data Direction Register Reserved Core Timer Control Status Register Core Timer Counter Register Port Interrupt Control Register SuperFlash Function Register Port Pull-up Control Register Control Register Reserved Reserved Carrier Generator High Data Register Carrier Generator Data Register Carrier Generator High Data Register Direct Address 0000H 0001H 0002H 0003H 0004H DDRA7
DEFINITIONS
Address, Symbol DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Reset Value2,3
DDRA6
DDRB
0005H
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRC
0006H
DDRC3
DDRC2
DDRC1
DDRC0
CTSCR
0007H 0008H
CTOF
RTIF
TOFE
RTIE
TOFC
RTFC
CTCR
0009H
CTD7
CTD6
CTD5
CTD4
CTD3
CTD2
CTD1
CTD0
PBIC
000AH
INPRB7
INPRB6
INPRB5
INPRB4
INPRB3
INPRB2
INPRB1
INPRB0
SFFR
000BH
PREN
MEREN
SEREN
PROG
MERA
SERA
PBPUC
000CH
CWTC CHR1
000DH 000EH 000FH 0010H
IROLN
CMTPOL
CWT_EN
00000001b 00UUUUUUb
CLR1
0011H
IROLP
00UUUUUUb
CHR2
0012H
00UUUUUUb
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet TABLE
Symbol1 CLR2
3-1: REGISTER DESCRIPTIONS
Description Carrier Generator Data Register Modulator Control Status Register Modulator Data Register Modulator Data Register Modulator Data Register Power Saving Control Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Watchdog Timer Reset Register Direct Address 0013H
DEFINITIONS (CONTINUED)
Address, Symbol Reset Value2,3 00UUUUUUb
MCSR
0014H
DIV2
EIMSK
EXSPC
BASE
MODE
EOCIE
MCGEN
MDR1
0015H
MB11
MB10
SB11
SB10
UUUUUUUUb
MDR2
0016H
UUUUUUUUb
MDR3
0017H
UUUUUUUUb
PSCR
0018H
STOP
10000011b
CWTC
0019H 001AH 001BH 001CH 001DH 001EH 001FH 3FF0H
CWT_CLR
T3-1.8
reserved bits unaffected reset These registers reset either external internal reset.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet PORT Data Register (PORTA)
Location 0000H Reset Value
Symbol PA[7:0]
Function Port data register These bits both reading writing. Write data this register will output data port pins when it's output mode. pins input mode, only output data register updated, port pins tri-stated. Reading data from this register will read state port pins when input mode. pins output mode, reads output data register. Table details. detailed explanation each parallel port, please refer Section 4.0, "Parallel Input/Output Ports" page
PORT Data Register (PORTB)
Location 0001H Reset Value
Symbol PB[7:0]
Function Port data register These bits both reading writing. Writing data this register will output data port pins when it's output mode. pins input mode, only output data register updated, port pins tri-stated. Reading data from this register will read state port pins when input mode. pins output mode, reads output data register. Table details.
PORT Data Register (PORTC)
Location 0003H DDRC3 DDRC2 DDRC1 DDRC0 Reset Value
Symbol PC[3:0]
Function Port data register These bits both reading writing. Writing data this register will output data port pins when it's output mode. pins input mode, only output data register updated, port pins tri-stated. Reading data from this register will read state port pins when input mode. pins output mode, reads output data register. Table details. 3-2: FUNCTIONS
DDRA, DDRB, DDRC
TABLE
Access Write Write Read Read
GENERAL PURPOSE
Mode Input Output Input Output Functions Data written into output data register. Data written into output data register output pins. state read output data register read
T3-2.0
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet PORT Data Direction Register (DDRA)
Location 0004H DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Reset Value
Symbol DDRA[7:0]
Function Port data direction register These bits both reading writing. Table details. Port input Port output
PORT Data Direction Register (DDRB)
Location 0005H DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 Reset Value
Symbol DDRB[7:0]
Function Port data direction register These bits both reading writing. Table details. Port input Port output
PORT Data Direction Register (DDRC)
Location 0006H Reset Value
Symbol DDRC[3:0]
Function Port data direction register These bits both reading writing. Table details. Port input Port output
PORT Interrupt Control Register (PBIC)
Location 000AH INPRB7 INPRB6 INPRB5 INPRB4 INPRB3 INPRB2 INPRB1 INPRB0 Reset Value
Symbol INPRB[7:0]
Function Port interrupt control bits Interrupt enabled Interrupt disabled
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet PORT Pull-up Control Register (PBPUC)
Location 000CH Reset Value
Symbol PU1,PU0
Function Port pull-up control bits. following table shows pull-up strength. Defaults strong pull-up when reset. 3-3: PULL-UP CONTROL DESCRIPTION
Pull-up pull-up Port Weak pull-up each Port Weak pull-up each Port Strong pull-up each Port bit1
T3-3.1
TABLE
Default value after Power-on Reset
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet Core Timer Control Status Register (CTCSR)
Location 0008H CTOF RTIF TOFE RTIE TOFC RTFC Reset Value
Symbol CTOF
Function Core timer overflow bit. CTOF real-only status bit, this when 8-bit ripple counter rolls over from 00H. Writing this effect. Reset clears CTOF. CTOF zero writing TOFC. Real-time Interrupt bit. RTIF read-only status bit. Writing effect this bit. Reset clears RTIF. real time interrupt circuit consists divider one-of-four selector. input clock frequency that drives circuit E/212 with three additional divider stages that allows maximum interrupt period internal peripheral clock rate 2.048 MHz. Writing RTFC clears RTIF. When output chosen (one-of-four selector) stage goes active.
RTIF
TOFE
Timer overflow enable bit. TOFE statuses both read write. Reset clears this bit. CTOF timer overflow occurs. CTOF interrupt request generated
RTIE
Real time interrupt enable bit. RTIE status both read write. Reset clears this bit. RTIF set. RTIF interrupt request generated.
TOFC
Timer overflow flag clear bit. This writing only. Writing zero effect CTOF bit. This always reads zero. When written this bit, CTOF cleared.
RTFC
Real time interrupt flag clear bit. This writing only. Writing zero effect RTIF bit. This always reads zero. When written this bit, RTIF cleared.
RT[1:0]
Real time interrupt rate select bit. These bits select four taps from interrupt logic. Table 3-4. Reset sets these bits, which selects lowest periodic rate gives maximum. Care should taken when altering timeout period imminent uncertain. should cleared before changing taps. selected modified during cycle which counter switching, RTIF could missed additional could generated. 3-4:
Rate
TABLE
16ms
RATES
4.096 OSCILLATOR, PRESCALER=1
Minimum Rates (215-212)/E (216-213)/E (217-214)/E (218-215)/E 14ms 28ms 56ms 112ms Maximum Rates (215)/E (216)/E (217)/E (218)/E 16ms 32ms 64ms 128ms
T3-4.2
RT1-RT0 212/E1 213/E 214/E 215/E
internal peripheral clock frequency FOSC/2
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet Core Timer Counter Register (CTCR)
Location 0009H CTD7 CTD6 CTD5 CTD4 CTD3 CTD2 CTD1 CTD0 Reset Value
Symbol CTD[7:0]
Function core timer counter register This read only status register which contains current value 8-bit ripple counter. This counter clocked clock (E/4) used various functions, including software input capture. Extended time achieved using timer overflow function increment variable simulate 16-bit counter.
SuperFlash Function Register (SFFR)
Location 000BH PREN MEREN SEREN PROG MERA SERA Reset Value
Symbol PREN
Function Byte program enable bit. Disable byte program. Enable byte program.
MEREN
Mass (chip) program enable. Disable mass (chip) erase program. Enable mass (chip) erase program.
SEREN
Sector program enable. Disable sector erase program. Enable sector erase program.
PROG
Byte program control bit. performs byte program Performs byte program.
MERA
Mass (chip) program active bit. performs chip program Performs chip program.
SERA
Sector program active bit. performs sector program. Performs sector program.
Therefore, when SFFR=22H, will perform Sector-Erase, SFFR=44H, will perform ChipErase, SFFR=88H, will perform Byte-Program. detailed explanation flash control, please refer Section 5.1, "In-Application Programming" page
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet Watchdog Timer Control Register (CWTC)
Location 000DH CWT_EN Reset Value
Symbol CWT_EN
Function watchdog timer enable bit. watchdog timer enabled. watchdog timer disabled.
Watchdog Timer Reset Register (CWTR)
Location 3FF0H
CWT_CLR
Reset Value
Symbol CWT_CLR
Function This writing only. detail explanation Watchdog Timer Reset, please refer Section Write zero this will clear watchdog timer. Write this effect. Read this will always returns one.
Carrier Generator High Data Register1 (CHR1)
Location 0010H IROLN CMTPOL Reset Value 00UUUUUUb
Symbol IROLN
Function latch control bit. Reading IROLN reads state latch. Writing IROLN updates latch with data being written negative edge internal processor clock (FOSC/2). latch clear reset. Writing CHR1 update IROLN will also update primary carrier high data value. addition, writing CHR1 update IROLN will update polarity bit. should contain data CMTPOL polarity bit. output polarity bit. This controls polarity output (IRO). output active high. output active low.
CMTPOL
PH[5:0]
Primary carrier high time data values. When selected, these bits contain number input clocks required generate carrier high time periods. When operating timer mode, CHR1 CLR1 always selected. When operating mode, CHR1, CLR1 CHR2, CLR2 alternately selected under control modulator. primary carrier high time values undefined reset. These bits must written non-zero values that before carrier generator enabled avoid spurious results.
CHR1 used both reading writing. Note:"U" indicates that unaffected after reset.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet Carrier Generator Data Register1 (CLR1)
Location 0011H IROLP Reset Value 00UUUUUUb
Symbol IROLP
Function latch control bit. Reading IROLP reads state latch. Writing IROLP updates latch with data being written negative edge internal processor clock (FOSC/2). Writing CLR1 update IROLP will also update primary carrier data value. Care should taken that bits data written CHR1 CLR1. Primary carrier time data values. function these bits same PH[5:0].
PL[5:0]
Carrier Generator High Data Register2 (CHR2)
Location 0012H Reset Value 00UUUUUUb
Symbol SH[5:0]
Function Secondary carrier high time data values. When selected, these bits contain number input clocks required generate carrier high time periods. When operating time mode, CHR2 CLR2 never selected. When operating mode, CHR2, CLR2 CHR1, CLR1 alternately selected under control modulator. secondary carrier high time values undefined reset. These bits must written nonzero values before carrier generator enabled when operating mode.
Carrier Generator Data Register2 (CLR2)
Location 0013H Reset Value 00UUUUUUb
Symbol SL[5:0]
Function Secondary carrier time data values. function these bits same SH[5:0].
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet Modulator Control Status Register (MCSR)
Location 0014H DIV2 EIMSK EXSPC BASE MODE EOCIE MCGEN Reset Value
Symbol
Function modulation cycle status bit. This read only. when match occurs between contents space period register SREG down counter. cycle, counter initialized with contents mark period buffer, MBUFF SREG loaded with space period buffer SBUFF. This flag cleared reading MCSR followed access MDR2 MDR3. cleared reset. current modulation cycle progress. modulator cycle occurred. Divide scaler bit. divide-by-two prescaler causes clocked rate, when times rate enabled FOSC disabled. Since this double buffered, this should during transmission. divide-by-two prescaler disabled. divide-by-two prescaler enabled. External Interrupt Mask bit. This used mask keyscan interrupts. This cleared reset. keyscan interrupts enabled. keyscan interrupts disabled. Extended Space Enable bit. detailed description extended space operation, please refer 65P542R Programming User's Manual. Extended space disabled. Extended space enabled Baseband Enable bit. This disables carrier generator forces carrier output high generation baseband protocols. When BASE cleared, carrier generator enabled carrier output toggles frequency determined values stored carrier data registers. This cleared reset. This double buffered should written during transmission. Baseband disabled. Baseband enabled. Mode select bit. This cleared reset. This double buffered should written during transmission. operates Time mode. operates mode. Interrupt enable bit. Interrupt request will generated when EOCIE set. Otherwise, interrupt will generated interrupt disabled. interrupt enabled. Modulator carrier generator enable bit. this will initialize carrier modulator will enable clocks. Once enabled, carrier generator modulator will function continuously. this zero, current modulator cycle will allowed expire before carrier modulator clocks disabled modulator output forced low. prevent spurious operation, user should initialize data control registers before enabling system. This cleared reset. bits except used both reading writing. Modulator carrier generator enabled.
DIV2
EIMSK
EXSPC
BASE
MODE
EOCIE
MCGEN
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet Modulator Data Register (MDR1)
Location 0015H MB11 MB10 SB11 SB10 Reset Value UUUUUUUUb
Symbol MB[11:8] SB[11:8]
Function MBUFF high bits. SBUFF high bits.
These bits used both reading writing. Modulator Data Register (MDR2)
Location 0016H Reset Value UUUUUUUUb
Symbol MB[7:0]
Function MBUFF lower bits. These bits used both reading writing.
Modulator Data Register (MDR3)
Location 0016H Reset Value UUUUUUUUb
Symbol SB[7:0]
Function SBUFF lower bits. bits used reading writing.
Power Saving Control Register (PSCR)
Location 0018H STOP Reset Value 10000011b
Symbol
Function This enable disable stop idle mode. This used both reading writing. STOP IDLE mode enable STOP IDLE mode disable.
STOP
Stop mode enable write this will make device entering stop mode EN=0 write this effect. Read returns one.
Idle mode enable write this will make device entering idle mode EN=0 write this effect. Read returns one.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
SRAM
There Bytes SRAM available. SRAM addresses start from location 0020H 017FH. stack pointer address Bytes stack beginning address location 00FFH ending 00C0H.
TABLE
3-5: INTERRUPT/RESET SECTOR
User Vectors Flash Memory Read Protection Unused Core Timer Vector (High Byte) Core Timer Vector (Low Byte) Vector (High Byte) Vector (Low Byte) IRQ/Port Vector (High Byte) IRQ/Port Vector (Low Byte) Vector (High Byte) Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte)
T3-5.5
Address Location FF80H FF81H-FFF5H FFF6H FFF7H FFF8H FFF9H FFFAH FFFBH FFFCH FFFDH FFFEH FFFFH
SuperFlash Memory
SST65P542R KByte SuperFlash EEPROM memory. memory organized sectors Bytes each. minimum erasable memory unit sector Bytes. user programmable flash memory occupies address space from C000H FF7FH. user vector area consists Bytes starting from address location FF80H FFFFH. Address FF80H flash memory read protection. There five predetermined user vectors from FFF6H through FFFFH dedicated reset interrupts. Every vector consists bytes loaded into program counter jumping interrupt service routine (ISR). Table detailed descriptions these vectors.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
PARALLEL INPUT/OUTPUT PORTS Port
Port consists eight individual pins driven data register direction register control usage these pins either inputs outputs. Port pins Input mode during Reset. Software must right direction register first before performing Read Write operation. Read operation port that output will read back data from internal latch register instead pins. details, please refer Section Port data register Port data direction register.
Port
Port pins similar Port pins except that each Port pins programmable interrupt generation option which enabled Port pins. Port pins have optional programmable pull-ups. There choice between pull-up strengths which could selected PU1. details, please refer Section 3.1, Port Interrupt Control Register Port Pull-up Control Register.
WEAK0
WEAK1
INPRB7 DDRB7
From other Port Pins
Interrupt Logic
F03.3
FIGURE
4-1: PORT INTERRUPT PULL-UP OPTIONS
Port
Port 4-bit bi-directional port (PC3-PC0). Every Port high current driving capability. Reset clears Port Data Register data direction register, thereby returning ports inputs. details, please refer Section Port data register Port data direction register.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
FLASH MEMORY PROGRAMMING In-Application Programming
SST65P542R allows "In-Application Programming" (IAP) update user code internal Kbyte SuperFlash memory. Write/Erase operations require setting enable SuperFlash Function Register (SFFR) located 000BH. following sections describe operations that performs alter contents SuperFlash Memory. detailed explanation SuperFlash Function Register, please refer Section 3.1. 5.1.1 Chip-Erase Chip-Erase operation requires MEREN MERA bits logical "1". After setting these bits, writing data address location flash memory will trigger Chip-Erase operation. idle while SST65P542R busy doing erases memory locations. 5.1.2 Sector-Erase Sector-Erase operation requires SEREN SERA bits logical "1". After setting these bits, writing data address within sector erased will erase data sector. idle while SST65P542R busy doing erase sector. 5.1.3 Byte-Program Byte-Program operation requires PREN PROG bits logical "1". After setting these bits, then writing data target address programmed. idle while SST65P542R busy doing programming byte. Refer following summary different functions.
External Host Programming Mode
external host programming mode provide programmer access 16KB embedded flash memory SST65P542R. enter external host programming mode, users must follow setup sequences pins (See Figure 11-1): RY/BY# (pin POROUT# (pin output pins. drive. Drive RST# (pin low. Drive LPRST# (pin low. Drive LPRST# (pin high after TRST. Drive PROG_RST (pin low. Drive clocks TCLKIN. each clock's rising edge provide data TDIN (pin shown Figure 11-1. data bits "11010011". Wait RY/BY# (pin POROUT# high. Drive least clocks TCLKIN. Read-protect byte set, then RY/BY# will low. Otherwise, RY/BY# will stay high. RY/BY# low, wait RY/BY# (pin high. SST65P542R external host programming mode ready embedded flash Read Write operations. SST65P542R external host programming mode ready embedded flash external host Read Write. soon RST# released `1', chip exits external host programming mode then enters user mode. 5.2.1 External Host Mode Read Operation shown Figure 11-2, Read operation needs address setup cycles data setup cycle. high transition SCLK latches high order address A[13:8] from AD[5:0] while MODE[1:0] inputs high transition SCLK latches order address A[7:0] from AD[7:0] while MODE[1:0] inputs setting signal low; high transition SCLK latches data D[7:0] AD[7:0] while MODE[1:0] reading. After reading data, external host should signal high.
TABLE
5-1: SFFR COMMANDS
Command Writes SFFR Comment Erase whole flash memory Erase sector addressed CXXXH Program data byte address CXXXH. Write data CXXXH before Byte-Program performed, Chip-Erase Sector-Erase must issued erase target programming locations.
T5-1.1
Function Chip-Erase Sector-Erase Byte-Program
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet 5.2.2 External Host Mode Write Operation shown Figure 11-3, Write operation needs address setup cycles data setup cycle. high transition SCLK latches high order address A[13:8] from AD[5:0] while MODE[1:0] inputs high transition SCLK latches TABLE
Pins 10,20
order address A[7:0] from AD[7:0] while MODE[1:0] inputs high transition SCLK latches data D[0:7] from AD[7:0] while MODE[1:0] writing. However, actual Write operation embedded flash memory occurs rising edge WE#.
5-2: EXTERNAL HOST PROGRAMMING MODE DESCRIPTIONS
Symbol AD[7:0] MODE[1:0] SLCK PROG_RST POROUT# RY/BY# LPRST# TDIN TCLKIN Type1 I/O1 Name Functions Embedded flash memory address data multiplex AD[7:0] selecting MODE[1:0] Address data selection bits external host programming mode Clock latch address data after entering external host programming mode Reset signal external host programming mode Embedded flash memory power-on reset output Embedded flash Ready/Busy output. High ready Write Enable: embedded flash memory data write enable, active Output Enable: embedded flash memory data enable, active Signal entering external host programming mode Data input entering external host programming mode This clock will latch TDIN entering external host programming mode Ground: Circuit ground reference) Power Supply: Supply voltage (3.2V)
T5-2.3
Input; Output
5.2.3 External Host Mode Byte-Program Operation This device programmed byte byte basis. Byte-Program operation consists three steps. first step three-byte load sequence Software Data Protection. second step load byte address byte data. third step internal Program operation which initiated after rising edge fourth WE#. Byte-Program operation determined using RY/BY#. commands written during Byte-Program operation will ignored. Table software command sequence, Figure 11-5 flash Byte-Program timing diagram, Figure 11-9 Byte-Program command sequence flowchart. 5.2.4 External Host Mode Chip-Erase Operation. device provides Chip-Erase operation, which allows user erase entire memory array '1's state. This useful when device must quickly erased entirely. Chip-Erase operation initiated executing six-byte Software Data Protection command sequence, last byte Sequence address 1555H with ChipErase command 10H. Chip-Erase operation begins with sixth write enable's (WE#) rising edge. Chip-Erase determined using signal RY/BY#. commands written during Chip-Erase
©2002 Silicon Storage Technology, Inc.
operation will ignored. Table software command sequence, Figure 11-4 flash Chip-Erase timing diagram, Figure 11-11 Chip-Erase command sequence flowchart. 5.2.5 External Host Mode Sector-Erase Operation Sector-Erase operation allows system erase device sector-by-sector basis. sector architecture based uniform sector size Bytes. SectorErase operation initiated executing six-byte command sequence Software Data Protection, last byte sequence sector address with Sector-Erase command 30H. address lines A[13:7] will used determine sector address. internal Erase operation begins after sixth write enable's (WE#) rising edge. End-of-Erase determined using signal BY#. commands written during Sector-Erase operation will ignored. Table software command sequence, Figure 11-5 flash Sector-Erase timing diagram, Figure 11-11 Sector-Erase command sequence flowchart.
S71170-04-000 2/02
Remote Controller SST65P542R
Data Sheet 5.2.6 Operation Status Detection Program Timer Method During Program Erase operation, programmer timer decide completion operation. When Program Erase operation started, system setup timer (for Byte-Program), TSCE (for ChipErase), (for Sector-Erase) time period. After this timer time-out, operation completed. Figure 1110 Program Timer flowchart. 5.2.7 Operation Status Detection RY/BY# Method During internal Program Erase operation, signal RY/BY# indicates status operation. When internal Program Erase operation progress, signal RY/BY# will driven low. When internal Program Erase operation completed, signal RY/BY# will driven high. device then ready next operation. Figure 11-10 Program Timer flowchart. 5.2.8 Exiting External Host Programming Mode exit external host programming mode, external host must RST# high, PROG_RST reset high. device will exit host programming enter user mode. starts execution codes User Memory Space from reset vector. TABLE 5.2.9 Flash Read Protection protect program code from piracy flash memory location 3F80H (user memory address FF80H, flash memory mapped C000H through FFFFH, Figure 3-1) evaluated internal hardware determine read protect mode state. During this evaluation period, only RY/BY# valid other pins blocked. this byte (read protect active), Chip-Erase will performed internal hardware before external host programming mode activated. While Chip-Erase could take TSCE (See Table 11-5) maximum time, users RY/BY# determine completion Chip-Erase. this byte (not read protected), flash memory visible using external host programming. During internal Program Erase operation, signal indicates status operation. When internal Program Erase operation progress, RY/BY# will driven low. When internal Program Erase operation completed, RY/BY# will driven high. device then ready next operation. Figure 11-10 Program Timer flowchart. Note: After writing flash read protection register, device needs continue power-on prior finishing programming function. programming function include Program-Verify function.
5-3: EXTERNAL HOST PROGRAMMING MODE ASSIGNMENT
MODE0=0 MODE1=0 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] Input Input Input Input Input Input MODE0=0 MODE1=1 Input Input Input Input Input Input Input Input MODE0=1 MODE1=0 Input Input Input Input Input Input Input Input MODE0=1 MODE1=1 Output Output Output Output Output Output Output Output
T5-3.1
TABLE
5-4: SOFTWARE COMMAND SEQUENCE
Write Cycle Addr1 1555H 1555H 1555H Data Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data Write Cycle Addr1 1555H 1555H 1555H Data Write Cycle Addr1 1555H 1555H Data Data
T5-4.3
Command Sequence Sector-Erase Chip-Erase Byte-Program
Write Cycle Addr1 2AAAH 2AAAH Data
Write Cycle Addr1 SAX2 1555H Data
Address format A13-A0 (Hex) Sector-Erase; uses A13-A7 address lines Program Byte address
©2002 Silicon Storage Technology, Inc. S71170-04-000 2/02
Remote Controller SST65P542R
RESET
65P542R reset from five sources: external inputs three internal restart conditions.
Data Address
Watchdog Reset Illegal Address Reset
Address
Reset Control
Internal Reset
RST#
LPRST#
4064 Clock Cycle Delay
F16.2
FIGURE
6-1: RESET BLOCK DIAGRAM 1.9-2.1V. voltage below threshold values, device will reset order protect against inadvertent Write flash memory.
External Reset
low-level input RST# causes program counter contents location FFFEH FFFFH (Reset Vector). initialized known state. Stack pointer will reset FFH. Hardware Reset highest priority input chip. internal Schmitt trigger implemented RST# input enhance noise immunity.
Watchdog Timer Reset
SST65P542R (Computer Operating Properly) watchdog timer monitoring proper operations MCU. normal operation, clearing watchdog timer executed software within preset period time avoid reaching time-out condition. clear watchdog timer, software write location 3FF0H. Watchdog Reset asserted resets when time-out condition occurs. watchdog timer disabled during external reset. enable CWT, write logical control register (000DH). Refer SST65P542R Programming User's Manual more information.
External Power Reset
LPRST# external sources reset. signal LPRST# allows into power reset mode. clocks oscillator processor halted when LPRST# held low. After LPRST# de-asserted (driven high), delay 4064 clock cycles automatically enabled wait stable crystal oscillation. This also implements internal Schmitt trigger enhance noise immunity.
Illegal Address Reset
illegal address reset generated when attempts fetch instruction from address space (0000H 001FH). Those addresses reserved registers only.
Internal Power-on Brown-out Reset
internal reset signal will reset peripheral components. Please refer Figure 6-1. When device powered internal power-up voltage 2.0-2.2V. addition, internal brown-out voltage
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
INTERRUPTS
SST65P542R accepts five sources interrupts with highest lowest priority: Software Interrupt, External Interrupts (IRQ# Port Interrupt, Core Timer Interrupt. Whenever multiple interrupt requests active same time, higher priority will serviced first. interrupts maskable except Software Interrupt which generated executing instruction. mask interrupts, interrupt mask Process Status Word (PSW). Before serving interrupt, registers pushed onto stack sequence PCL, PCH, IDX, ACC, PSW. interrupt service routine should clear source interrupt before exiting. executing instruction, stored registers popped from stack program resumes from interrupted location. external interrupts, IRQ# Port interrupts edge-sensitive asserted falling edge pins. Port Interrupt Control Register enables disables interrupts each individual port External Interrupt Mask (EIMSK) Modulator Control Status Register used mask external interrupts that lower priority interrupts such timer interrupts served. state external interrupt received during masked period preserved. When EIMSK clear, pending interrupts activate interrupt processing again. external interrupt causes load contents memory locations FFFAH FFFBH into Program Counter.
Interrupt Software Interrupt
instruction causes load contents memory locations FFFCH FFFDH into Program Counter regardless interrupt mask register. interrupt generated when cycle flag (EOC) cycle interrupt enable (EOCIE) bits modulator control status register (MCSR). This interrupt will vector interrupt service routine located address specified contents memory locations FFF8H FFF9H.
External Interrupts
Upon completion current instruction, responds interrupt request that latched internally. IRQ# must asserted (low) least TILIH (125 ns). Following completion current instruction, interrupt latch tested. both interrupt mask bit) clear interrupt request pending, interrupt service routine entered. external resistor required IRQ# input wired-AND operation.
Core Timer Interrupt
core timer 14-stage multifunctional ripple timer. User select overflow real-time interrupt setting Core Timer Control Status Register. Please timer section more details. timer interrupt causes load contents memory locations FFF6H FFF7H into Program Counter.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
OPERATION MODES
device operate different modes. Operation mode includes User mode Learning mode. definitions vary between different operation modes described Table 8-1.
Learning Mode
enter learning mode, input signal IRQ# pin, then instruction record input signal width. detail information learning mode, please refer application note Remote Controller Learning Algorithm using SST65P542R.
User Mode
user mode, embedded fetches program codes from user memory space. Please refer SST65P542R Programming User's Manual instruction sets internal programming information. TABLE
8-1: ASSIGNMENT DIFFERENT OPERATION MODES
Normal Interface Modes User Mode PB[0] PB[1] PB[2] PB[3] PB[4] PB[5] PB[6] PB[7] PA[0] PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] PC[0] PC[1] PC[2] PC[3] LPRST# RST# IRQ# OSC2 OSC1 Learning Mode PB[0] PB[1] PB[2] PB[3] PB[4] PB[5] PB[6] PB[7] PA[0] PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] PC[0] PC[1] PC[2] PC[3] LPRST# RST# IRIN OSC2 OSC1 AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] PROG_RST MODE[1] SCLK RY/BY# POROUT# TDIN MODE[0] LPRST# TCLKIN use2
T8-1.8
External Host Programming Mode1
Table description. OSC2 output, used during external host program mode.
©2002 Silicon Storage Technology, Inc. S71170-04-000 2/02
Remote Controller SST65P542R
PERIPHERALS OTHERS Core Timer
Core Timer provides following features: Real Time Interrupt (RTI) Timer Overflow watchdog timer Power-on reset (POR) Please refer SST65P542R Programming User's Manual programming information.
OSC2 OSC1
Carrier Modulator Transmitter (CMT)
SST65P542R integrates carrier modulator transmitter supporting various encoding methods. purpose this module reduce loading MCU. Three major functions performed this block: carrier generation, modulation, transmission. Please refer SST65P542R Programming User's Manual programming information. FIGURE 9-1: USING
F05a.6
CRYSTAL
EXTERNAL CLOCK SIGNAL DON'T CONNECT
OSC1
Clock Input Options
Control connections 2-lead on-chip oscillator OSC1 OSC2 pins. OSC1 input OSC2 output. crystal resonator, ceramic resonator, external clock signal drive oscillator.
OSC2
Crystal/Ceramic Resonator
crystal/ceramic oscillator circuit shown Figure 9-1. ceramic resonator instead crystal used reduce costs. recommended that resonator capacitors mounted close pins possible minimize output distortion. Crystal manufacturer, supply voltage, other factors cause circuit performance differ from application another. should adjusted appropriately each design. FIGURE
F05b.3
9-2: EXTERNAL CLOCK DRIVE
External Clock Drive
external clock source provided, OSC1 clock input OSC2 don't connect. Leave OSC2 open.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
10.0 POWER SAVING MODES
SST65P542R provides power saving modes: Stop mode Idle mode. These modes entered through setting Power Saving Control Register. Refer Section power saving control register. device recovered from STOP mode. There three conditions that will recover device from STOP mode: external IRQ#/Port interrupt (EIMSK=0), RST# external reset LPRST#. STOP will when device been brought STOP mode. interrupt mask bit) will affected.
10.1 STOP Mode
Writing logic STOP Power Saving Control Register enters STOP mode. achieve lowest possible power consumption, implementation uses STOP gate internal clock. Figure 10-1 illustration clock arrangement STOP mode. Since there clock input, internal states maintained changed including registers memory except that core timer counter bits cleared. external interrupt brought device STOP mode, other interrupts served until
10.2 IDLE Mode
Writing logic IDLE Power Saving Control Register enters IDLE mode. IDLE mode, timer still running. internal external interrupt will recover device from IDLE mode. both STOP IDLE bits '0', then STOP mode takes effect. IDLE will when device been brought IDLE mode. interrupt mask bit) will affected.
Clock Generator STOP Peripherals
IDLE
F04.2
FIGURE 10-1: STOP MODE
IDLE
MODE
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
11.0 ELECTRICAL SPECIFICATION 11.1 Absolute Maximum Stress Ratings
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Ambient Temperature Under Bias -55°C +125 Storage Temperature Voltage Ground Potential. -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+1.0V Package Power Dissipation Capability °C). 1.0W Surface Mount Lead Soldering Temperature Seconds) Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time. (Based package heat transfer limitations, devices power consumption.)
11.2 Reliability Characteristics
TABLE 11-1: RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 100+IDD Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T11-1.3
parameter measured only initial qualification after design process change that could affect this parameter.
11.3 Specifications
TABLE 11-2: RECOMMENDED OPERATING CONDITIONS
Symbol FOSC Parameter Supply Voltage Temperature Osc. Frequency
(Ta= +70°C)
Unit
T11-2.0
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
11.4 Electrical Characteristics
TABLE 11-3: ELECTRICAL CHARACTERISTICS +70°C, 2.2-3.2V,
Symbol
Parameter Supply Current without Flash Erase/Program Operation with Flash Erase/Program Operation Idle2 Stop 0°to +70°
2.75
-12.5 VDD-0.3 VDD-0.3 VDD-0.3
Unit
Ports Hi-Z Leakage current Port Port Port Input Current IRQL, RESETL, LPRSTL, OSC1 Port with Strong Pull-ups Enable (VIN 0.2xVDD) Port with Strong Pull-ups Enabled (VIN 0.8xVDD) Port with Weak Pull-ups Enable (VIN 0.2xVDD) Port with Weak Pull-ups Enabled (VIN 0.8xVDD) Output Voltage -7.5 VDD-0.4 VDD-0.4 VDD-0.8 VDD-0.5
(ILOAD OSC2 (ILOAD -500 OSC2 Output High Voltage (ILOAD -1.2 Port Port (ILOAD (ILOAD Port
Output Voltage (ILOAD Port Port (ILOAD (ILOAD Port T11-3.4
Input High Voltage Port Port Port OSC1 IRQL, RESETL, LPRSTL
Input Voltage Port Port Port OSC1 IRQL, RESETL, LPRSTL
Test conditions loading. Idle current typical, maximum MHz, 2.2V, loading.
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
11.5 Electrical Characteristics
TABLE 11-4: CONTROL TIMING
Symbol FOSC FEXT TCYC TOXOV1 TILCH1 TRL1 TILIH1 TOH,TOL1 Characteristic Frequency operation Crystal External clock Internal Operating Frequency Cycle Time Crystal Oscillator Startup Time Stop Recovery Startup Time RST# Pulse Width Interrupt Pulse Width (Edge-Triggered) OSC1 Pulse Width TCYC
T11-4.2
+70°C, 3.2V,
Unit
Guaranteed design.
TABLE 11-5: EXTERNAL HOST PROGRAMMING-MODE TIMING PARAMETERS
Symbol TAS1
Parameter Address/Data Setup Time SCLK Cycle Time Address/Data Hold Time SCLK Pulse Width High Sector-Erase Time2 Chip-Erase Time2 Byte-Program Time2 TDIN Hold Time TDIN Setup Time TCLKIN Pulse Width TCLKIN Pulse Width High Reset Time Output Enable Time Address Latch Setup Time Data Latch Setup Time Read Access Time
Units
TAH1 TCPH1 TSCE
T11-5.7
TDS1
TDPH1 TRST1 TOE1 TWES1 TWEH1 TAA1
Guaranteed design. Applies well
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
TDPH TCLKIN (pin RESET# (pin TRST LPRST# (pin PROG_RST (pin
TSCE1 Clocks
TDIN (pin RY/BY# (pin POROUT# (pin OSC1 (pin WE#/OE# (pins SCLK (pin
F06.13
Read-Protect byte set.
FIGURE 11-1: EXTERNAL HOST PROGRAMMING MODE SETUP CYCLE TIMING DIAGRAM
TCPH SCLK (pin AD[7:0] (pin 8-1)
XXXXX
A[13:8]
A[7:0]
Data
Mode[1:0] (pin (pin (pin
XXXXX
XXXXXXXXX
F07b.9
FIGURE 11-2: EXTERNAL HOST PROGRAMMING MODE READ CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
TCPH SCLK (pin
AD[7:0] (pin 8-1) Mode[1:0] (pin
A[13:8]
A[7:0]
Data/Cmd
XXXXXXX XXXX XXXXXXX XXXX
TWEH
(pin (pin
TWES
F07a.10
FIGURE 11-3: EXTERNAL HOST PROGRAMMING MODE WRITE CYCLE TIMING DIAGRAM
SIX-BYTE WRITE COMMAND CHIP-ERASE AD[7:0]
TSCE
SCLK
Mode[1:0]
RY/BY#
F08.9
FIGURE 11-4: EXTERNAL HOST PROGRAMMING MODE CHIP-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
SIX-BYTE WRITE COMMAND SECTOR-ERASE AD[7:0]
SCLK
Mode[1:0]
RY/BY# Note: Sector Address, A13-A7 used
F09.9
FIGURE 11-5: EXTERNAL HOST PROGRAMMING MODE SECTOR-ERASE TIMING DIAGRAM
FOUR-BYTE WRITE COMMAND BYTE-PROGRAM AD[7:0] Data
SCLK
Mode[1:0]
RY/BY# Note: Byte Address, A13-A0 used
F10.9
FIGURE 11-6: EXTERNAL HOST PROGRAMMING MODE BYTE-PROGRAM TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F14.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD) Input rise fall times (10% 90%)
Note: VHIGH Test VLOW Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE 11-7: INPUT/OUTPUT REFERENCE WAVEFORM
TESTER
F15.0
FIGURE 11-8: TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Start
Write data: Address: 1555H
Write data: Address: 2AAAH
Write data: Address: 1555H
Write Address Data
Wait Program (TBP, RY/BY#)
Program Completed
F11.6
FIGURE 11-9: BYTE-PROGRAM COMMAND SEQUENCE
EXTERNAL HOST PROGRAMMING MODE
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Program Timer Program/Erase Initiated
RY/BY# Polling Program/Erase Initiated
RY/BY# Wait TBP, TSCE,
Program/Erase Completed
RY/BY# High
Program/Erase Completed
F12.3
FIGURE 11-10: WAIT OPTIONS
EXTERNAL HOST PROGRAMMING MODE
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
Chip-Erase Command Sequence Load data: Address: 1555H
Sector-Erase Command Sequence Load data: Address: 1555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 1555H
Load data: Address: 1555H
Load data: Address: 1555H
Load data: Address: 1555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 1555H
Load data: Address:
Wait End-of-Erase (TSCE, RY/BY#)
Wait End-of-Erase (TSE, RY/BY#)
Chip erased FFFFH
Sector erased FFFFH
F13.7
FIGURE 11-11: CHIP-/SECTOR-ERASE COMMAND SEQUENCE
EXTERNAL HOST PROGRAMMING MODE
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
12.0 PRODUCT ORDERING INFORMATION
SST65 SSTXX Package Modifier leads Package Type SOIC Operation Temperature Commercial: +70°C Operating Frequency Function Remote Controller On-Chip SRAM Size Bytes Flash Memory Size KByte Core Sub-Block Enhanced 6502 core Voltage 2.2- 3.2V Device Family
12.1 Valid Combinations
SST65P542R-8-C-SG
©2002 Silicon Storage Technology, Inc.
S71170-04-000 2/02
Remote Controller SST65P542R
13.0 PACKAGING DIAGRAMS
7.40 7.60
10.01 10.64
Identifier
17.70 18.10 2.36 2.64 1.27
1.27
Note:
Complies with JEDEC publication MS-013 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05) Maximum allowable mold flash 0.15mm package ends, 0.25mm between leads.
28.soicSG-ILL.5
28-LEAD SMALL OUTLINE (SOIC) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71170-04-000 2/02

SST65P542R SST65P542RRemote Controller FEATURES: 8-bit

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