Description T7504 T5504 devices single-chip, fourchannel µ-law/A-
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T7504 T5504 Quad Codecs with Filters
Description
T7504 T5504 devices single-chip, fourchannel µ-law/A-law codecs with filters. These integrated circuits provide analog-to-digital digital-to-analog conversion. They provide transmit receive filtering necessary interface voice telephone circuit time-division multiplexed system. These devices available 28-pin PLCCs. T7504 also available 44-pin MQFP. T5504 differs from T7504 timing mode. T5504 operates nondelay timing mode (digital data valid when frame sync goes high), T7504 operates delayed timing mode (digital data valid clock cycle after frame sync goes high) (see Figures 6-9).
only Low-power, latch-up-free CMOS technology mW/channel typical operating power dissipation mW/channel typical powerdown dissipation Automatic master clock frequency selection 2.048 4.096 On-chip sample hold, autozero, precision voltage reference Differential architecture high noise immunity power supply rejection Flexible time-slotted interface 2.048 4.096 data rate Meets exceeds ITU-T G.711-G.712 requirements characteristics D3/D4 Agere Systems Inc.'s PUB43801) Operating temperature range: µ-law/A-law companding selectable
GSX0 VFXIN0 FILTER NETWORK
ENCODER
INTERFACE
CHANNEL
PSx0 PSx1 PSx2 PSx3 PSEP GNDD
VFROP0 VFRON0
FILTER NETWORK
DECODER
POWERDOWN CONTROL
INTERNAL TIMING CONTROL GSX1 VFXIN1 VFRO1 GSX2 VFXIN2 VFRO2 GSX3 VFXIN3 VFRO3 CHANNEL CHANNEL BIAS CIRCUITRY REFERENCE
MCLK ASEL
(MQFP ONLY) GNDA (PLCC ONLY) GNDA (MQFP ONLY)
CHANNEL
5-3579 (F).d
Figure Block Diagram 28-Pin 28-Pin PLCC
T7504 T5504 Quad Codecs with Filters
Functional Description
Four channels data input output passed through only ports, some type time-slot assignment necessary. scheme used here utilize timing modes time slots corresponding master clock frequencies either 2.048 4.096 MHz, respectively. Each device four transmit frame sync inputs, each channel. During single frame, each transmit frame sync input supplied single pulse. timing pulse indicates beginning time slot during which data that channel clocked device. During frame, transmit frame sync pulses must separated from each other more time slots. channel placed standby (low-power) mode input been There single frame sync separation input (FSEP). number negative clock edges minus that occurs while FSEP high delay clock periods) that placed between rising edge transmit frame sign falling edge used receiver sample sign bit. There must always pulse FSEP input since this input provides signal required maintain internal timing. FSEP pulse clock period less, device makes transmit edges receive sampling edges half clock period apart. entire device placed powerdown mode FSEP remains Time slot zero defined starting first rising MCLK edge after FSEP detected negative MCLK edge. T7504, MCLK negative-going edges that detect start FSEP must integer multiples eight MCLK periods apart (zero multiples allowed). Since FSEP assumed define time slot number multiples separating FSXN FSEP time-slot number. T5504, FSXN time slot nominally starts MCLK positive edge following negative edge which detects FSEP.
frequency master clock must either 2.048 4.096 MHz. Internal circuitry determines master clock frequency during powerup reset interval. Powerdown guaranteed MCLK lost unless device already powerdown mode FSEP least analog input section Figure includes onchip that used conjunction with external, user-supplied resistors vary encoder passband gain. feedback resistance (RF) should range from capacitance from ground should kept less than input signal should coupled. best performance, maximum gain this should limited less.
VFXIN CODEC FILTERS
GAIN
5-3786
Figure Typical Analog Input Section
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Information
GNDD FSEP FSx3 FSx1 FSx0 FSx2 MCLK
ASEL
GNDA0
VFxIN2
T-7504 T-5504
VFxIN0
GSx2
GSx0
VFRO2
VFRO0
GNDA2
VFRO3 GSx3 VFxIN3 GNDA3 VFxIN1 GSx1
GNDA1
VFRO1
5-3580 (F).b
Figure 28-Pin PLCC Diagram
GNDD FSEP FSx3 FSx2 FSx1 T-7504 VFRO3 VFxIN3 GSx3 GNDA3 GNDA4 VFxIN1 GSx1 VFRO1
MCLK ASEL VDDA VFxIN2 GSx2 VFRO2 GNDA2
FSx0 VDDA GNDA0 VFxIN0 GSx0 VFRO0 GNDA1
5-4770
Figure 44-Pin MQFP Diagram Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Information (continued)
Table Descriptions
Symbol PLCC MQFP VFXIN3 VFXIN2 VFXIN1 VFXIN0 GSX3 GSX2 GSX1 GSX0 VFRO3 VFRO2 VFRO1 VFRO0 [1:0] VDDA [1:0] Voice Frequency Transmitter Input. Analog inverting input uncommitted operational amplifier transmit filter input. Connect signal digitized this through resistor (see Figure Gain Transmitter. Output transmit uncommitted operational amplifier. input transmit differential filters. Connect corresponding VFXIN through resistor (see Figure Voice Frequency Receiver Output. This drive 2000 greater) loads. Type* Name/Function
GNDA4 GNDA3 GNDA2 GNDA1 GNDA0
Digital Analog Power Supplies. pins must connected circuit board. Each should bypassed ground with least capacitance close device possible. PLCC packages, serves both analog digital internal circuits. Analog Grounds. ground pins must connected circuit board.
MCLK
GNDD FSX3 FSX2 FSX1 FSX0
ASEL FSEP
Receive Data Input. data this shifted into device falling edges MCLK. Data only entered valid time slots defined relationship pulses inputs pulse FSEP input. Transmit Data Output. This remains high-impedance state except during active transmit time slots. active transmit time slot defined which pulse present inputs. Data shifted rising edge MCLK. Master Clock Input. frequency must 2.048 4.096 MHz. This clock serves clock data transfer. duty cycle required. Digital Ground. Ground connection digital circuitry. ground pins must connected circuit board. Transmit Frame Sync. This signal edge trigger must high minimum MCLK cycle. This signal must derived from MCLK. division ratio 1:256 1:512 (FSX:MCLK). Each input must have pulse present start desired active output time slot. Pulses various inputs must separated more integer multiples time slots. internal pull-down device included each FSX. A-Law/µ-Law Select. logic selects µ-law coding. logic high selects A-law coding. pull-down device included. Frame Sync Separation. pulse width this signal defines timing offset between transmit receive frames. Internally generated receive frame sync pulses delayed from corresponding transmit frame sync pulse rising edge less than FSEP pulse width negative MCLK edges. pulse width MCLK period less, transmit receive frame syncs made coincident. Loss FSEP causes device powerdown. master clock frequency 2.048 4.096 MHz, delays clock pulses allowed, respectively. Timing relationships between FSEP, FSXN, time slot given Figures 6-9.
Indicates pull-down device included this lead.
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operational sections this data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. Parameter Storage Temperature Range Power Supply Voltage Voltage with Respect Ground Maximum Power Dissipation (package limit) Symbol Tstg -0.5 Unit
Handling Precautions
Although protection circuitry been designed into this device, proper precautions should taken avoid exposure electrostatic discharge (ESD) during handling mounting. Agere employs human-body model (HBM) charged-device model (CDM) susceptibility testing protection design evaluation. voltage thresholds dependent circuit parameters used define model. industry-wide standard been adopted CDM. However, standard (resistance 1500 capacitance widely used and, therefore, used comparison purposes. threshold presented here obtained using these circuit parameters: Threshold Voltage Device T7504 T5504 Rating >2000 >2000
Electrical Characteristics
Specifications apply MCLK either 2.048 4.096 MHz, unless otherwise noted.
Characteristics
Table Digital Interface Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Input Current, Pins without Pull-down Input Current, Pins with Pull-down Output Current High-impedance State Input Capacitance Symbol Test Conditions digital inputs digital inputs -3.2 -320 digital input digital input Unit
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Electrical Characteristics (continued)
Table Power Dissipation Power measurements made MCLK 4.096 MHz, outputs unloaded. Parameter Powerdown Current Powerup Current Standby Current Symbol IDD0 IDD1 IDDS Test Conditions MCLK present, FSX[3:0] FSEP MCLK, FSX[3:0], FSEP present MCLK, FSEP present; FSX[3:0] Unit
Transmission Characteristics
Table Analog Interface Parameter Input Resistance, VFXIN Input Leakage Current, VFXIN Open-loop Voltage Gain, Open-loop Unity Gain Bandwidth, Load Capacitance, Load Resistance, Input Voltage, VFXIN Load Resistance, VFRO Load Capacitance, VFRO Output Resistance, VFRO Symbol RVFXI IBVFXI AVOL CLX1 RLX1 RLVFRO CLVFRO ROVFRO Test Conditions 0.25 VFxI 4.75 0.25 VFxI 4.75 Relative ground dBm0, 1020 code applied Partial powerdown channel under test Alternating zero µ-law code applied FSX[3:0] FSEP active, load FSEP 2000 5000 2.25 2.35 2000 3000 10000 2.65 Unit Vp-p
Output Voltage, VFRO Output Voltage, VFRO, Standby Output Leakage Current, VFRO, Powerdown Output Voltage Swing, VFRO
VORPD IOVFRO VSWR
2.25 2.35 2.15
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Transmission Characteristics (continued)
Transmission Characteristics
Unless otherwise noted, analog input dBm0, 1020 sine wave; input amplifier unity gain. digital input stream equivalent that obtained passing dBm0, 1020 sine wave through ideal encoder. output level sin(x)/x-corrected. Table Absolute Gain Parameter Symbol Encoder Milliwatt Response (transmit gain tolerance) Decoder Milliwatt Response (receive gain tolerance) Test Conditions Signal input 0.775 Vrms, µ-law A-law Measured relative 0.775 Vrms, µ-law A-law, input dBm0 1020 -0.25 0.25 Unit dBm0
-0.25
0.25
dBm0
Table Gain Tracking Parameter Transmit Gain Tracking Error Sinusoidal Input µ-Law/A-Law Receive Gain Tracking Error Sinusoidal Input µ-Law/A-Law Table Distortion Parameter Transmit Signal Distortion Symbol Test Conditions µ-law dBm0 VFXI dBm0 A-law dBm0 VFXI dBm0 µ-law dBm0 VFXI dBm0 A-law dBm0 VFXI dBm0 µ-law dBm0 VFxI dBm0 A-law dBm0 VFxI dBm0 µ-law dBm0 VFRO dBm0 A-law dBm0 VFRO dBm0 µ-law dBm0 VFRO dBm0 A-law dBm0 VFRO dBm0 µ-law dBm0 VFRO dBm0 A-law dBm0 VFRO dBm0 Hz-3400 dBm0 input, output other single frequency 3400 Hz-3400 dBm0 input, output other single frequency 3400 Transmit receive, frequencies range (300 Hz-3400 dBm0 Unit dBm0 Symbol Test Conditions dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 -0.25 -0.50 -0.25 -0.50 0.25 0.50 0.25 0.50 Unit
Receive Signal Distortion
Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion
SFDX
SFDR
dBm0
dBm0
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Transmission Characteristics (continued)
Table Envelope Delay Distortion Parameter Delay, Absolute* Delay, Relative 1600 Symbol Test Conditions 1600 Hz-600 Hz-800 Hz-1000 1000 Hz-1600 1600 Hz-2600 2600 Hz-2800 2800 Hz-3000 1600 Hz-1000 1000 Hz-1600 1600 Hz-2600 2600 Hz-2800 2800 Hz-3000 time slot/channel time slot/channel 1600 Unit
Delay, Absolute* Delay, Relative 1600
Round Trip Delay, Absolute*
DRTA
Varies function time slots chosen.
Overload Compression Figure shows region operation encoder signal levels above reference input power dBm0).
FUNDAMENTAL OUTPUT POWER (dBm)
ACCEPTABLE REGION
FUNDAMENTAL INPUT POWER (dBm)
5-3586
Figure Overload Compression Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Transmission Characteristics (continued)
Table Noise Parameter Transmit Noise µ-Law Transmit Noise A-Law Receive Noise µ-Law Receive Noise A-Law Noise, Single Frequency kHz-100 Power Supply Rejection Transmit Symbol PSRX Test Conditions Input amplifier gain code alternating positive negative zero code A-law positive VFXIN Vrms, measurement VFRO, mVrms: kHz-4 kHz-50 code positive mVrms: kHz-4 kHz-25 kHz-50 dBm0, Hz-3400 input code applied: 4600 Hz-7600 7600 Hz-8400 8400 Hz-50 Unit dBrnC0 dBrnC0 dBm0p dBrnC0 dBm0p dBm0
Power Supply Rejection Receive
PSRX
Spurious Out-of-Band Signals VFRO Relative Input
Table Receive Gain Relative Gain 1.02 Frequency (Hz) Below 3000 3140 3380 3860 4600 above -0.150 -0.570 -0.885 ±0.04 ±0.04 -0.58 -10.7 0.150 0.150 0.010 -9.4 Unit
Table Transmit Gain Relative Gain 1.02 Frequency (Hz) 16.67 3000 3140 3380 3860 4600 above -1.8 -0.150 -0.570 -0.885 -0.5 ±0.04 ±0.04 -0.58 -10.7 0.150 0.150 0.010 -9.4 Unit
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Transmission Characteristics (continued)
Table Interchannel Crosstalk (Between Channels) (See note below.) Parameter Transmit Receive Crosstalk dBm0 Transmit Levels Receive Transmit Crosstalk dBm0 Receive Levels Transmit Transmit Crosstalk dBm0 Transmit Levels Receive Receive Crosstalk dBm0 Receive Levels Symbol CTXX-RY Test Conditions Hz-3400 idle code channel under test; dBm0 into other single channel Hz-3400 VFXIN Vrms channel under test; dBm0 code level other single channel Hz-3400 dBm0 applied single channel VFXIN except channel under test, which VFXIN Vrms Hz-3400 dBm0 code level single channel except channel under test, which idle code applied Unit
CTRX-XY
CTXX-XY
CTRX-RY
Table Intrachannel Crosstalk (Within Channels) (See Note below.) Parameter Symbol Transmit Receive CTXX-RX Crosstalk dBm0 Transmit Levels Receive Transmit CTRX-XX Crosstalk dBm0 Receive Levels Test Conditions Hz-3400 idle code channel under test; dBm0 into VFXIN Hz-3400 VFXIN Vrms channel under test; dBm0 code level Unit
Note: Tables crosstalk into transmit channels (VFXIN) significantly affected parasitic capacitive feeds from VFRO outputs. layouts should arranged keep these parasitics low. resistor value (from VFXIN) should also kept possible (while maintaining load above Table minimize crosstalk.
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Timing Characteristics
Table Clock Section (See Figures Symbol tMCHMCL1 tCDC tMCH1MCH2 tMCL2MCL1 Parameter Clock Pulse Width Duty Cycle, Clock Rise Fall Time Test Conditions Unit
Table T7504 Transmit Section (See Figure Symbol tMCHDV tMCHDV1 tMCLDZ* tFSHMCL tMCLFSH tFSLMCL tFSHFSL Parameter Data Enabled Entry Data Delay from Data Float Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Setup Frame-sync Pulse Width Test Conditions CLOAD CLOAD CLOAD tMCHMCH Unit
Timing parameter tMCLDZ referenced high-impedance state.
Table T5504 Transmit Section (See Figure Symbol tFSHDV tMCHDV1 tMCHDZ* tFSHMCL tMCLFSH tFSLMCL tFSHFSL Parameter Data Enabled Entry Data Delay from Data Float Exit Frame-sync Hold Time Frame-sync High Setup Frame-sync Setup Frame-sync Pulse Width Test Conditions CLOAD CLOAD CLOAD tMCHMCH Unit
Timing parameter tMCHDZ referenced high-impedance state.
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Timing Characteristics (continued)
Table T7504 T5504 Receive Section (See Figures Symbol tDVMCL tMCLDV tSPHMCL tMCLSPH tSPLMCL Parameter Receive Data Setup Receive Data Hold Frame Separation Hold Time Frame Separation High Setup Frame Separation Setup Test Conditions Unit
5-3581
Figure T7504 Transmit Receive Timing, FSEP MCLK
5-3582
Figure T7504 Receive Timing, FSEP MCLK Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Timing Characteristics (continued)
5-3581 (C).a
Figure T5504 Transmit Receive Timing, FSEP MCLK
5-3582 (C).a
Figure T5504 Receive Timing, FSEP MCLK
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Timing Characteristics (continued)
5-3583 (C).a
Figure Typical Frame Sync Timing Operation)
Applications
0.1µF GSXn VFXINn T7504 T5504 VFROn
SLIC 0.1µF ACIN
ZRCV
5-3584
Figure Typical T7504 T5504/SLIC Interconnection
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Outline Diagrams
28-Pin PLCC
Controlling dimensions inches.
12.446 0.127 11.506 0.076 IDENTIFIER ZONE
11.506 0.076 12.446 0.127
4.572 SEATING PLANE 1.27 0.51 0.330/0.533
5-2608 (F).r5
0.10
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Outline Diagrams (continued)
44-Pin MQFP
Controlling dimensions inches.
13.20 0.20 10.00 0.20 IDENTIFIER ZONE
13.20 0.20 10.00 0.20
DETAIL
DETAIL
1.95/2.10 2.35
SEATING PLANE 0.10
0.80
0.25
1.60
0.25 GAGE PLANE SEATING PLANE 0.73/1.03 0.30/0.45
0.130/0.230
0.20
DETAIL
DETAIL
5-2111 (F).r12
Agere Systems Inc.
T7504 T5504 Quad Codecs with Filters
Ordering Information
Device Code 7504 7504 JL-DB 7504 ML-TR 5504 5504 ML-TR Package 28-Pin, PLCC 44-Pin, MQFP Pack Tray 28-Pin, PLCC Tape Reel 28-Pin, PLCC 28-Pin, PLCC Tape Reel Temperature Timing Mode Delayed Delayed Delayed Nondelayed Nondelayed Comcode 107203184 107740466 107231680 107364044 107364051
Agere Systems Inc.
additional information, contact your Agere Systems Account Manager following: http://www.agere.com INTERNET: docmaster@agere.com E-MAIL: AMERICA: Agere Systems Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18109-3286 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) Tel. (44) 7000 624624, (44) 1344 EUROPE:
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application.
Copyright 2002 Agere Systems Inc. Rights Reserved
February 2002 DS02-149ALC (Replaces DS99-201ALC)
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