MSPS guaranteed sampling rate (AD9445BSV-125) 78.3 dBFS SNR/92 dBFS SF
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14-Bit, 105/125 MSPS, Sampling AD9445
MSPS guaranteed sampling rate (AD9445BSV-125) 78.3 dBFS SNR/92 dBFS SFDR with input (3.2 p-p) 74.8 dBFS SNR/95 dBFS SFDR with input (2.0 p-p) 77.0 dBFS SNR/87 dBFS SFDR with input (3.2 p-p) 74.6 dBFS SNR/95 dBFS SFDR with input (2.0 p-p) 73.0 dBFS SNR/88 dBFS SFDR with input (2.0 p-p) dBFS 2-tone SFDR with dBFS 2-tone SFDR with fsec jitter Excellent linearity ±0.25 typical ±0.8 typical differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) CMOS outputs Data format select (offset binary twos complement) Output clock available supply operation
AGND AVDD1 AVDD2 DRGND DRVDD ENABLE CMOS LVDS OUTPUT STAGING MODE OUTPUT MODE
05489-001
AD9445
BUFFER VIN+ VIN- PIPELINE
CLK+ CLK-
CLOCK TIMING MANAGEMENT
VREF SENSE REFT REFB
Figure
Optional features allow users implement various selectable operating conditions, including input range, data format select, high sampling mode, output data mode. AD9445 available Pb-free, 100-lead, surface-mount, plastic package (100-lead TQFP/EP) specified over industrial temperature range -40°C +85°C.
APPLICATIONS
Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar Infrared imaging Medical imaging Communications instrumentation
PRODUCT HIGHLIGHTS
High performance: outstanding SFDR performance sampling applications such multicarrier, multimode cellular base station receivers. Ease use: on-chip reference high input impedance track-and-hold with adjustable analog input range output clock simplifies data capture. Packaged Pb-free, 100-lead TQFP/EP package. Clock duty cycle stabilizer (DCS) maintains overall performance over wide range clock pulse widths. (out-of-range) outputs indicate when signal beyond selected input range. enable allows users configure device optimum SFDR when sampling frequencies above (AD9445-125) (AD9445-105).
GENERAL DESCRIPTION
AD9445 14-bit, monolithic, sampling analog-to-digital converter (ADC) with on-chip sampling track-and-hold circuit. optimized performance, small size, ease use. product operates MSPS conversion rate designed multicarrier, multimode receivers, such those found cellular infrastructure equipment. requires power supplies voltage differential input clock full performance operation. external reference driver components required many applications. Data outputs CMOS LVDS compatible (ANSI-644 compatible) include means reduce overall current needed short trace distances.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2005 Analog Devices, Inc. rights reserved.
AD9445 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Product Highlights Revision History Specifications. Specifications Specifications. Digital Specifications Switching Specifications Timing Diagrams. Absolute Maximum Ratings. Thermal Resistance Caution. Terminology Configurations Function Descriptions Equivalent Circuits. Typical Performance Characteristics Theory Operation Analog Input Reference Overview Clock Input Considerations. Power Considerations. Digital Outputs Timing Operational Mode Selection Evaluation Board Outline Dimensions Ordering Guide
REVISION HISTORY
10/05-Revision Initial Version
Rev. Page
AD9445 SPECIFICATIONS
SPECIFICATIONS
AVDD1 AVDD2 DRVDD LVDS mode, specified minimum sampling rate, differential input, internal trimmed reference (1.0 mode), -1.0 dBFS, unless otherwise noted. ENABLE AGND. Table
Parameter RESOLUTION ACCURACY Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL)1 VOLTAGE REFERENCE Output Voltage VREF Load Regulation Reference Input Current (External VREF INPUT REFERRED NOISE ANALOG INPUT Input Span VREF VREF Internal Input Common-Mode Voltage External Input Common-Mode Voltage Input Resistance Input Capacitance2 POWER SUPPLIES Supply Voltage AVDD1 AVDD2 DRVDD-LVDS Outputs DRVDD-CMOS Outputs Supply Current1 AVDD1 AVDD21, IDRVDD1-LVDS Outputs IDRVDD1-CMOS Outputs PSRR Offset Gain POWER CONSUMPTION LVDS Outputs CMOS Outputs Input)
Temp Full Full Full 25°C Full 25°C Full 25°C Full Full Full Full 25°C
AD9445BSVZ-105 Guaranteed -0.6 -1.6 +0.65
AD9445BSVZ-125 Guaranteed -0.6 +0.65
Unit Bits
±0.25 ±0.65
±0.25 ±0.8
+1.6
Full Full Full Full Full Full
Full Full Full Full Full Full Full Full Full Full Full Full
3.14 4.75
3.46 5.25
3.14 4.75
3.46 5.25
mV/V
Measured maximum clock rate, MHz, full-scale sine wave, with differential termination each pair output bits LVDS output mode approximately loading each output CMOS output mode. Input capacitance resistance refers effective impedance between differential input AGND. Refer Figure equivalent analog input structure. ENABLE AVDD1, IAVDD2 increases which increases power dissipation.
Rev. Page
AD9445
SPECIFICATIONS
AVDD1 AVDD2 DRVDD LVDS mode, specified minimum sample rate, differential input, internal trimmed reference (1.0 mode), -1.0 dBFS, ENABLE ground, unless otherwise noted. Table
Parameter SIGNAL-TO-NOISE RATIO (SNR) MHz2 MHz2 (3.2 Input) (3.2 Input) (3.2 Input) (3.2 Input)1 (3.2 Input)2 SIGNAL-TO-NOISE DISTORTION (SINAD) MHz1 MHz2 MHz2 MHz2 (3.2 Input) (3.2 Input) (3.2 Input) (3.2 Input)1 (3.2 Input)2 EFFECTIVE NUMBER BITS (ENOB) MHz1 MHz2 MHz2 MHz2 Temp 25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C AD9445BSVZ-105 74.3 74.3 73.6 72.1 70.5 77.6 77.5 75.3 73.7 74.2 74.2 73.3 72.5 71.7 67.2 65.2 77.4 77.3 75.7 75.1 72.5 12.2 12.2 12.1 12.0 11.8 11.7 11.6 AD9445BSVZ-125 74.1 73.8 73.2 72.9 70.5 77.3 77.3 75.4 73.5 73.9 73.7 73.0 72.5 71.5 66.3 64.3 76.9 76.8 75.4 75.2 71.8 12.2 12.1 12.0 12.0 11.8 11.7 11.6 Unit Bits Bits Bits Bits Bits Bits Bits
73.3 72.9 72.2 72.2 71.4
72.9 72.5 72.3 71.4 71.3
73.2 72.8 72.3 71.4 71.3 70.2
72.8 72.3 72.4 71.9 70.7 69.3
Rev. Page
AD9445
Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR, Second Third Harmonic) MHz1 MHz2 MHz2 MHz2 (3.2 Input) (3.2 Input) (3.2 Input) (3.2 Input)1 (3.2 Input)2 WORST SPUR EXCLUDING SECOND THIRD HARMONICS MHz1 MHz2 MHz2 MHz2 (3.2 Input) (3.2 Input) (3.2 Input) (3.2 Input)1 (3.2 Input)2 TWO-TONE SFDR 30.3 dBFS, 31.3 dBFS 170.3 dBFS, 171.3 dBFS ANALOG BANDWIDTH
Temp
AD9445BSVZ-105
AD9445BSVZ-125
Unit
25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C
25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full
dBFS dBFS
ENABLE (AGND AD9445-105; ENABLE high (AVDD1) AD9445-125. ENABLE high (AVDD1).
Rev. Page
AD9445
DIGITAL SPECIFICATIONS
AVDD1 AVDD2 DRVDD RLVDS_BIAS 3.74 unless otherwise noted. Table
Parameter CMOS LOGIC INPUTS (DFS, MODE, OUTPUT MODE) High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance DIGITAL OUTPUT BITS-CMOS MODE D13, OTR) DRVDD High Level Output Voltage Level Output Voltage DIGITAL OUTPUT BITS-LVDS MODE D13, OTR) Differential Output Voltage Output Offset Voltage CLOCK INPUTS (CLK+, CLK-) Differential Input Voltage Common-Mode Voltage Differential Input Resistance Differential Input Capacitance
Temp Full Full Full Full Full
AD9445BSVZ-105
AD9445BSVZ-125
Unit
Full Full Full Full Full Full Full Full
3.25 1.125 1.375
3.25 1.125 1.375
Output voltage levels measured with load each output. LVDS RTERM
SWITCHING SPECIFICATIONS
AVDD1 AVDD2 DRVDD unless otherwise noted. Table
Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate Period Pulse Width High (tCLKH) Pulse Width Low1 (tCLKL) DATA OUTPUT PARAMETERS Output Propagation Delay-CMOS (tPD) (Dx, DCO+) Output Propagation Delay-LVDS (tPD) (Dx+), (tCPD)3 (DCO+) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter,
Temp Full Full Full Full Full Full Full Full Full Full
AD9445BSVZ-105 3.35
AD9445BSVZ-125 3.35
Unit MSPS MSPS Cycles fsec
With duty cycle stabilizer (DCS) enabled. Output propagation delay measured from clock transition data transition with load. LVDS RTERM Measured from point rising edge CLK+ point data transition.
Rev. Page
AD9445
TIMING DIAGRAMS
tCLKL tCLKH
CLK+ CLK- 1/fS
DATA CLOCK CYCLES DCO+ DCO-
05489-002
tCPD
Figure LVDS Mode Timing Diagram
tCLKL tCLKH
CLK-
CLK+
CLOCK CYCLES
DCO+ DCO-
05489-003
Figure CMOS Timing Diagram
Rev. Page
AD9445 ABSOLUTE MAXIMUM RATINGS
Table
With Respect AGND AGND DGND DGND DRVDD DRVDD AVDD1 DGND AGND AGND
Parameter ELECTRICAL AVDD1 AVDD2 DRVDD AGND AVDD1 AVDD2 AVDD2 D13± CLK+/CLK- OUTPUT MODE, MODE, DFS, SFDR, ENABLE VIN+, VIN- VREF SENSE REFT, REFB ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering sec) Junction Temperature
Rating -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 DRVDD -0.3 AVDD1 -0.3 AVDD1
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL RESISTANCE
heat sink AD9445 package must soldered ground. Table
Package Type 100-lead TQFP/EP 19.8 Unit °C/W
AGND AGND AGND AGND
-0.3 AVDD2 -0.3 AVDD1 -0.3 AVDD1 -0.3 AVDD1 -65°C +125°C -40°C +85°C 300°C 150°C
Typical 19.8°C/W (heat sink soldered) multilayer board still air. Typical 8.3°C/W (heat sink soldered) multilayer board still air. Typical 2°C/W (junction exposed heat sink) represents thermal resistance through heat sink path. Airflow increases heat dissipation, effectively reducing Also, more metal directly contact with package leads from metal traces through holes, ground, power planes reduces required that exposed heat sink soldered ground plane.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD9445 TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth) analog input frequency which spectral power fundamental frequency determined analysis) reduced Aperture Delay (tA) delay between point rising edge clock instant which analog input sampled. Aperture Uncertainty (Jitter, sample-to-sample variation aperture delay. Clock Pulse Width Duty Cycle Pulse width high minimum amount time that clock pulse should left Logic state achieve rated performance. Pulse width minimum time clock pulse should left state. given clock rate, these specifications define acceptable clock duty cycle. Differential Nonlinearity (DNL, Missing Codes) ideal exhibits code transitions that exactly apart. deviation from this ideal value. Guaranteed missing codes 14-bit resolution indicates that 16,384 codes must present over operating ranges. Effective Number Bits (ENOB) effective number bits sine wave input given input frequency calculated directly from measured SINAD using following formula: Minimum Conversion Rate clock rate which lowest analog signal frequency drops more than below guaranteed limit. Offset Error major carry transition should occur analog value below VIN+ VIN-. Offset error defined deviation actual transition from that point. Out-of-Range Recovery Time time takes reacquire analog input after transition from above positive full scale above negative full scale, from below negative full scale below positive full scale. Output Propagation Delay (tPD) delay between clock rising edge time when bits within valid logic levels. Power-Supply Rejection Ratio change full scale from value with supply minimum limit value with supply maximum limit. Signal-to-Noise Distortion (SINAD) ratio input signal amplitude value other spectral components below Nyquist frequency, including harmonics excluding Signal-to-Noise Ratio (SNR) ratio input signal amplitude value other spectral components below Nyquist frequency, excluding first harmonics Spurious-Free Dynamic Range (SFDR) ratio signal amplitude value peak spurious spectral component. peak spurious component harmonic. SFDR reported (that degrades signal level lowered) dBFS (always related back converter full scale). Temperature Drift temperature drift offset error gain error specifies maximum change from initial (25°C) value value TMIN TMAX. Total Harmonic Distortion (THD) ratio input signal amplitude value first harmonic components. Two-Tone SFDR ratio value either input tone value peak spurious component. peak spurious component product.
Rev. Page
ENOB
(SINAD 1.76
6.02
Gain Error first code transition should occur analog value above negative full scale. last transition should occur analog value below positive full scale. Gain error deviation actual difference between first last code transitions ideal difference between first last code transitions. Integral Nonlinearity (INL) deviation each individual code from line drawn from negative full scale through positive full scale. point used negative full scale occurs before first code transition. Positive full scale defined level beyond last code transition. deviation measured from middle each particular code true straight line. Maximum Conversion Rate clock rate which parametric testing performed.
AD9445 CONFIGURATIONS FUNCTION DESCRIPTIONS
ENABLE D13+ (MSB) DRGND DRVDD DRVDD
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND
D12+
D11+
D10+
D13-
D12-
D11-
D10-
MODE OUTPUT MODE LVDS_BIAS AVDD1 SENSE VREF AGND
DRGND DCO+ DCO- DRVDD DRGND (LSB)
AD9445 LVDS MODE
VIEW (Not Scale)
REFT REFB AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1 AVDD1 AGND VIN+ VIN- AGND AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
CLK-
AVDD1
AVDD1
AVDD1
CLK+
DRGND
DRVDD
AGND
AGND
AGND
CONNECT
Figure 100-Lead TQFP/EP Configuration LVDS Mode
Rev. Page
05489-004
AD9445
Table Function Descriptions-100-Lead TQFP/EP LVDS Mode
Exposed Heat Sink Mnemonic MODE OUTPUT MODE LVDS_BIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 VIN+ VIN- CLK+ CLK- DRGND DRVDD (LSB) DCO- DCO+ D10- D10+ D11- D11+ Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. (AGND) enable (recommended); high (AVDD1) disable DCS. Connect. These pins should float. CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE CMOS mode; OUTPUT MODE (AVDD1) LVDS outputs. Data Format Select Pin. CMOS control that determines format output data. high (AVDD1) twos complement; (ground) offset binary format. LVDS Output Current. Place resistor terminated DRGND. (±5%) Analog Supply. Reference Mode Selection. Connect AGND internal reference; connect AVDD1 external reference. Reference I/O. Function dependent SENSE external programming resistors. Decouple ground with capacitors. Analog Ground. exposed heat sink bottom package must connected AGND. Differential Reference Output. Decoupled ground with capacitor REFB (Pin with capacitors. Differential Reference Output. Decoupled ground with capacitor REFT (Pin with capacitors. Analog Supply (±5%). Analog Input-True. Analog Input-Complement. Clock Input-True. Clock Input-Complement. Digital Output Ground. Digital Output Supply (3.0 Complement Output (LVDS Levels). True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Data Clock Output-Complement. Data Clock Output-True. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit.
Rev. Page
AD9445
Mnemonic D12- D12+ D13- D13+ (MSB) ENABLE Description Complement Output Bit. True Output Bit. Complement Output Bit. True Output Bit. Out-of-Range Complement Output Bit. Out-of-Range True Output Bit. ENABLE Control Pin. CMOS-compatible control optimize configuration AD9445 analog front end. Connecting ENABLE AGND optimizes SFDR performance applications with analog input frequencies <210 MSPS speed grade <230 MSPS speed grade. applications with analog inputs >225 MSPS speed grade >230 MSPS speed grade, this should connected AVDD1 optimum SFDR performance. Power dissipation from AVDD2 increases
Rev. Page
AD9445
ENABLE (MSB) DRGND DRVDD DRVDD
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND
MODE OUTPUT MODE LVDS_BIAS AVDD1 SENSE VREF AGND
DRGND (LSB) DCO+ DCO- DRVDD DRGND
AD9445 CMOS MODE
VIEW (Not Scale)
REFT REFB AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1 AVDD1 AGND VIN+ VIN- AGND AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
CLK-
AVDD1
AVDD1
AVDD1
CLK+
DRGND
DRVDD
AGND
AGND
AGND
CONNECT
Figure 100-Lead TQFP/EP Configuration CMOS Mode
Rev. Page
05489-005
AD9445
Table Function Descriptions-100-Lead TQFP/EP CMOS Mode
Exposed Heat Sink Mnemonic MODE OUTPUT MODE LVDS_BIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 VIN+ VIN- CLK+ CLK- DRGND DRVDD DCO- DCO+ (LSB) (MSB) ENABLE Description Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. (AGND) enable (recommended); high (AVDD1) disable DCS. Connect. These pins should float. CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE CMOS mode; OUTPUT MODE (AVDD1) LVDS outputs. Data Format Select Pin. CMOS control that determines format output data. high (AVDD1) twos complement; (ground) offset binary format. LVDS Output Current. Place resistor terminated DRGND. (±5%) Analog Supply. Reference Mode Selection. Connect AGND internal reference; connect AVDD1 external reference. Reference I/O. Function dependent SENSE external programming resistors. Decouple ground with capacitors. Analog Ground. exposed heat sink bottom package must connected AGND. Differential Reference Output. Decoupled ground with capacitor REFB (Pin with capacitors. Differential Reference Output. Decoupled ground with capacitor REFT (Pin with capacitors. Analog Supply (±5%). Analog Input-True. Analog Input-Complement. Clock Input-True. Clock Input-Complement. Digital Output Ground. Digital Output Supply (3.0 Data Clock Output-Complement. Data Clock Output-True. True Output (CMOS levels). True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. True Output Bit. Out-of-Range True Output Bit. ENABLE CMOS-compatible Control Pin. Optimizes configuration analog front end. Connecting ENABLE AGND optimizes SFDR performance applications with analog input frequencies <210 MSPS speed grade <230 MSPS speed grade. applications with analog inputs >225 MSPS speed grade >230 MSPS speed grade, this should connected AVDD1 optimum SFDR. Power dissipation from AVDD2 increases
Rev. Page
AD9445 EQUIVALENT CIRCUITS
AVDD2 VIN+
DRVDD
3.5V
AVDD2
VIN-
05489-006
Figure Equivalent Analog Input Circuit
Figure Equivalent CMOS Digital Output Circuit
05489-009
DRVDD
DRVDD
1.2V LVDS_BIAS 3.74k
ENABLE, MODE, OUTPUT MODE,
05489-007
05489-010
ILVDSOUT
Figure Equivalent LVDS_BIAS Circuit
Figure Equivalent Digital Input Circuit, DFS, MODE, OUTPUT MODE
AVDD2
DRVDD
CLK+
CLK-
2.5k 2.5k
05489-008
Figure Equivalent LVDS Digital Output Circuit
Figure Equivalent Sample Clock Input Circuit
Rev. Page
05489-011
AD9445 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 AVDD2 DRVDD rated sample rate, LVDS mode, enabled, 25°C, differential input, -1.0 dBFS, internal trimmed reference (nominal VREF unless otherwise noted.
AMPLITUDE (dBFS)
125MSPS 30.3MHz -1.0dBFS 73.4dB ENOB 12.1BITS SFDR 94dBc
AMPLITUDE (dBFS)
-100
05489-012
125MSPS 225.3MHz -1.0dBFS 72.9dB ENOB 12.1BITS SFDR 88dBc
-100 -110 -120 -130 15.625 31.250 FREQUENCY (MHz) 46.875
-120 -130 15.625 31.250 FREQUENCY (MHz) 46.875
62.500
62.500
Figure AD9445-125 Point Single-Tone FFT/125 MSPS/30.3
Figure AD9445-125 Point Single-Tone FFT/125 MSPS/225.3
AMPLITUDE (dBFS)
125MSPS 100.3MHz -1.0dBFS ENOB 12.1BITS SFDR 96dBc
AMPLITUDE (dBFS)
-100
05489-013
125MSPS 300.3MHz -1.0dBFS 72.0dB ENOB 11.8BITS SFDR 87dBc
-100 -110 -120 -130 15.625 31.250 FREQUENCY (MHz) 46.875
-120 -130 15.625 31.250 FREQUENCY (MHz) 46.875
62.500
62.500
Figure AD9445-125 Point Single-Tone FFT/125 MSPS/100.3
Figure AD9445-125 Point Single-Tone FFT/125 MSPS/300.3
AMPLITUDE (dBFS)
125MSPS 170.3MHz -1.0dBFS 73.2dB ENOB 12.0BITS SFDR 91dBc
AMPLITUDE (dBFS)
-100
05489-014
125MSPS 450.3MHz -1.0dBFS 70.5dB ENOB 11.6BITS SFDR 69dBc
-100 -110 -120 -130 15.625 31.250 FREQUENCY (MHz) 46.875
-120 -130 15.625 31.250 FREQUENCY (MHz) 46.875
62.500
62.500
Figure AD9445-125 Point Single-Tone FFT/125 MSPS/170.3
Figure AD9445-125 Point Single-Tone FFT/125 MSPS/450.3
Rev. Page
05489-017
-110
05489-016
-110
05489-015
-110
AD9445
SFDR +85°C SFDR +25°C SFDR -40°C +25°C
(dB) (dB)
SFDR +85°C SFDR +25°C -40°C -40°C +25°C +85°C +85°C
05489-018
SFDR -40°C
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure AD9445-125 SNR/SFDR Analog Input Frequency, MSPS, Input Range
Figure AD9445-125 SNR/SFDR Analog Input Frequency, MSPS, Input Range
SFDR +25°C
SFDR +85°C 125M SFDR
105M SFDR
+25°C
(dB)
SFDR -40°C -40°C
(dB)
125M
05489-019 05489-022
+85°C ANALOG INPUT FREQUENCY (MHz)
105M SAMPLE RATE (MSPS)
Figure AD9445-125 SNR/SFDR Analog Input Frequency, Input Range, MSPS, CMOS Output Mode
Figure AD9445 Single-Tone SNR/SFDR Sample Rate
SFDR dBFS
SFDR dBFS
dBFS
(dB) (dB)
dBFS
SFDR
05489-020
SFDR -100
05489-023
-100
ANALOG INPUT AMPLITUDE (dB)
ANALOG INPUT AMPLITUDE (dB)
Figure AD9445-125 SNR/SFDR Analog Input Level, MSPS/225.3
Rev. Page
Figure AD9445-125 SNR/SFDR Analog Input Level, MSPS/225.3 MHz, CMOS Output Mode
05489-021
AD9445
AMPLITUDE (dBFS)
105MSPS 30.3MHz -1.0dBFS 74.3dB ENOB 12.2BITS SFDR 92dBc
AMPLITUDE (dBFS)
-100
05489-024
105MSPS 225.3MHz -1.0dBFS 73.0dB ENOB 12.0BITS SFDR 87dBc
-100 -110 -120 -130 13.125 26.250 FREQUENCY (MHz) 39.375
-120 -130 13.125 26.250 FREQUENCY (MHz) 39.375
52.500
52.500
Figure AD9445-105 Point Single-Tone FFT/105 MSPS/30.3
Figure AD9445-105 Point Single-Tone FFT/105 MSPS/225.3
AMPLITUDE (dBFS)
105MSPS 100.3MHz -1.0dBFS 73.5dB ENOB 11.8BITS SFDR 93dBc
AMPLITUDE (dBFS)
-100
05489-025
105MSPS 300.3MHz -1.0dBFS 72.1dB ENOB 11.8BITS SFDR 87dBc
-100 -110 -120 -130 13.125 26.250 FREQUENCY (MHz) 39.375
-120 -130 13.125 26.250 FREQUENCY (MHz) 39.375
52.500
52.500
Figure AD9445-105 Point Single-Tone FFT/105 MSPS/100.3
Figure AD9445-105 Point Single-Tone FFT/105 MSPS/300.3
AMPLITUDE (dBFS)
105MSPS 170.3MHz -1.0dBFS 73.6dB ENOB 12.1BITS SFDR 94dBc
AMPLITUDE (dBFS)
-100
05489-026
105MSPS 450.3MHz -1.0dBFS 70.5dB ENOB 11.6BITS SFDR 70dBc
-100 -110 -120 -130 13.125 26.250 FREQUENCY (MHz) 39.375
-120 -130 13.125 26.250 FREQUENCY (MHz) 39.375
52.500
52.500
Figure AD9445-105 Point Single-Tone FFT/105 MSPS/170.3
Figure AD9445-105 Point Single-Tone FFT/105 MSPS/450.3
Rev. Page
05489-029
-110
05489-028
-110
05489-027
-110
AD9445
SFDR +25°C SFDR +85°C
(dB) (dB)
SFDR -40°C SFDR +25°C +25°C +85°C +25°C
05489-030
SFDR +85°C SFDR -40°C
-40°C ANALOG INPUT FREQUENCY (MHz)
-40°C
+85°C
ANALOG INPUT FREQUENCY (MHz)
Figure AD9445-105 SNR/SFDR Analog Input Frequency, MSPS,
Figure AD9445-105 SNR/SFDR Analog Input Frequency, MSPS,
SFDR +25°C
(dB)
SFDR +85°C
SFDR
SFDR -40°C
(dB)
-40°C
+25°C +85°C
05489-034
05489-031
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT COMMON-MODE VOLTAGE
Figure AD9445-105 SNR/SFDR Analog Input Frequency, Input Range, MSPS, CMOS Output Mode
Figure AD9445-105 SNR/SFDR Analog Input Common Mode, MSPS/10.3
SFDR dBFS
SFDR dBFS
dBFS
(dB)
dBFS
(dB)
SFDR
SFDR
05489-032
-100
05489-035
-100
ANALOG INPUT AMPLITUDE (dB)
ANALOG INPUT AMPLITUDE (dB)
Figure AD9445-105 SNR/SFDR Analog Input Level, MSPS/225.3
Rev. Page
Figure AD9445-105 SNR/SFDR Analog Input Level, MSPS/225.3 MHz, CMOS Output Mode
05489-033
AD9445
AMPLITUDE (dBFS)
125MSPS 30.3MHz -7.0dBFS 31.3MHz -7.0dBFS SFDR 102dBFS
SPUR IMD3 (dB)
-100
05489-037
SFDR
-100 -110 -120 -130 -140 13.625 27.250 40.875 54.500 FREQUENCY (MHz)
WORST IMD3
SFDR dBFS
05489-041
-110 -120 -100
WORST IMD3 dBFS
FUNDAMENTAL LEVEL (dB)
Figure AD9445-125 Point Two-Tone FFT/ MSPS/30.3 MHz, 31.3
Figure AD9445-125 Two-Tone SFDR Analog Input Level MSPS/170.3 MHz, 171.3
SPUR IMD3 (dB)
SFDR
AMPLITUDE (dBFS)
-100 -110
05489-038
105MSPS 30.3MHz -7.0dBFS 31.3MHz -7.0dBFS SFDR 102dBFS
-100 -110 -120 -100 WORST IMD3 dBFS SFDR dBFS WORST IMD3
-130 -140 13.125 26.250 FREQUENCY (MHz) 39.375
52.500
FUNDAMENTAL LEVEL (dB)
Figure AD9445-125 Two-Tone SFDR Analog Input Level MSPS/30.3 MHz, 31.3
Figure AD9445-105 Point Two-Tone FFT/105 MSPS/30.3 MHz, 31.3
AMPLITUDE (dBFS)
125MSPS 170.3MHz -7.0dBFS 171.3MHz -7.0dBFS SFDR 91dBFS
SPUR IMD3 (dB)
-100
05489-040
-100 -110 -120 -130 -140 13.625 27.250 40.875 54.500 FREQUENCY (MHz)
SFDR
WORST IMD3
SFDR dBFS WORST IMD3 dBFS
05489-043
-110 -120 -100
FUNDAMENTAL LEVEL (dB)
Figure AD9445-125 Point Two-Tone FFT/ MSPS/170.3 MHz, 171.3
Rev. Page
Figure AD9445-105 Two-Tone SFDR Analog Input Level MSPS/30.3 MHz, 31.3
05489-042
-120
AD9445
25000 22190 20000 25000 23754 30000 SAMPLE SIZE 65538 26294
20000
FREQUENCY
15000
FREQUENCY
15743 15000
16117
10000 7968
9003
10000
5000
05489-044
5000 1127 1355 OUTPUT CODE
OUTPUT CODE
Figure AD9445-125 Grounded Input Histogram
Figure AD9445-105 Grounded Input Histogram
AMPLITUDE (dBFS)
105MSPS 170.3MHz -7.0dBFS 171.3MHz -7.0dBFS SFDR 92dBFS
GAIN ERROR (%FSR)
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6
05489-045
05489-048
-100 -110 -120 -130 -140 13.125 26.250 FREQUENCY (MHz) 39.375
-0.7 -0.8
52.500
TEMPERATURE (°C)
Figure AD9445-105 Point Two-Tone FFT/105 MSPS/170.3 MHz, 171.3
Figure AD9445-125 Gain Temperature
SPUR IMD3 (dB)
ERROR (LSB)
SFDR
-100 -110 -120 -100 WORST IMD3 dBFS
05489-046
-0.1 -0.2
05489-049
WORST IMD3
SFDR dBFS
-0.3 -0.4 4096 8192 OUTPUT CODE 12288
16384
FUNDAMENTAL LEVEL (dB)
Figure AD9445-105 Two-Tone SFDR Analog Input Level MSPS/170.3 MHz, 171.3
Figure AD9445-105 Error Output Code, MSPS, 10.3
Rev. Page
05489-047
3350
3493
AD9445
ERROR (LSB)
ERROR (LSB)
05489-050
-0.1 -0.2
-0.2 -0.4 -0.6 -0.8 -1.0 4096 8192 OUTPUT CODE 12288
05489-053
-0.3 -0.4 4096 8192 OUTPUT CODE 12288
16384
16384
Figure AD9445-125 Error Output Code, MSPS, 10.3
Figure AD9445-125 Error Output Code, MSPS, 10.3
1.014
1.012 1.010
ISUPPLY (mA) VREF
AVDD1 AVDD2
1.008
1.006 DRVDD
05489-051 05489-066
1.004
SAMPLE RATE (MSPS)
1.002
TEMPERATURE (°C)
Figure AD9445-125 VREF Temperature
Figure AD9445-105 Power Supply Current Sample Rate 10.3 dBFS
ERROR (LSB)
170.3MHz
(dB)
-0.1 -0.2 -0.3 -0.4 -0.5 4096 8192 OUTPUT CODE 12288
05489-052
225.3MHz
300.3MHz
16384
ANALOG INPUT RANGE p-p)
Figure AD9445-105 Error Output Code, MSPS, 10.3
Figure AD9445-125 Analog Input Range, MSPS/170.3 MHz, 225.3 MHz, 300.3
Rev. Page
05489-067
AD9445
170.3MHz SFDR
(dB)
170.3MHz SFDR 225.3MHz SFDR
(dB)
300.3MHz SFDR
225.3MHz SFDR
05489-068
300.3MHz SFDR
ANALOG INPUT RANGE p-p)
ANALOG INPUT RANGE p-p)
Figure AD9445-105 Analog Input Range, MSPS/170.3 MHz, 225.3 MHz, 300.3
Figure AD9445-105 SFDR Analog Input Range, MSPS/170.3 MHz, 225.3 MHz, 300.3
AVDD1
ISUPPLY (mA)
105M dBFS
AVDD2 DRVDD
05489-069 05489-039
(dB)
125M dBFS
SAMPLE RATE (MSPS)
ANALOG INPUT RANGE p-p)
Figure AD9445-125 Power Supply Current Sample Rate 10.3 dBFS
Figure Analog Input Range, dBFS
170.3MHz SFDR
(dB)
225.3MHz SFDR
05489-070
300.3MHz SFDR
ANALOG INPUT RANGE p-p)
Figure AD9445-125 SFDR Analog Input Range, MSPS/170.3 MHz, 225.3 MHz, 300.3
Rev. Page
05489-071
AD9445 THEORY OPERATION
AD9445 architecture optimized high speed ease use. analog inputs drive integrated, high bandwidth track-and-hold circuit that samples signal prior quantization 14-bit pipeline core. device includes on-board reference input logic that accepts TTL, CMOS, LVPECL levels. digital output logic levels user selectable standard CMOS LVDS (ANSI-644 compatible) OUTPUT MODE pin. connected AGND). Because this trim maximum performance provided analog input range, there little benefit using analog input ranges p-p. Users cautioned that differential nonlinearity varies with reference voltage. Configurations that <2.0 exhibit missing codes and, therefore, degraded noise distortion performance.
VIN+ VIN- REFT CORE 0.1F 0.1F REFB VREF 0.1F SELECT LOGIC SENSE 0.5V 0.1F
ANALOG INPUT REFERENCE OVERVIEW
stable accurate band voltage reference built into AD9445. input range adjusted varying reference voltage applied AD9445, using either internal reference externally applied reference voltage. input span tracks reference voltage changes linearly.
Internal Reference Connection
comparator within AD9445 detects potential SENSE configures reference into three possible states, which summarized Table SENSE grounded, reference amplifier switch connected internal resistor divider (see Figure 59), setting VREF ~1.0 Connecting SENSE VREF switches reference amplifier output SENSE pin, completing loop providing ~1.0 reference output. resistor divider connected shown Figure switch again sets SENSE pin. This puts reference amplifier noninverting mode with VREF output defined
AD9445
Figure Internal Reference Configuration
VIN+ VIN- REFT CORE 0.1F 0.1F REFB VREF 0.1F SENSE SELECT LOGIC 0.1F
VREF
reference configurations, REFT REFB drive analog-to-digital conversion core establish input span. input range always equals twice voltage reference either internal external reference.
0.5V
Internal Reference Trim
internal reference voltage trimmed during production test adjust gain (analog input voltage range) AD9445. Therefore, there little advantage user supplying external voltage reference AD9445. gain trim performed with AD9445 input range nominal (SENSE
Table Reference Configuration Summary
Selected Mode External Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD1 VREF AGND Resulting VREF
(See Figure
AD9445
Figure Programmable Reference Configuration
Resulting Differential Span p-p) external reference VREF
Rev. Page
05489-055
05489-054
AD9445
External Reference Operation
AD9445's internal reference trimmed enhance gain accuracy ADC. external reference more stable over temperature, gain likely improve. Figure shows typical drift characteristics internal reference both modes. When SENSE tied AVDD, internal reference disabled, allowing external reference. internal reference buffer loads external reference with equivalent load. internal buffer still generates positive negative full-scale references, REFT REFB, core. input span always twice value reference voltage; therefore, external reference must limited maximum
VIN+
3.5V
VIN-
DIGITAL
DIGITAL
05489-056
Figure Differential Analog Input Range VREF
Analog Inputs
with most high speed, high dynamic range ADCs, analog input AD9445 differential. Differential inputs improve on-chip performance because signals processed through attenuation gain stages. Most improvement result differential analog stages having high rejection even-order harmonics. There also benefits level. First, differential inputs have high common-mode rejection stray signals, such ground power noise. Second, they provide good rejection common-mode signals, such local oscillator feedthrough. specified noise distortion AD9445 cannot realized with single-ended analog input, such configurations discouraged. Contact sales recommendations other 14-bit ADCs that support singleended analog input configurations. With reference, which nominal value (see Internal Reference Trim section), differential input range AD9445 analog input nominally each input (VIN+ VIN-). AD9445 analog input voltage range offset from ground Each analog input connects through resistor bias voltage input differential buffer. internal bias network input properly biases buffer maximum linearity range (see Equivalent Circuits section).
Therefore, analog source driving AD9445 should accoupled input pins. recommended method driving analog input AD9445 transformer convert single-ended signals differential (see Figure 62). Series resistors between output transformer AD9445 analog inputs help isolate analog input source from switching transients caused internal sample-and-hold circuit. series resistors, along with resisters connected internal bias, must considered impedance matching transformer input. example, there impedance ratio transformer, input will match source with full-scale drive 10.0 dBm. impedance matching also incorporated secondary side transformer, shown evaluation board schematic (see Figure 67).
ANALOG INPUT SIGNAL ADT1-1WT VIN+
0.1F
AD9445
05489-057
VIN-
Figure Transformer-Coupled Analog Input Circuit
High Applications
applications where analog input frequency range >100 MHz, phase amplitude matching analog inputs becomes critical optimize performance ADC. circuit Figure used optimize matching these parameters. This configuration uses double balun configuration that parasitics, high bandwidth, parasitic cancellation.
ETC1-1-13 ETC1-1-13 SOURCE 0.1F
0.1F
VIN+
AD9445
VIN-
05489-058
Figure Double Balun-Coupled Analog Input Circuit
Rev. Page
AD9445
CLOCK INPUT CONSIDERATIONS
high speed extremely sensitive quality sampling clock provided user. track-and-hold circuit essentially mixer, noise, distortion, timing jitter clock combined with desired signal analog-todigital output. that reason, considerable care taken design clock inputs AD9445, user advised give careful thought clock source. Typical high speed ADCs both clock edges generate variety internal timing signals and, result, sensitive clock duty cycle. Commonly tolerance required clock duty cycle maintain dynamic performance characteristics. AD9445 contains clock duty cycle stabilizer (DCS) that retimes nonsampling edge, providing internal clock signal with nominal duty cycle. Noise distortion performance nearly flat duty cycle with enabled. circuit locks rising edge CLK+ optimizes timing internally. This allows wide range input duty cycles input without degrading performance. Jitter rising edge input still paramount concern reduced internal stabilization circuit. duty cycle control loop does function clock rates less than nominally. loop associated with time constant that should considered applications where clock rate change dynamically, requiring wait time after dynamic clock frequency increase decrease before loop relocked input signal. During time that loop locked, loop bypassed, internal device timing dependent duty cycle input clock signal. such application, appropriate disable duty cycle stabilizer. other applications, enabling circuit recommended maximize performance. circuit controlled MODE pin; CMOS logic (AGND) MODE enables duty cycle stabilizer, logic high (AVDD1 disables controller. AD9445 input sample clock signal must high quality, extremely phase noise source prevent degradation performance. Maintaining 14-bit accuracy places premium encode clock phase noise. performance easily degrade with analog input signals when using high jitter clock source. (See AN-501 Application Note, Aperture Uncertainty System Performance.) optimum performance, AD9445 must clocked differentially. sample clock inputs internally biased ~2.2 input signal usually ac-coupled into CLK+ CLK- pins transformer capacitors. Figure shows preferred method clocking AD9445. clock source (low jitter) converted from singleended differential using transformer. back-to-back Schottky diodes across secondary transformer limit clock excursions into AD9445 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD9445 limits noise presented sample clock inputs. jitter clock available, help band-pass filter clock reference before driving clock inputs. Another option couple differential ECL/PECL signal encode input pins, shown Figure
CLOCK SOURCE ADT1-1WT
0.1F
CLK+
AD9445
HSMS2812 DIODES
05489-059
CLK-
Figure Crystal Clock Oscillator, Differential Encode
0.1F
ENCODE ECL/ PECL 0.1F
AD9445
ENCODE
05489-060
Figure Differential Encode
Jitter Considerations
High speed, high resolution ADCs sensitive quality clock input. degradation given input frequency (fINPUT) amplitude only aperture jitter (tJ) calculated using following equation:
log[2fINPUT
equation, aperture jitter represents rootmean-square jitter sources, which includes clock input, analog input signal, aperture jitter specification. undersampling applications particularly sensitive jitter, Figure clock input should treated analog signal cases where aperture jitter affect dynamic range AD9445. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. jitter crystal-controlled oscillators make best clock sources. clock generated from another type source gating, dividing, another method), should synchronized original clock during last step.
Rev. Page
AD9445
0.2ps
0.5ps
(dBc)
1.0ps 1.5ps 2.0ps 2.5ps 3.0ps
INPUT FREQUENCY (MHz)
1000
Figure Input Frequency Jitter
POWER CONSIDERATIONS
Care should taken when selecting power source. linear supplies highly recommended. Switching supplies tend have radiated components that received AD9445. Each power supply pins should decoupled closely package possible using chip capacitors. AD9445 separate digital analog power supply pins. analog supplies denoted AVDD1 (3.3 AVDD2 digital supply pins denoted DRVDD. Although AVDD1 DRVDD supplies tied together, best performance achieved when supplies separate. This because fast digital output swings couple switching current back into analog supplies. Note that both AVDD1 AVDD2 must held within specified voltage. DRVDD supply AD9445 dedicated supply digital outputs either LVDS CMOS output mode. When LVDS mode, DRVDD should CMOS mode, DRVDD supply connected from compatibility with receiving logic.
05489-061
resistor placed (LVDS_BIAS) ground. Dynamic performance, including both SFDR SNR, maximized when AD9445 used LVDS mode; designers encouraged take advantage this mode. AD9445 outputs include complimentary LVDS outputs each data (Dx+/Dx-), overrange output (OR+/OR-), output data clock output (DCO+/DCO-). RSET resistor current multiplied on-chip, setting output current each output equal nominal IRSET). differential termination resistor placed LVDS receiver inputs results nominal swing receiver. LVDS mode facilitates interfacing with LVDS receivers custom ASICs FPGAs that have LVDS capability superior switching performance noisy environments. Single point-to-point topologies recommended, with termination resistor placed close receiver possible. recommended keep trace length less than inches keep differential output trace lengths equal possible.
CMOS Mode
applications that tolerate slight degradation dynamic performance, AD9445 output drivers configured interface with logic families matching DRVDD digital supply interfaced logic. CMOS outputs available when OUTPUT MODE CMOS logic AGND convenience). this mode, output data bits, single-ended CMOS, overrange output, output clock provided differential CMOS signal, DCO+/DCO-. Lower supply voltages recommended avoid coupling switching transients back sensitive analog sections ADC. capacitive load CMOS outputs should minimized, each output should connected single gate through series resistor (220 minimize switching transients caused capacitive loading.
TIMING
AD9445 provides latched data outputs with pipeline delay clock cycles. Data outputs available propagation delay (tPD) after rising edge CLK+. Refer Figure Figure detailed timing diagrams.
DIGITAL OUTPUTS
LVDS Mode
off-chip drivers chip configured provide LVDS-compatible output levels (OUTPUT MODE). LVDS outputs available when OUTPUT MODE CMOS logic high AVDD1 convenience) 3.74 RSET
Rev. Page
AD9445
OPERATIONAL MODE SELECTION
Data Format Select
data format select (DFS) AD9445 determines coding format output data. This CMOScompatible, with logic high AVDD1, selecting twos complement logic (AGND) selecting offset binary format. Table summarizes output coding.
ENABLE
ENABLE CMOS-compatible control that optimizes configuration AD9445 analog front end. crossover analog input frequency determining ENABLE connection differs MSPS MSPS speed grades. MSPS speed grade, connecting ENABLE AGND optimizes SFDR performance applications with analog input frequencies <210 MHz. applications with analog inputs >210 MHz, this should connected AVDD1 optimum SFDR performance. Connecting this AVDD1 reconfigures ADC, thereby improving high spurious performance. Operating this mode increases power dissipation from AVDD2 MSPS speed grade, connecting ENABLE AGND optimizes SFDR performance applications with analog input frequencies <230 MHz. applications with analog inputs >230 MHz, this should connected AVDD1 optimize performance.
Output Mode Select
OUPUT MODE controls logic compatibility, well pinout digital outputs. This CMOS-compatible input. With OUTPUT MODE (AGND), AD9445 outputs CMOS compatible, assignment device defined Table With OUTPUT MODE (AVDD1, AD9445 outputs LVDS compatible, assignment device defined Table
Duty Cycle Stabilizer
circuit controlled MODE pin; CMOS logic (AGND) MODE enables DCS, logic high (AVDD1, disables controller.
Table Digital Output Coding
Code 16,383 8192 8191 VIN+ VIN- Input Span +1.600 -0.000195 -1.60 VIN+ VIN- Input Span +1.000 -0.000122 -1.00 Digital Output Offset Binary 1111 1111 1111 0000 0000 0000 1111 1111 1111 0000 0000 0000 Digital Output Twos Complement 1111 1111 1111 0000 0000 0000 1111 1111 1111 0000 0000 0000
Rev. Page
AD9445 EVALUATION BOARD
Evaluation boards offered configure AD9445 either CMOS LVDS mode only. This design represents recommended configuration using device over wide range sampling rates analog input frequencies. These evaluation boards provide support circuitry required operate various modes configurations. Complete schematics shown Figure through Figure Gerber files available from engineering applications demonstrating proper routing grounding techniques that should applied system level. critical that signal sources with very phase noise (<60 fsec jitter) used realize ultimate performance converter. Proper filtering input signal remove harmonics lower integrated noise input also necessary achieve specified noise performance. evaluation boards shipped with power supply. evaluation boards include dropout regulators generate various supplies required AD9445 support circuitry. Separate power supplies provided isolate from support circuitry. Each input configuration selected proper connection various jumpers (see Figure 67). LVDS mode evaluation boards include LVDS-to-CMOS translator, making them compatible with high speed FIFO evaluation (HSC-ADC-EVALA-SC). includes high speed data capture board that provides hardware solution capturing samples high speed output data FIFO memory chip (user upgradeable samples). Software provided enable user download captured data port. This software also includes behavioral model AD9445 many other high speed ADCs. Behavioral modeling AD9445 also available www.analog.com/ADIsimADC. ADIsimADCsoftware supports virtual evaluation using proprietary behavioral modeling technology. This allows rapid comparison between AD9445 other high speed ADCs with without hardware evaluation boards. user choose remove translator terminations access LVDS outputs directly.
Rev. Page
AD9445
PTMICRO4 PTMICRO4
DRGND MTHOLE6 MTHOLE6 MTHOLE6 MTHOLE6 XTALPWR EXTREF DRGND DRVDD
DRVDD D11_C/D6_Y D11_T/D7_Y
D12_C/D8_Y D12_T/D9_Y D13_C/D10_Y D13_T/D11_Y D14_C/D12_Y D14_T/D13_Y D15_C/D14_Y (MSB) D15_T/D15_Y DRGND DRVDD DOR_C DOR_T/DOR_Y
EPAD
DRVDD D11_C D11_T D12_C D12_T D13_C D13_T D14_C D14_T D15_C D15_T DRGND DRVDD OR_C OR_T AGND AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AGND AGND AGND
DRGND D10_T/D5_Y D10_C/D4_Y D9_T/D3_Y D9_C/D2_Y
0.1F 0.1F 0.1F 0.1F
Figure AD9445 Evaluation Board Schematic
EXTREF
Rev. Page
3.74k
D8_T/D1_Y D8_C/D0_Y
AD9445/AD9446
D7_T D7_C DRVDD DRGND D6_T D6_C
TOUT
0.1F
ETC1-1-13
SMBMST 0.1F
10nH
D0_T D0_C DRVDD DRGND AGND AVDD1 AVDD1 AVDD1 AGND ENCB
AGND AVDD1 AVDD2 AVDD1 AVDD2 AVDD1 AVDD1 AVDD1 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2
0.1F
TINB
SCLK 0.1F MODE OUTPUT MODE LVDSBIAS AVDD1 SENSE VREF AGND REFT REFB AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1 AVDD1 AGND VIN+ VIN- AGND AVDD2
DRGND D10_T D10_C D9_T D9_C D8_T D8_C DCOB D7_T D7_C DRVDD DRGND D6_T D6_C D5_T D5_C D4_T D4_C D3_T D3_C D2_T D2_C D1_T D1_C
D5_T D5_C D4_T D4_C D3_T D3_C D2_T D2_C D1_T D1_C
ETC1-1-13
ANALOG
TOUTB
OPTIONAL
0.1F
TOUT TOUTB 0.1F
ADT1-1WT
ENCB
D0_T D0_C (LSB) DRVDD DRGND
TINB
05489-062
VXTAL XTALPWR VXTAL MAKE LAYOUT PARASITIC LOADING SYMMETRICAL 0.1F
ENCODE
OPTIONAL ENCODE CIRCUITS
ADT1-1WT
SMBMST
SMBMST
ECLOSC ~OUT XTALINPUT
0.1F
ENCB DRVDD FERRITE VCCX FERRITE FERRITE DRVDDX VXTAL
0.1F
XTALINPUT
Figure AD9445 Evaluation Board Schematic (Continued)
Rev. Page
ADP3338
VCCX OUT1
POWER OPTIONS
DRGND
ADP3338
3.3V OUT1 VCCX DRVDDX
ADP3338
3.3V OUT1 DRGND DRVDDX
PJ-102A
DRGND
DRGND
05489-063
AD9445
AD9445
BYPASS CAPACITORS
0.1F 0.1F 0.1F 0.01F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F
DRVDD DRGND 0.1F 0.1F 0.1F 0.1F
DRVDD DRGND
0.1F 0.1F 0.1F 0.01F 0.1F 0.1F 0.1F
EXTREF
C108 C109 C110
05489-064
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
Figure AD9445 Evaluation Board Schematic (Continued)
Rev. Page
SN75LVDT390 DRVDD DRVDD DRGND DRVDD EN_1_2 EN_3_4
DOR_T/DOR_Y DOR_C
SN75LVDS386 RSO16ISO DRVDD RSO16ISO DRVDD DRGND D15O D14O D13O D12O D11O D10O
DRGND DRGND DOR_C D15_C/D14_Y D14_C/D12_Y D13_C/D10_Y D12_C/D8_Y D11_C/D6_Y D10_C/D4_Y D9_C/D2_Y D8_C/DO_Y D7_C D6_C D5_C D4_C D3_C D2_C D1_C D0_C DRGND
DRGND
C40MS
DRGND GNDN D15O D14O D13O D12O D11O D10O DRGND
DOR_T/DOR_Y
D15_T/D15_Y
DRGND DRVDD DRVDD DRGND DRVDD
D14_T/D13_Y
D13_T/D11_Y
D12_T/D9_Y
D11_T/D7_Y
D10_T/D5_Y
D9_T/D3_Y
Figure AD9445 Evaluation Board Schematic (Continued)
Rev. Page
DRGND DRVDD DRVDD DRGND DRVDD DRGND DRVDD DRVDD DRGND DRVDD 0.1F DRGND 0.1F 0.1F 0.1F
D8_T/D1_Y
D7_T
D6_T
D5_T
D4_T
D3_T
D2_T
D1_T
D0_T
DRGND
D15_T/D15_Y D15_C/D14_Y D14_T/D13_Y D14_C/D12_Y D13_T/D11_Y D13_C/D10_Y D12_T/D9_Y D12_C/D8_Y D11_T/D7_Y D11_C/D6_Y D10_T/D5_Y D10_C/D4_Y D9_T/D3_Y D9_C/D2_Y D8_T/D1_Y D8_C/D0_Y D7_T D7_C D6_T D6_C D5_T D5_C D4_T D4_C D3_T D3_C D2_T D2_C D1_T D1_C D0_T D0_C VCC1 VCC2 GND1 GND2 VCC3 VCC4 GND3 GND4 VCC5 VCC6 GND5
C40MS
05489-065
AD9445
AD9445
Table AD9445-125 Baseband Customer Evaluation Board Bill Materials
Item Qty. Reference Designator C33, C34, C87, C88, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, C48, C50, C52, C53, C59, C60, C76, C77, C78, C82, C84, C85, C86, C90, C91, C94, C95, C96, C30, C39, C56, C64, E10, E14, E18, E19, E20, E24, E25, E26, E27, E30, E31, E36, R10, R19, R39, R28, RZ4, C44, C13, C14, C16, C17, C18, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, C93, C108, C109, C1101 C981 E151 Description Capacitor Capacitor Package TAJD Value Manufacturer Digi-Key Corporation Digi-Key Corporation Mfg. Part 478-1699-2 PCC2146CT-ND
Capacitor Capacitor Capacitor Diode Diode Header
TAJD SOT23M5 SOT23M5 EHOLE
0.01
Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Mouser Electronics
445-1796-1-ND 478-1699-2 490-1717-1-ND MA3X71600LCT-ND MA3X71600LCT-ND 517-6111TG
Inductor EMIFIL® BLM31PG500SN1L PJ-002A Header Resistor Resistor Resistor BRES402 Resistor Resistor array Transformer AD9445BSVZ-125 ADP3338-5 ADP3338-3.3 SN75LVDT386 SN75LVDT390 Resistor Capacitor CAP402
0603A 1206MIL PJ-002A C40MS 16PIN ADT1-1WT SV-100-3 SOT-223HS SOT-223HS TSSOP64 SOIC16PW TAJD
Digi-Key Corporation Coilcraft, Inc. Mouser Electronics Digi-Key Corporation Samtec, Inc. Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Mini-Circuits Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. Arrow Electronics, Inc. Arrow Electronics, Inc. Digi-Key Corporation Digi-Key Corporation
ARFX1231-ND 0603CS-10NXGBU 81-BLM31P500S CP-002A-ND TSW-120-08-L-D-RA P3.74KLCT-ND P49.9LCT-ND P0.0JCT-ND P1.0KLCT-ND P33JCT-ND 742C163220JCT-ND ADT1-1WT AD9445BSVZ-125 ADP3338-5 ADP3338-33 SN75LVDT386DGG SN75LVDT390PW P36JCT-ND 478-1699-2
3.74
Capacitor Header Header BRES402 BRES402 ECLOSC
EHOLE C40MS DIP4(14)
Rev. Page
Digi-Key Corporation Mouser Electronics Digi-Key Corporation Samtec, Inc.
490-1717-1-ND 517-6111TG ARFX1231-ND TSW-120-08-L-D-RA
AD9445
Item
Qty.
Reference Designator P21, P221
Description MTHOLE6 Balun transformer Term strip
Package MTHOLE6 SM-22 PTMICRO4
Value
Manufacturer M/A-COM Newark Electronics
Mfg. Part ETC1-1-13
Parts populated.
Table AD9445-125 Customer Evaluation Board Bill Materials
Item Qty. Reference Designator C33, C34, C87, C88, C10, C11, C12, C15, C20, C21, C22, C23, C26, C27, C28, C32, C35, C38, C40, C42, C43, C46, C47, C48, C50, C52, C53, C59, C60, C76, C77, C78, C82, C84, C85, C86, C90, C91, C94, C95, C96, C30, C39, C56, C64, E10, E14, E18, E19, E20, E24, E25, E26, E27, E30, E31, E36, R10, R19, R39, R28, RZ4, C44, Description Capacitor Capacitor Package TAJD Value Manufacturer Digi-Key Corporation Digi-Key Corporation MFG_PART_NO 478-1699-2 PCC2146CT-ND
Capacitor Capacitor Capacitor Diode Diode Header
TAJD SOT23M5 SOT23M5 EHOLE
0.01
Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Mouser Electronics
445-1796-1-ND 478-1699-2 490-1717-1-ND MA3X71600LCT-ND MA3X71600LCT-ND 517-6111TG
Inductor EMIFIL® BLM31PG500SN1L PJ-002A Header Resistor Resistor Resistor BRES402 Resistor Resistor array AD9445BSVZ-125 ADP3338-5 ADP3338-3.3 SN75LVDT386 SN75LVDT390 Balun transformer Resistor Transformer Capacitor
0603A 1206MIL PJ-002A C40MS 16PIN SV-100-3 SOT223HS SOT-223HS TSSOP64 SOIC16PW SM-22 ADT1-1WT TAJD
3.74
Digi-Key Corporation Coilcraft, Inc. Mouser Electronics Digi-Key Corporation Samtec, Inc. Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Digi-Key Corporation Analog Devices, Inc. Analog Devices, Inc. Analog Devices, Inc. Arrow Electronics, Inc. Arrow Electronics, Inc. M/A-COM Digi-Key Corporation Mini-Circuits Digi-Key Corporation
ARFX1231-ND 0603CS-10NXGBU 81-BLM31P500S CP-002A-ND TSW-120-08-L-D-RA P3.74KLCT-ND P49.9LCT-ND P0.0JCT-ND P1.0KLCT-ND P33JCT-ND 742C163220JCT-ND AD9445BSVZ-125 ADP3338-5 ADP3338-3.3 SN75LVDT386DGG SN75LVDT390PW ETC-1-1-13 P49.9LCT-ND ADT1-1WT 478-1699-2
Rev. Page
AD9445
Item Qty. Reference Designator C13, C14, C16, C17, C18, C19, C29, C31, C36, C37, C41, C45, C49, C61, C69, C70, C72, C73, C75, C93, C108, C109, C1101 C981 E151 P21, P221 Description CAP402 Package Value Manufacturer MFG_PART_NO
Capacitor Header Header BRES402 BRES402 ECLOSC MTHOLE6 Resistor Transformer Term strip
EHOLE C40MS DIP4(14) MTHOLE6 ADT1-1WT PTMICRO4
Digi-Key Corporation Mouser Electronics Digi-Key Corporation Samtec, Inc.
409-1717-1-ND 517-6111TG ARFX1231-ND TSW-120-08-L-D-RA
Digi-Key Corporation Mini-Circuits Newark Electronics
P36JCT-ND ADT1-1WT
Parts populated.
Rev. Page
AD9445 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.20
16.00 14.00
VIEW
(PINS DOWN)
EXPOSED
9.50
1.05 1.00 0.95
0.15 0.05
SEATING PLANE
0.20 0.09 3.5° 0.08 COPLANARITY
BOTTOM VIEW (PINS
VIEW
0.50 LEAD PITCH
0.27 0.22 0.17
VIEW
ROTATED
COMPLIANT JEDEC STANDARDS MS-026-AED-HD NOTES CENTER FIGURES TYPICAL UNLESS OTHERWISE NOTED. PACKAGE CONDUCTIVE HEAT SLUG HELP DISSIPATE HEAT ENSURE RELIABLE OPERATION DEVICE OVER FULL INDUSTRIAL TEMPERATURE RANGE. SLUG EXPOSED BOTTOM PACKAGE ELECTRICALLY CONNECTED CHIP GROUND. RECOMMENDED THAT SIGNAL TRACES VIAS LOCATED UNDER PACKAGE THAT COULD COME CONTACT WITH CONDUCTIVE SLUG. ATTACHING SLUG GROUND PLANE WILL REDUCE JUNCTION TEMPERATURE DEVICE WHICH BENEFICIAL HIGH TEMPERATURE ENVIRONMENTS.
Figure 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] (SV-100-3) Dimensions shown millimeters
ORDERING GUIDE
Model AD9445BSVZ-125 AD9445BSVZ-1051 AD9445-IF-LVDS/PCB AD9445-BB-LVDS/PCB
Temperature Range -40°C +85°C -40°C +85°C
Package Description 100-Lead TQFP_EP 100-Lead TQFP_EP AD9445-125 (>100 MHz) LVDS Mode Evaluation Board AD9445-125 Baseband (<100 MHz) LVDS Mode Evaluation Board
Package Option SV-100-3 SV-100-3
Pb-free part.
Rev. Page
AD9445 NOTES
Rev. Page
AD9445 NOTES
Rev. Page
AD9445 NOTES
2005 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D05489-0-10/05(0)
Rev. Page
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