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eZ80L92
PS013012-1004 PRELIMINARY
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eZ80L92
Revision History
Each instance Table reflects change this document from previous revision. more detail, click appropriate link table.
Table Revision History this Document Revision Level Page
Date October 2004
Section
Description
Formatted current publication standards. Timer Control Registers External Memory Read Timing External Read Timing Real-Time Clock Oscillator Source Selection Clarified RST_EN descriptions. Correction label, Clock Rise Deassertion Delay, Figure Correction label, Clock Rise Deassertion Delay, Figure Clarified language describing drive frequency.
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Table Contents
Revision History .iii List Figures .viii List Tables Architectural Overview Features Block Diagram Description Characteristics Register eZ80® Core Features Improved Instructions Reset RESET Operation Low-Power Modes Overview SLEEP Mode HALT Mode Clock Peripheral Power-Down Registers General-Purpose Input/Output GPIO Overview GPIO Operation GPIO Interrupts GPIO Control Registers
Interrupt Controller Maskable Interrupts Nonmaskable Interrupts Chip Selects Wait States Memory Chip Selects Memory Chip Select Operation Chip Select Operation Wait States WAIT Input Signal Chip Selects During Request/Bus Acknowledge Cycles
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eZ80L92
Mode Controller eZ80 Mode Mode Intel Mode Motorola Mode Chip Select Registers Watch-Dog Timer Watch-Dog Timer Overview Watch-Dog Timer Operation Watch-Dog Timer Registers Programmable Reload Timers Programmable Reload Timers Overview Programmable Reload Timer Operation Programmable Reload Timer Registers Real-Time Clock Real-Time Clock Overview Real-Time Clock Alarm Real-Time Clock Oscillator Source Selection Real-Time Clock Battery Backup Real-Time Clock Recommended Operation Real-Time Clock Registers Universal Asynchronous Receiver/Transmitter UART Functional Description UART Interrupts UART Recommended Usage Baud Rate Generator Control Registers UART Registers Infrared Encoder/Decoder Functional Description Transmit Receive Jitter Infrared Encoder/Decoder Signal Pins Loopback Testing Serial Peripheral Interface Signals Functional Description Flags
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Baud Rate Generator Data Transfer Procedure with Configured Master Data Transfer Procedure with Configured Slave Registers Serial Interface General Characteristics Transferring Data Clock Synchronization Operating Modes Registers ZiLOG Debug Interface Introduction ZDI-Supported Protocol Clock Data Conventions Start Condition Register Addressing Write Operations Read Operations Operation eZ80L92 During Break Points Requests During Debug Mode Write-Only Registers Read-Only Registers Register Definitions On-Chip Instrumentation Introduction On-Chip Instrumentation Activation Interface Information Requests
eZ80® Instruction Op-Code On-Chip Oscillators Primary Crystal Oscillator Operation Real-Time Clock Crystal Oscillator Operation Electrical Characteristics Absolute Maximum Ratings Characteristics Characteristics External Memory Read Timing
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External Memory Write Timing External Read Timing External Write Timing Wait State Timing Read Operations Wait State Timing Write Operations General Purpose Port Input Sample Timing General Purpose Port Output Timing External Acknowledge Timing External System Clock Driver (PHI) Timing Part Number Description Precharacterization Product
Document Information Document Number Description Change Index Customer Feedback Form
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viii
List Figures
Figure eZ80L92 Block Diagram Figure 100-Pin LQFP Configuration eZ80L92 Figure GPIO Port Block Diagram Figure Memory Chip Select Example Figure Wait Input Sampling Block Diagram Figure Wait State Operation Example (Read Operation) Figure Mode Read Timing Example Figure Mode Write Timing Example Figure IntelBus Mode Signal Mapping Figure IntelBus Mode Read Timing Example (Separate Address Data Buses) Figure IntelBus Mode Write Timing Example (Separate Address Data Buses) Figure IntelBus Mode Read Timing Example (Multiplexed Address Data Bus) Figure IntelBus Mode Write Timing Example (Multiplexed Address Data Bus) Figure Motorola Mode Signal Mapping Figure Motorola Mode Read Timing Example Figure Motorola Mode Write Timing Example Figure Watch-Dog Timer Block Diagram Figure Programmable Reload Timer Block Diagram Figure Single Pass Mode Operation Example Figure Continuous Mode Operation Example Figure Timer Output Operation Example Figure Real-Time Clock 32KHz Oscillator Block Diagram Figure UART Block Diagram Figure Infrared System Block Diagram Figure Infrared Data Transmission
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List Figures
eZ80L92
Figure Infrared Data Reception Figure Master Device Figure Slave Device Figure Timing Figure Clock Data Relationship Figure START STOP Conditions Protocol Figure Frame Structure Figure Acknowledge Figure Clock Synchronization Protocol Figure Typical Debug Setup Figure Schematic Building Target Board ZPAK Connector Figure Write Timing Figure Read Timing Figure Address Write Timing Figure Single-Byte Data Write Timing Figure Block Data Write Timing Figure Single-Byte Data Read Timing Figure Block Data Read Timing Figure Recommended Crystal Oscillator Configuration (20MHz operation) Figure Recommended Crystal Oscillator Configuration (32KHz operation) Figure Frequency (Typical Figure WAIT (Typical Figure External Memory Read Timing Figure External Memory Write Timing Figure External Write Timing Figure External Read Timing Figure External Write Timing Figure Wait State Timing Read Operations Figure Wait State Timing Write Operations Figure Port Input Sample Timing
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eZ80L92
Figure GPIO Port Output Timing Figure 100-Lead Plastic Low-Profile Quad Flat Package (LQFP)
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List Tables
Table Revision History this Document .iii Table 100-Pin LQFP Identification eZ80L92 Device Table Characteristics eZ80L92 Table Register Table Clock Peripheral Power-Down Register Table Clock Peripheral Power-Down Register Table GPIO Mode Selection Table Port Data Registers Table Port Data Direction Registers Table Port Alternate Registers Table Port Alternate Registers Table Interrupt Vector Sources Priority Table Vectored Interrupt Operation Table Register Values Memory Chip Select Example Figure Table Mode Read States Table Mode Write States Table IntelBus Mode Read States (Separate Address Data Buses) Table IntelBus Mode Write States (Separate Address Data Buses) Table IntelBus Mode Read States (Multiplexed Address Data Bus) Table IntelBus Mode Write States (Multiplexed Address Data Bus). Table Motorola Mode Read States Table Motorola Mode Write States Table Chip Select Lower Bound Registers Table Chip Select Upper Bound Registers Table Chip Select Control Registers Table Chip Select Mode Control Registers Table Watch-Dog Timer Approximate Time-Out Delays Table Watch-Dog Timer Control Register
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Table Watch-Dog Timer Reset Register Table Single Pass Mode Operation Example. Table Continuous Mode Operation Example. Table Timer Operation Example. Table Timer Control Registers Table Timer Data Registers-Low Byte Table Timer Data Registers-High Byte Table Timer Reload Registers-Low Byte Table Timer Reload Registers-High Byte Table Timer Input Source Select Register Table Real-Time Clock Seconds Register Table Real-Time Clock Minutes Register Table Real-Time Clock Hours Register Table Real-Time Clock Day-of-the-Week Register. Table Real-Time Clock Day-of-the-Month Register Table Real-Time Clock Month Register Table Real-Time Clock Year Register Table Real-Time Clock Century Register Table Real-Time Clock Alarm Seconds Register Table Real-Time Clock Alarm Minutes Register. Table Real-Time Clock Alarm Hours Register Table Real-Time Clock Alarm Day-of-the-Week Register Table Real-Time Clock Alarm Control Register Table Real-Time Clock Control Register. Table UART Baud Rate Generator Registers-Low Byte. Table UART Baud Rate Generator Registers-High Byte Table UART Transmit Holding Registers Table UART Receive Buffer Registers Table UART Interrupt Enable Registers Table UART Interrupt Identification Registers
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xiii
Table UART Interrupt Status Codes Table UART FIFO Control Registers Table UART Line Control Registers Table UART Character Parameter Definition Table UART Modem Control Registers. Table UART Line Status Registers Table UART Modem Status Registers Table UART Scratch Registers Table GPIO Mode Selection when using IrDA Encoder/Decoder. Table Infrared Encoder/Decoder Control Register. Table Clock Phase Clock Polarity Operation Table Baud Rate Generator Register-Low Byte Table Baud Rate Generator Register-High Byte. Table Control Register. Table Status Register Table Transmit Shift Register Table Receive Buffer Register. Table Master Transmit Status Codes Table 10-Bit Master Transmit Status Codes Table Master Transmit Status Codes Data Bytes Table Master Receive Status Codes. Table Master Receive Status Codes Data Bytes Table Register Descriptions. Table Slave Address Register Table Extended Slave Address Register Table Data Register Table Control Registers Table Status Registers Table Status Codes. Table Clock Control Registers.
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Table Software Reset Register. Table Recommended Clock System Clock Frequency Table Write-Only Registers Table Read-Only Registers Table Address Match Registers Table Break Control Register Table Master Control Register Table Write Data Registers. Table Read/Write Control Register Functions Table Control Register. Table Instruction Store Registers Table 100. Write Memory Register Table 101. eZ80® Product Byte Register Table 102. eZ80® Product High Byte Register. Table 103. eZ80® Product Revision Register Table 104. Status Register Table 105. Read Registers-Low, High Upper Table 106. Control Register. Table 107. Read Memory Register Table 108. Pins Table 109. Arithmetic Instructions. Table 110. Manipulation Instructions. Table 111. Block Transfer Compare Instructions Table 112. Exchange Instructions Table 113. Input/Output Instructions Table 114. Load Instructions Table 115. Logical Instructions Table 116. Processor Control Instructions Table 117. Program Control Instructions Table 118. Rotate Shift Instructions
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Table 119. Code Map-First Code Table 120. Code Map-Second Code after 0CBh Table 121. Code Map-Second Code After 0DDh Table 122. Code Map-Second Code After 0EDh Table 123. Code Map-Second Code After 0FDh Table 124. Code Map-Fourth Byte After 0DDh, 0CBh, Table 125. Code Map-Fourth Byte After 0FDh, 0CBh, Table 126. Recommended Crystal Oscillator Specifications Operation). Table 127. Recommended Crystal Oscillator Specifications Operation) Table 128. Absolute Maximum Ratings Table 129. Characteristics Table 130. Characteristics Table 131. External Read Timing Table 132. External Read Timing Table 133. External Write Timing Table 134. GPIO Port Output Timing Table 135. Acknowledge Timing Table 136. System Clock Timing Table 137. Ordering Information
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Architectural Overview
eZ80L92 microcontroller high-speed single-cycle instruction-fetch microcontroller with maximum clock speed MHz. eZ80L92 member ZiLOG's eZ80Acclaim!family Flash microcontrollers. operate Z80-compatible addressing mode full 24-bit addressing mode MB). rich peripheral eZ80L92 makes suitable variety applications including industrial control, embedded communication, point-of-sale terminals.
Features
Single-cycle instruction fetch, high-performance, pipelined eZ80® core1 power features including SLEEP mode, HALT mode, selective peripheral power-down control UARTs with independent baud rate generators with independent clock rate generator with independent clock rate generator Infrared Data Association (IrDA)-compliant infrared encoder/decoder DMA-like eZ80® instructions efficient block data transfer Glueless external peripheral interface with Chip Selects, individual Wait State generators, external WAIT input pin-supports Intel-and Motorola-style buses Fixed-priority vectored interrupts (both internal external) interrupt controller Real-time clock with on-chip oscillator, selectable 50/60Hz input, separate battery backup 16-bit Counter/Timers with prescalers direct input/output drive Watch-Dog Timer bits General-Purpose JTAG debug interfaces 100-pin LQFP package 3.0-3.6 supply voltage with tolerant inputs Operating Temperature Range Standard: Extended:
simplicity, term eZ80® referred bulk this document.
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eZ80L92
Note: signals with overline active Low. example, B/W, which WORD active Low, B/W, which BYTE active Low. Power connections follow these conventional descriptions:
Connection Power Ground Circuit Device
Block Diagram
Figure illustrates block diagram eZ80L92 microcontroller.
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eZ80L92
Real-Time Clock Oscillator Serial Interface
RTC_VDD RTC_XIN RTC_XOUT
Controller
BUSACK BUSREQ INSTRD IORQ MREQ
MISO MOSI Serial Peripheral Interface (SPI) eZ80 RESET HALT_SLP
CTS0/1 DCD0/1 DSR0/1 DTR0/1 RI0/1 RTS0/1 RxD0/1 TxD0/1 Universal Asynchronous Receiver/ Transmitter (UART)
ZiLOG Debug Interface (JTAG/ZDI) Interrupt Vector [7:0] Interrupt Controller
JTAG/ZDI Signals
Chip Select Wait State Generator
WAIT
DATA[7:0] ADDR[23:0] 8-Bit General Purpose Port (GPIO) Crystal Oscillator System Clock Generator
IrDA Encoder/ Decoder
Programmable Reload Timer/Counters
Watch-Dog Timer (WDT)
PB[7:0]
Figure eZ80L92 Block Diagram
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T0_IN T1_IN T2_IN T3_IN T4_OUT T5_OUT
PC[7:0]
IR_TxD
IR_RxD
PD[7:0]
XOUT
Architectural Overview
eZ80L92
Description
Figure illustrates layout eZ80L92 100-pin LQFP package. Table describes pins their functions.
PB7/MOSI PB6/MISO PB5/T5_OUT PB4/T4_OUT PB3/SCK PB2/SS PB1/T1_IN PB0/T0_IN XOUT PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 PC2//RTS1 PC1/RxD1 PC0/TxD1 PS013012-1004 ADDR21 ADDR22 ADDR23 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 IORQ MREQ INSTRD WAIT ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20
100-Pin LQFP
PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0 PD1/RxD0/IR_RXD PD0/TxD0/IR_TXD TRIGOUT RTC_VDD RTC_XOUT RTC_XIN HALT_SLP BUSACK BUSREQ RESET
Figure 100-Pin LQFP Configuration eZ80L92
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Architectural Overview
eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device Symbol ADDR0 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR1
Address
Bidirectional
ADDR2
Address
Bidirectional
ADDR3
Address
Bidirectional
ADDR4
Address
Bidirectional
ADDR5
Address
Bidirectional
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eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol ADDR6 Function Power Supply Ground Address Bidirectional Signal Direction Description Power Supply. Ground. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR7
Address
Bidirectional
ADDR8
Address
Bidirectional
ADDR9
Address
Bidirectional
ADDR10
Address
Bidirectional
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Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol ADDR11 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Power Supply. Ground. Bidirectional Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR12
Address
Bidirectional
ADDR13
Address
Bidirectional
ADDR14
Address
Bidirectional
ADDR15
Power Supply Ground Address
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Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol ADDR16 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR17
Address
Bidirectional
ADDR18
Address
Bidirectional
ADDR19
Address
Bidirectional
ADDR20
Address
Bidirectional
ADDR21
Address
Bidirectional
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eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol ADDR22 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. indicates that access occurring defined memory address space. indicates that access occurring defined memory address space. indicates that access occurring defined memory address space. indicates that access occurring defined memory address space. Power Supply. Ground. Bidirectional data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master. data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master.
ADDR23
Address
Bidirectional
Chip Select
Output, Active
Chip Select
Output, Active
Chip Select
Output, Active
Chip Select
Output, Active
DATA0
Power Supply Ground Data
DATA1
Data
Bidirectional
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Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol DATA2 Function Data Signal Direction Bidirectional Description data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master. data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master. data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master. data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master. data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master. data transfers data from memory devices. eZ80L92 drives these lines only during Write cycles when eZ80L92 master. Power Supply. Ground. Bidirectional, Active IORQ indicates that accessing location space. indicate type access. eZ80L92 does drive this line during RESET. input acknowledge cycles. MREQ indicates that accessing location memory. INSTRD signals indicate type access. eZ80L92 does drive this line during RESET. input acknowledge cycles.
DATA3
Data
Bidirectional
DATA4
Data
Bidirectional
DATA5
Data
Bidirectional
DATA6
Data
Bidirectional
DATA7
Data
Bidirectional
IORQ
Power Supply Ground Input/Output Request
MREQ
Memory Request
Bidirectional, Active
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eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function Read Signal Direction Output, Active Description indicates that eZ80L92 reading from current address location. This tristated during acknowledge cycles. indicates that writing current address location. This tristated during acknowledge cycles. INSTRD (with MREQ indicates eZ80L92 fetching instruction from memory. This tristated during acknowledge cycles. Driving WAIT forces wait additional clock cycles external peripheral external memory complete Read Write operation.
Write
Output, Active
INSTRD
Instruction Output, Active Read Indicator
WAIT
WAIT Request Input, Active
RESET
Reset
Schmitt Trigger Input, This signal used initialize eZ80L92 Active MCU. This input must minimum system clock cycles, must held until clock stable. This input includes Schmitt trigger allow rise times.
Nonmaskable Schmitt Trigger Input, input higher priority input than Interrupt Active maskable interrupts. always recognized instruction, regardless state interrupt enable control bits. This input includes Schmitt trigger allow rise times. Request Input, Active External devices request eZ80L92 release memory interface their use, driving this Low. eZ80L92 responds BUSREQ, tristating address, data, control signals, driving BUSACK line Low. During acknowledge cycles ADDR[23:0], IORQ, MREQ inputs. this indicates that entered either HALT SLEEP mode because execution either HALT instruction.
BUSREQ
BUSACK
Acknowledge
Output, Active
HALT_SLP HALT SLEEP Indicator
Output, Active
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Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol RTC_XIN Function Power Supply Ground Real-Time Clock Crystal Input Input Signal Direction Description Power Supply. Ground. This input low-power 32KHz crystal oscillator Real-Time Clock. This output from low-power 32KHz crystal oscillator Real-Time Clock. This input when configured operate from 50/60 input clock signals crystal oscillator disabled. Power supply Real-Time Clock associated 32KHz oscillator. Isolated from power supply remainder chip. battery connected this supply constant power Real-Time Clock 32KHz oscillator. Ground. Input Input JTAG Mode Select Input. JTAG clock input. Active High trigger event indicator. JTAG data input pin. Functions data when JTAG disabled. JTAG data output pin. Power Supply.
RTC_XOUT Real-Time Clock Crystal Output
Bidirectional
RTC_VDD
Real-Time Clock Power Supply
TRIGOUT
Ground JTAG Test Mode Select JTAG Test Clock
JTAG Test Output Trigger Output JTAG Test Data JTAG Test Data Power Supply Bidirectional Output
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Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART transmit asynchronous serial data. This signal multiplexed with PD0. This used IrDA encoder/ decoder transmit serial data. This signal multiplexed with PD0. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART receive asynchronous serial data. This signal multiplexed with PD1. This used IrDA encoder/ decoder receive serial data. This signal multiplexed with PD1. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal from UART. This signal multiplexed with PD2.
TxD0
UART Output Transmit Data IrDA Transmit Output Data GPIO Port Bidirectional
IR_TXD
RxD0
Receive Data
Input
IR_RXD
IrDA Receive Data GPIO Port
Input
Bidirectional
RTS0
Request Send
Output, Active
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Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD3. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal UART. This signal multiplexed with PD4. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD5. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD6.
CTS0
Clear Send Input, Active GPIO Port Bidirectional
DTR0
Data Terminal Output, Active Ready GPIO Port Bidirectional
DSR0
Data Ready GPIO Port
Input, Active Bidirectional
DCD0
Data Carrier Detect
Input, Active
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eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD7. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART transmit asynchronous serial data. This signal multiplexed with PC0. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART receive asynchronous serial data. This signal multiplexed with PC1.
Ring Indicator Input, Active GPIO Port Bidirectional
TxD1
Transmit Data Output
GPIO Port
Bidirectional
RxD1
Receive Data
Input
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eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal from UART. This signal multiplexed with PC2. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC3. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal UART. This signal multiplexed with PC4. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC5.
RTS1
Request Send GPIO Port
Output, Active Bidirectional
CTS1
Clear Send Input, Active GPIO Port Bidirectional
DTR1
Data Terminal Output, Active Ready GPIO Port Bidirectional
DSR1
Data Ready
Input, Active
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eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC6. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC7. Ground. This input onboard crystal oscillator primary system clock. external oscillator used, clock output should connected this pin. When crystal used, should connected between XOUT. This output onboard crystal oscillator. When used, crystal should connected between XOUT. Power Supply.
DCD1
Data Carrier Detect GPIO Port
Input, Active Bidirectional
Ring Indicator Input, Active Ground System Clock Input Oscillator Input
XOUT
System Clock Output Oscillator Output Power Supply
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Architectural Overview
eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Alternate clock source Programmable Reload Timers This signal multiplexed with PB0. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Alternate clock source Programmable Reload Timers This signal multiplexed with PB1. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. slave select input line used select slave device mode. This signal multiplexed with PB2. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. serial clock. This signal multiplexed with PB3.
T0_IN
Timer
Input
GPIO Port
Bidirectional
T1_IN
Timer
Input
GPIO Port
Bidirectional
Slave Select
Input, Active
GPIO Port
Bidirectional
Serial Clock
Bidirectional
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Architectural Overview
eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Programmable Reload Timer timer-out signal. This signal multiplexed with PB4. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Programmable Reload Timer timer-out signal. This signal multiplexed with PB5. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. MISO line configured input when eZ80L92 master device output when eZ80L92 slave device. This signal multiplexed with PB6.
T4_OUT
Timer GPIO Port
Output Bidirectional
T5_OUT
Timer GPIO Port
Output Bidirectional
MISO
Master Slave
Bidirectional
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Architectural Overview
eZ80L92
Table 100-Pin LQFP Identification eZ80L92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. MOSI line configured output when eZ80L92 master device input when eZ80L92 slave device. This signal multiplexed with PB7. Power Supply. Ground. This carries data signal. This used receive transmit clock. This output driven internal system clock.
MOSI
Master Slave
Bidirectional
Power Supply Ground Serial Data Bidirectional Serial Clock Bidirectional
System Clock Output
Characteristics
Table describes characteristics each eZ80L92 MCU's 100-pin LQFP package.
Table Characteristics eZ80L92 Schmitt Trigger Open Input Drain/Source
Symbol ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5
Reset Active Direction Direction Low/High
Tristate Pull Output Up/Down
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Architectural Overview
eZ80L92
Table Characteristics eZ80L92 (Continued) Schmitt Trigger Open Input Drain/Source
Symbol ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 DATA0
Reset Active Direction Direction Low/High
Tristate Pull Output Up/Down
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Architectural Overview
eZ80L92
Table Characteristics eZ80L92 (Continued) Schmitt Trigger Open Input Drain/Source
Symbol DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 IORQ MREQ INSTRD WAIT RESET BUSREQ BUSACK HALT_SLP RTC_XIN RTC_XOUT RTC_VDD
Reset Active Direction Direction Low/High
Tristate Pull Output Up/Down
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Architectural Overview
eZ80L92
Table Characteristics eZ80L92 (Continued) Schmitt Trigger Open Input Drain/Source
Symbol
Reset Active Direction Direction Low/High Rising (In) Falling (Out) High
Tristate Pull Output Up/Down
TRIGOUT XOUT
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Architectural Overview
eZ80L92
Table Characteristics eZ80L92 (Continued) Schmitt Trigger Open Input Drain/Source
Symbol
Reset Active Direction Direction Low/High
Tristate Pull Output Up/Down
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Architectural Overview
eZ80L92
Register
on-chip peripheral registers accessed address space. operations employ 16-bit addresses. upper byte 24-bit address undefined during operations (ADDR[23:16] UU). operations using 16-bit addresses within range 0080h-00FFh routed on-chip peripherals. External Chip Selects generated address space programmed Chip Selects overlaps 0080h-00FFh address range. Registers unused addresses within 0080h-00FFh range assigned on-chip peripherals implemented. Read access such addresses returns unpredictable values Write access produces effect. Table diagrams register eZ80L92.
Table Register Address (hex) Mnemonic Reset (hex) Access Page
Name
Programmable Reload Counter/Timers 0080 0081 TMR0_CTL TMR0_DR_L TMR0_RR_L 0082 TMR0_DR_H TMR0_RR_H 0083 0084 TMR1_CTL TMR1_DR_L TMR1_RR_L 0085 TMR1_DR_H TMR1_RR_H 0086 TMR2_CTL Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read-only locked; Read/Write unlocked. After external reset reset, Control register reset x0xxxx00b. After Alarm Sleep-Mode Recovery reset, Control register reset x0xxxx10b.
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eZ80L92
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Access Page
Name
Programmable Reload Counter/Timers 0087 TMR2_DR_L TMR2_RR_L 0088 TMR2_DR_H TMR2_RR_H 0089 008A TMR3_CTL TMR3_DR_L TMR3_RR_L 008B TMR3_DR_H TMR3_RR_H 008C 008D TMR4_CTL TMR4_DR_L TMR4_RR_L 008E TMR4_DR_H TMR4_RR_H 008F 0090 TMR5_CTL TMR5_DR_L TMR5_RR_L 0091 TMR5_DR_H TMR5_RR_H 0092 TMR_ISS Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Input Source Select Register
Watch-Dog Timer 0093 0094 WDT_CTL WDT_RR Watch-Dog Timer Control Register1 Watch-Dog Timer Reset Register 00/20
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read-only locked; Read/Write unlocked. After external reset reset, Control register reset x0xxxx00b. After Alarm Sleep-Mode Recovery reset, Control register reset x0xxxx10b.
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eZ80L92
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Access Page
Name Port Data Register2 Port Data Direction Register Port Alternate Register Port Alternate Register Port Data Register Port Data Direction Register Port Alternate Register Port Alternate Register Port Data Register Port Data Direction Register Port Alternate Register Port Alternate Register
General-Purpose Input/Output Ports 009A 009B 009C 009D 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 PB_DR PB_DDR PB_ALT1 PB_ALT2 PC_DR PC_DDR PC_ALT1 PC_ALT2 PD_DR PD_DDR PD_ALT1 PD_ALT2 R/W2 R/W2
Chip Select/Wait State Generator 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00B0 00B1 CS0_LBR CS0_UBR CS0_CTL CS1_LBR CS1_UBR CS1_CTL CS2_LBR CS2_UBR CS2_CTL CS3_LBR Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register Chip Select Lower Bound Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read-only locked; Read/Write unlocked. After external reset reset, Control register reset x0xxxx00b. After Alarm Sleep-Mode Recovery reset, Control register reset x0xxxx10b.
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Register
eZ80L92
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Access Page
Name
Chip Select/Wait State Generator 00B2 00B3 CS3_UBR CS3_CTL Chip Select Upper Bound Register Chip Select Control Register
Serial Peripheral Interface (SPI) Block 00B8 00B9 00BA 00BB 00BC SPI_BRG_L SPI_BRG_H SPI_CTL SPI_SR SPI_TSR SPI_RBR Baud Rate Generator Register-Low Byte Baud Rate Generator Register-High Byte Control Register Status Register Transmit Shift Register Receive Buffer Register
Infrared Encoder/Decoder Block 00BF IR_CTL Infrared Encoder/Decoder Control
Universal Asynchronous Receiver/Transmitter (UART0) Block 00C0 UART0_RBR UART0_THR UART0_BRG_L 00C1 UART0_IER UART Receive Buffer Register UART Transmit Holding Register UART Baud Rate Generator Register- Byte UART Interrupt Enable Register
UART0_BRG_H UART Baud Rate Generator Register- High Byte 00C2 UART0_IIR UART0_FCTL 00C3 UART0_LCTL UART Interrupt Identification Register UART FIFO Control Register UART Line Control Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read-only locked; Read/Write unlocked. After external reset reset, Control register reset x0xxxx00b. After Alarm Sleep-Mode Recovery reset, Control register reset x0xxxx10b.
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Register
eZ80L92
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Access Page
Name
Universal Asynchronous Receiver/Transmitter (UART0) Block 00C4 00C5 00C6 00C7 UART0_MCTL UART0_LSR UART0_MSR UART0_SPR UART Modem Control Register UART Line Status Register UART Modem Status Register UART Scratch Register
I<SuperscriptBold>2C Block 00C8 00C9 00CA 00CB 00CC I2C_SAR I2C_XSAR I2C_DR I2C_CTL I2C_SR I2C_CCR 00CD I2C_SRR Slave Address Register Extended Slave Address Register Data Register Control Register Status Register Clock Control Register Software Reset Register
Universal Asynchronous Receiver/Transmitter (UART1) Block 00D0 UART1_RBR UART1_THR UART1_BRG_L 00D1 UART1_IER UART Receive Buffer Register UART Transmit Holding Register UART Baud Rate Generator Register- Byte UART Interrupt Enable Register
UART1_BRG_H UART Baud Rate Generator Register- High Byte 00D2 UART1_IIR UART1_FCTL 00D3 00D4 UART1_LCTL UART1_MCTL UART Interrupt Identification Register UART FIFO Control Register UART Line Control Register UART Modem Control Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read-only locked; Read/Write unlocked. After external reset reset, Control register reset x0xxxx00b. After Alarm Sleep-Mode Recovery reset, Control register reset x0xxxx10b.
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eZ80L92
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Access Page
Name
Universal Asynchronous Receiver/Transmitter (UART1) Block 00D5 00D6 00D7 UART1_LSR UART1_MSR UART1_SPR UART Line Status Register UART Modem Status Register UART Scratch Register
Low-Power Control 00DB 00DC CLK_PPD1 CLK_PPD2 Clock Peripheral Power-Down Register Clock Peripheral Power-Down Register
Real-Time Clock 00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED RTC_SEC RTC_MIN RTC_HRS RTC_DOW RTC_DOM RTC_MON RTC_YR RTC_CEN RTC_ASEC RTC_AMIN RTC_AHRS RTC_ADOW RTC_ACTRL RTC_CTRL Seconds Register3 Minutes Register Hours Register Day-of-the-Week Register Day-of-the-Month Register Month Register Year Register Century Register Alarm Seconds Register Alarm Minutes Register Alarm Hours Register Alarm Day-of-the-Week Register Alarm Control Register Control Register4 x0xxxx00b/ x0xxxx10b R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read-only locked; Read/Write unlocked. After external reset reset, Control register reset x0xxxx00b. After Alarm Sleep-Mode Recovery reset, Control register reset x0xxxx10b.
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Register
eZ80L92
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Access Page
Name
Chip Select Mode Control 00F0 00F1 00F2 00F3 CS0_BMC CS1_BMC CS2_BMC CS3_BMC Chip Select Mode Control Register Chip Select Mode Control Register Chip Select Mode Control Register Chip Select Mode Control Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read-only locked; Read/Write unlocked. After external reset reset, Control register reset x0xxxx00b. After Alarm Sleep-Mode Recovery reset, Control register reset x0xxxx10b.
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Register
eZ80L92
eZ80® Core
eZ80® first 8-bit microprocessor support linear addressing. Each software module task under real-time executive operating system operate Z80-compatible mode full 24-bit address mode. eZ80® instruction superset instruction sets Z180 CPUs. Z180 programs executed eZ80® with little modification.
Features
Code-compatible with Z180 products 24-bit linear address space Single-cycle instruction fetch Pipelined fetch, decode, execute Dual Stack Pointers (24-bit) (16-bit) memory modes 24-bit registers (Arithmetic Logic Unit) Debug support Nonmaskable Interrupt (NMI), plus support maskable vectored interrupts
Improved Instructions
Four block transfer instructions provide DMA-like operations memory memory transfers. These instructions are: INDRX (input from I/O, decrement memory address, leave address unchanged, repeat) INIRX (input from I/O, increment memory address, leave address unchanged, repeat) OTDRX (output I/O, decrement memory address, leave address unchanged, repeat) OTIRX (output I/O, increment memory address, leave address unchanged, repeat) Four other block transfer instructions modified improve performance relative eZ80190 device. These modified instructions are: IND2R (input from I/O, decrement memory address, decrement address, repeat)
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eZ80® Core
eZ80L92
INI2R (input from I/O, increment memory address, increment address, repeat) OTD2R (output I/O, decrement memory address, decrement address, repeat) OTI2R (output I/O, increment memory address, increment address, repeat)
more information about eZ80® CPU, instruction set, eZ80® programming, please refer eZ80 User Manual. more information about eZ80190, please refer eZ80190 Product Specification.
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eZ80® Core
eZ80L92
Reset
RESET Operation
RESET controller within eZ80L92 provides consistent system reset (RESET) function type resets that affect system. There events which cause RESET:
External RESET assertion Watch-Dog Timer (WDT) time-out when configured generate RESET Real-Time Clock alarm with eZ80® low-power SLEEP mode Execution Debug RESET command
During RESET, internal RESET mode timer holds system RESET system clock (SCLK) cycles. RESET mode timer begins incrementing next rising edge SCLK following deactivation RESET events (RESET pin, Watch-Dog Timer, Real-Time Clock, Debugger) Note: User must determine SCLK cycles provides sufficient time primary crystal oscillator stabilize. RESET, external RESET pin, must always executed following application power (VDD ramp). Without RESET following power-up, proper operation eZ80L92 cannot guaranteed.
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Reset
eZ80L92
Low-Power Modes
Overview
eZ80L92 provides range power-saving features. highest level power reduction provided SLEEP mode. next level power reduction provided HALT instruction. lowest level power reduction provided clock peripheral power-down registers.
SLEEP Mode
Execution eZ80® CPU's instruction places eZ80L92 into SLEEP mode. SLEEP mode, operating characteristics are:
Primary crystal oscillator disabled System clock disabled eZ80® idle Program counter (PC) stops incrementing crystal oscillator continues operate drive Real-Time Clock Watch-Dog Timer configured operate from oscillator)
eZ80® brought SLEEP mode following operations:
RESET external RESET driven RESET Real-Time Clock alarm RESET Watch-Dog Timer time-out running oscillator configured generate RESET upon time-out) RESET execution Debug RESET command
After exiting SLEEP mode, standard RESET delay occurs allow primary crystal oscillator stabilize. Refer Reset section more information.
HALT Mode
Execution eZ80® CPU's HALT instruction places eZ80L92 into HALT mode. HALT mode, operating characteristics are:
Primary crystal oscillator enabled continues operate System clock enabled continues operate
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Low-Power Modes
eZ80L92
eZ80® idle Program counter (PC) stops incrementing
eZ80® brought HALT mode following operations: Nonmaskable interrupt (NMI) Maskable interrupt RESET external RESET driven Watch-Dog Timer time-out configured generate either RESET upon time-out) RESET execution Debug RESET command
minimize current HALT mode, system clock should disabled unused on-chip peripherals Clock Peripheral Power-Down Registers.
Clock Peripheral Power-Down Registers
reduce power, Clock Peripheral Power-Down Registers allow system clock disabled unused on-chip peripherals. Upon RESET, peripherals enabled. clock unused peripherals disabled setting appropriate Clock Peripheral Power-Down Registers When powered down, peripherals completely disabled. reenable, Clock Peripheral Power-Down Registers must cleared Many peripherals feature separate enable/disable control bits that must appropriately operation. These peripheral specific enable/disable bits provide same level power reduction Clock Peripheral Power-Down Registers. When powered down, standard peripheral control registers accessible Read Write access. Tables
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Low-Power Modes
eZ80L92
Table Clock Peripheral Power-Down Register (CLK_PPD1 00DBh) Reset Access
Note: Read/Write; Read Only.
Position GPIO_D_OFF GPIO_C_OFF GPIO_B_OFF SPI_OFF I2C_OFF UART1_OFF UART0_OFF
Value Description System clock GPIO Port powered down. Port alternate functions operate correctly. System clock GPIO Port powered System clock GPIO Port powered down. Port alternate functions operate correctly. System clock GPIO Port powered System clock GPIO Port powered down. Port alternate functions operate correctly. System clock GPIO Port powered Reserved. System clock powered down. System clock powered System clock powered down. System clock powered System clock UART1 powered down. System clock UART1 powered System clock UART0 IrDA endec powered down. System clock UART0 IrDA endec powered
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Low-Power Modes
eZ80L92
Table Clock Peripheral Power-Down Register (CLK_PPD2 00DCh) Reset Access
Note: Read/Write; Read Only.
Position PHI_OFF PRT5_OFF PRT4_OFF PRT3_OFF PRT2_OFF PRT1_OFF PRT0_OFF
Value Description Clock output disabled (output high-impedance). Clock output enabled. Reserved. System clock PRT5 powered down. System clock PRT5 powered System clock PRT4 powered down. System clock PRT4 powered System clock PRT3 powered down. System clock PRT3 powered System clock PRT2 powered down. System clock PRT2 powered System clock PRT1 powered down. System clock PRT1 powered System clock PRT0 powered down. System clock PRT0 powered
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Low-Power Modes
eZ80L92
General-Purpose Input/Output
GPIO Overview
eZ80L92 features General-Purpose Input/Output (GPIO) pins. GPIO pins assembled three 8-bit ports- Port Port Port port signals configured either inputs outputs. addition, port pins used vectored interrupt sources eZ80® CPU.
GPIO Operation
GPIO operation same GPIO ports (Ports Each port features eight GPIO port pins. operating mode each controlled four bits that divided between four 8-bit registers. These GPIO mode control registers are:
Port Data Register (Px_DR) Port Data Direction Register (Px_DDR) Port Alternate Register (Px_ALT1) Port Alternate Register (Px_ALT2)
where representing three GPIO ports mode each controlled setting each register pertinent configured. example, operating mode Port (PB7), values contained PB_DR[7], PB_DDR[7], PB_ALT1[7], PB_ALT2[7]. combination GPIO control register bits allows individual configuration each port nine modes. modes, reading Port Data register returns sampled state, level, signal corresponding pin. Table indicates function each port signal based upon these four register bits. After RESET event, GPIO port pins configured standard digital inputs, with interrupts disabled.
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General-Purpose Input/Output
eZ80L92
Table GPIO Mode Selection GPIO Px_ALT2 Mode Bits7:0 Px_ALT1 Px_DDR Px_DR Bits7:0 Bits7:0 Bits7:0 Port Mode Output Output Input from Input from Open-Drain output Open-Drain Open source Open source output Reserved Interrupt-dual edge triggered
Output High impedance High impedance High impedance High impedance High impedance High impedance
Port D-alternate function controls port I/O. Port D-alternate function controls port I/O. Interrupt-active Interrupt-active High High impedance High impedance
Interrupt-falling edge triggered High impedance Interrupt-rising edge triggered High impedance
GPIO Mode port configured standard digital output pin. value writ-
Port Data register (Px_DR) presented pin.
GPIO Mode port configured standard digital input pin. output
tristated (high impedance). value stored Port Data register produces effect. modes, Read from Port Data register returns pin's value. GPIO Mode default operating mode following RESET.
GPIO Mode port configured open-drain I/O. GPIO pins feature
internal pull-up supply voltage. employ GPIO OPEN-DRAIN mode, external pull-up resistor must connect supply voltage. Writing Port Data register outputs pin. Writing Port Data register results high-impedance output.
GPIO Mode port configured open-source I/O. GPIO pins fea-
ture internal pull-down supply ground. employ GPIO OPENSOURCE mode, external pull-down resistor must connect supply ground.
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General-Purpose Input/Output
eZ80L92
Writing Port Data register outputs High pin. Writing Port Data register results high-impedance output.
GPIO Mode Reserved. This produces high-impedance output. GPIO Mode This enables dual edge-triggered interrupt mode. Both rising
falling edge cause interrupt request sent eZ80® CPU. Writing Port Data register position resets corresponding interrupt request. Writing produces effect. programmer must Port Data register before entering edge-triggered interrupt mode.
GPIO Mode Ports port configured pass control over
alternate (secondary) functions assigned pin. example, alternate mode function alternate mode function Timer Out. When GPIO Mode enabled, output data tristated control come from alternate function's data output tristate control, respectively. value Port Data register produces effect operation. Note: Input signals sampled system clock before being passed alternate function input.
GPIO Mode port configured level-sensitive interrupt modes. interrupt
request generated when level same level stored Port Data register. port value sampled system clock. input must held selected interrupt level minimum clock periods initiate interrupt. interrupt request remains active long this condition maintained external source.
GPIO Mode port configured single edge-triggered interrupt mode.
value Port Data register determines positive negative edge causes interrupt request. Port Data register sets selected generate interrupt request falling edges. Port Data register sets selected generate interrupt request rising edges. interrupt request remains active until written corresponding interrupt request Port Data register bit. Writing produces effect operation. programmer must Port Data register before entering edge-triggered interrupt mode. simplified block diagram GPIO port illustrated Figure
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General-Purpose Input/Output
eZ80L92
GPIO Register Data (Input)
System Clock Mode Mode Data System Clock GPIO Register Data (Output) Mode Mode Port
Figure GPIO Port Block Diagram
GPIO Interrupts
Each port used interrupt source. Interrupts either level- edgetriggered. Level-Triggered Interrupts When port configured level-triggered interrupts, corresponding port tristated. interrupt request generated when level same level stored Port Data register. port value sampled system clock. input must held selected interrupt level minimum consecutive clock cycles initiate interrupt. interrupt request remains active long this condition maintained external source. example, programmed low-level interrupt forced consecutive clock cycles, interrupt request signal generated from that port sent eZ80® CPU. interrupt request signal remains active until external device driving forces High. Edge-Triggered Interrupts When port configured edge-triggered interrupts, corresponding port tristated. receives correct edge from external device, port generates interrupt request signal eZ80® CPU. time port configured
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General-Purpose Input/Output
eZ80L92
edge-triggered interrupt, writing that pin's Port Data register causes reset edge-detected interrupt. programmer must Port Data register before entering either single dual edge-triggered interrupt mode that port pin. When configured dual edge-triggered interrupt mode (GPIO Mode both rising falling edge cause interrupt request sent eZ80® CPU. When configured single edge-triggered interrupt mode (GPIO Mode value Port Data register determines positive negative edge causes interrupt request. Port Data register sets selected generate interrupt request falling edges. Port Data register sets selected generate interrupt request rising edges.
GPIO Control Registers
GPIO Control Registers operate groups four with each Port Each GPIO port features Port Data register, Port Data Direction register, Port Alternate register Port Alternate register Port Data Registers When port pins configured output modes, data written Port Data registers, detailed Table driven corresponding pins. modes, reading from Port Data registers always returns current sampled value corresponding pins. When port pins configured edge-triggered interrupt sources, writing corresponding Port Data register clears interrupt signal that sent eZ80® CPU. When port pins configured edge-selectable interrupts level-sensitive interrupts, value written Port Data register selects interrupt edge interrupt level. Table more information.
Table Port Data Registers (PB_DR 009Ah, PC_DR 009Eh, PD_DR 00A2h) Reset Access
Note: Undefined; Read/Write.
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General-Purpose Input/Output
eZ80L92
Port Data Direction Registers conjunction with other GPIO Control Registers, Port Data Direction registers, detailed Table control operating modes GPIO port pins. Table more information.
Table Port Data Direction Registers (PB_DDR 009Bh, PC_DDR 009Fh, PD_DDR 00A3h) Reset Access
Note: Read/Write.
Port Alternate Register conjunction with other GPIO Control Registers, Port Alternate Register detailed Table control operating modes GPIO port pins. Table more information.
Table Port Alternate Registers (PB_ALT1 009Ch, PC_ALT1 00A0h, PD_ALT1 00A4h) Reset Access
Note: Read/Write.
Port Alternate Register conjunction with other GPIO Control Registers, Port Alternate Register detailed Table control operating modes GPIO port pins. Table more information.
Table Port Alternate Registers (PB_ALT2 009Dh, PC_ALT2 00A1h, PD_ALT2 00A5h) Reset Access
Note: Read/Write.
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General-Purpose Input/Output
eZ80L92
Interrupt Controller
interrupt controller eZ80L92 routes interrupt request signals from internal peripherals external devices (via GPIO pins) eZ80® CPU.
Maskable Interrupts
eZ80L92, maskable interrupts eZ80® CPU's vectored interrupt function. Table lists low-byte vector each maskable interrupt sources. maskable interrupt sources listed order their priority, with vector being highest-priority interrupt. full 16-bit interrupt vector located starting address {I[7:0], IVECT[7:0]} where I[7:0] eZ80® CPU's Interrupt Page Address Register.
Table Interrupt Vector Sources Priority Vector Source Unused Unused Unused Unused Unused UART Vector Source UART Unused Unused Unused Unused Unused Unused Unused Unused Port Port Vector Source Port Port Port Port Port Port Port Port Port Port Port Port Port Vector Source Port Port Port Port Port Port Port Port Port Unused Unused Unused Unused
Note: Absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, reserved hardware reset, NMI, instruction.
user's program should store interrupt service routine starting address twobyte interrupt vector locations. example, mode two-byte address interrupt service routine would stored {00h, I[7:0], 1Eh} {00h, I[7:0], 1Fh}. mode, two-byte address interrupt service routine would stored
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Interrupt Controller
eZ80L92
{MBASE[7:0], I[7:0], 1Eh} {MBASE, I[7:0], 1Fh}. least significant byte stored lower address. When more interrupt requests (IRQs) become active, interrupt request generated interrupt controller sent CPU. corresponding 8-bit interrupt vector highest priority interrupt placed 8-bit interrupt vector bus, IVECT[7:0]. interrupt vector internal eZ80L92 therefore visible externally. response time eZ80® interrupt request function current instruction being executed well number WAIT states being asserted. interrupt vector, {I[7:0], IVECT[7:0]}, visible address bus, ADDR[15:0], when interrupt service routine begins. response eZ80® vectored interrupt eZ80L92 explained Table Interrupt sources required active until Interrupt Service Routine (ISR) starts. recommended that Interrupt Page Address Register value changed user from default value this address create conflicts between nonmaskable interrupt vector, instruction addresses, maskable interrupt vectors.
Table Vectored Interrupt Operation Memory Mode Mode MADL Operation Read interrupt vector placed internal vectored interrupt bus, IVECT [7:0], interrupting peripheral. IEF1 IEF2 starting Program Counter effectively {MBASE, PC[15:0]}. Push 2-byte return address PC[15:0] onto ({MBASE,SPS}) stack. mode remains cleared interrupt vector address located MBASE, I[7:0], IVECT[7:0] PC[15:0] MBASE, I[7:0], IVECT[7:0] ending Program Counter effectively {MBASE, PC[15:0]} interrupt service routine must with RETI. Read interrupt vector placed internal vectored interrupt bus, IVECT [7:0], interrupting peripheral. IEF1 IEF2 starting Program Counter PC[23:0]. Push 3-byte return address, PC[23:0], onto stack. mode remains interrupt vector address located 00h, I[7:0], IVECT[7:0] PC[15:0] 00h, I[7:0], IVECT[7:0] ending Program Counter 00h, PC[15:0] interrupt service routine must with RETI.
Mode
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Table Vectored Interrupt Operation (Continued) Memory Mode Mode MADL Operation Read interrupt vector placed internal vectored interrupt bus, IVECT[7:0], interrupting peripheral. IEF1 IEF2 starting Program Counter effectively {MBASE, PC[15:0]}. Push 2-byte return address, PC[15:0], onto stack. Push byte onto stack indicate interrupt from mode (because mode interrupt vector address located 00h, I[7:0], IVECT[7:0] PC[15:0] 00h, I[7:0], IVECT[7:0] ending Program Counter 00h, PC[15:0] interrupt service routine must with RETI.L Read interrupt vector placed internal vectored interrupt bus, IVECT [7:0], interrupting peripheral. IEF1 IEF2 starting Program Counter PC[23:0]. Push 3-byte return address, PC[23:0], onto stack. Push byte onto stack indicate restart from mode (because mode remains interrupt vector address located {00h, I[7:0], IVECT[7:0]}. PC[15:0] 00h, I[7:0], IVECT[7:0] ending Program Counter 00h, PC[15:0] interrupt service routine must with RETI.L
Mode
Nonmaskable Interrupts
active input generates interrupt request eZ80® CPU. This nonmaskable interrupt always serviced eZ80® CPU, regardless state Interrupt Enable flags (IEF1 IEF2). nonmaskable interrupt prioritized higher than maskable interrupts. response eZ80® nonmaskable interrupt described detail eZ80® User Manual (UM0077).
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Chip Selects Wait States
eZ80L92 generates four Chip Selects external devices. Each Chip Select programmed access either memory space space. Memory Chip Selects individually programmed boundary. Chip Selects each choose 256-byte section space. addition, each Chip Select programmed wait states.
Memory Chip Selects
Each Chip Selects enabled either memory address space address space, both. select memory address space particular Chip Select, CSx_IO (CSx_CTL[4]) must reset select address space particular Chip Select, CSx_IO must After RESET, default Chip Selects configured memory address space. either memory address space address space, individual Chip Selects must enabled setting CSx_EN (CSx_CTL[3])
Memory Chip Select Operation
Operation each Memory Chip Selects controlled three control registers. enable particular Memory Chip Select, following conditions must met:
Chip Select enabled setting CSx_EN Chip Select configured Memory clearing CSx_IO address associated Chip Select range: CSx_LBR[7:0] ADDR[23:16] CSx_UBR[7:0] higher priority (lower number) Chip Select meets above conditions memory access instruction must executing
foregoing conditions generate Memory Chip Select, then following actions occur:
appropriate Chip Select-CS0, CS1, CS2, CS3-is asserted (driven Low) MREQ asserted (driven Low) Depending upon instruction, either asserted (driven Low)
upper lower bounds same value (CSx_UBR CSx_LBR), then particular Chip Select valid single page.
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Memory Chip Select Priority lower-numbered Chip Select granted priority over higher-numbered Chip Select. example, address space Chip Select overlaps Chip Select address space, Chip Select active. RESET States RESET, Chip Select active addresses, because Lower Bound register resets Upper Bound register resets FFh. other Chip Select Lower Upper Bound registers reset 00h. Memory Chip Select Example Memory Chip Selects demonstrated Figure associated control register values indicated Table this example, Chip Selects enabled configured memory addresses. Also, overlaps with CS0. Because prioritized higher than CS1, active much defined address space.
Memory Location CS3_UBR CS3_LBR CS2_UBR CS2_LBR CS1_UBR Active Address Space Active Address Space Active Address Space FFFFFFh D00000h CFFFFFh A00000h 9FFFFFh 800000h 7FFFFFh
CS0_UBR
Active Address Space
CS0_LBR CS1_LBR
000000h
Figure Memory Chip Select Example
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Table Register Values Memory Chip Select Example Figure Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO CSx_LBR CSx_UBR Description enabled Memory Chip Select. Valid addresses range from 000000h- 7FFFFFh. enabled Memory Chip Select. Valid addresses range from 800000h- 9FFFFFh. enabled Memory Chip Select. Valid addresses range from A00000h- CFFFFFh. enabled Memory Chip Select. Valid addresses range from D00000h- FFFFFFh.
Chip Select Operation
Chip Selects only active when performing instructions. Because space separate from memory space eZ80L92 device, there never conflict between memory addresses. eZ80L92 supports 16-bit address. Chip Select logic decodes High byte address, ADDR[15:8]. Because upper byte address bus, ADDR[23:16], ignored, devices always accessed from within memory mode (ADL Z80). MBASE offset value used setting MEMORY mode page also always ignored. Four Chip Selects available with eZ80L92. generate particular Chip Select, following conditions must met:
Chip Select enabled setting CSX_EN Chip Select configured setting CSx_IO Chip Select address match occurs-ADDR[15:8] CSx_LBR[7:0] higher-priority (lower-number) Chip Select meets above conditions address within on-chip peripheral address range 0080h-00FFh. Onchip peripheral registers assume priority addresses where:
0080h ADDR[15:0] 00FFh
instruction must executing
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foregoing conditions generate Chip Select, then following actions occur:
appropriate Chip Select-CS0, CS1, CS2, CS3-is asserted (driven Low) IORQ asserted (driven Low) Depending upon instruction, either asserted (driven Low)
WAIT States
each Chip Selects, programmable WAIT states asserted provide external devices with additional clock cycles complete their Read Write operations. number WAIT states particular Chip Select controlled 3-bit field CSx_WAIT (CSx_CTL[7:5]). WAIT states independently programmed provide WAIT states each Chip Select. WAIT states idle specified number system clock cycles.
WAIT Input Signal
Similar programmable WAIT states, external peripheral drive WAIT input force provide additional clock cycles complete Read Write operation. Driving WAIT stalls CPU. resumes operation first rising edge internal system clock following deassertion WAIT pin. Caution: WAIT driven external device, corresponding Chip Select device must programmed provide least WAIT state. input sampling WAIT input (shown Figure programmable WAIT state required allow external peripheral sufficient time assert WAIT pin. recommended that corresponding Chip Select external device programmed provide maximum number WAIT states (seven).
Wait
eZ80
System Clock
Figure Wait Input Sampling Block Diagram
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example WAIT state operation illustrated Figure this example, Chip Select configured provide single WAIT state. external peripheral being accessed drives WAIT request assertion additional WAIT state. WAIT asserted additional system clock cycles, WAIT states added until WAIT deasserted (High).
TCLK
TCSx_WAIT
TWAIT
ADDR[23:0]
DATA[7:0] (input)
MREQ
INSTRD
WAIT
Figure Wait State Operation Example (Read Operation)
Chip Selects During Request/Bus Acknowledge Cycles
When relinquishes address external peripheral response external request (BUSREQ), drives acknowledge (BUSACK) Low. external peripheral then drive address (and data bus). continues
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generate Chip Select signals response address bus. External devices cannot access internal registers eZ80L92.
Mode Controller
mode controller allows address data timing signal formats eZ80L92 configured connect seamlessly with external eZ80®, Z80-, Intel-, Motorola-compatible devices. modes each chip selects configured independently using Chip Select Mode Control Registers. number eZ80® system clock cycles mode state also independently programmable. Intel mode, multiplexed address data selected which lower byte address data byte both data bus, DATA[7:0]. Each modes explained more detail following sections.
eZ80 Mode
Chip selects configured eZ80 Mode modify signals from CPU. timing diagrams external Memory Read Write operations shown Characteristics section page 204. default mode each chip select eZ80 mode.
Mode
Chip selects configured mode modify eZ80® signals match microprocessor address data interface signal format timing. During Read operations, Mode employs three states (T1, described Table
Table Mode Read States STATE STATE Read cycle begins State drives address onto address associated Chip Select signal asserted. During State signal asserted. Depending upon instruction, either MREQ IORQ signal asserted. external WAIT driven least eZ80® system clock cycle prior State additional WAIT states (TWAIT) asserted until WAIT driven High. During State signals altered. data latched eZ80L92 rising edge eZ80® system clock State
STATE
During Write operations, Mode employs states (T1, described Table
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Table Mode Write States STATE STATE Write cycle begins State drives address onto address bus, associated Chip Select signal asserted. During State signal asserted. Depending upon instruction, either MREQ IORQ signal asserted. external WAIT driven least eZ80® system clock cycle prior State additional WAIT states (TWAIT) asserted until WAIT driven High. During State signals altered.
STATE
Mode Read Write timing illustrated Figures Mode states configured eZ80® system clock cycles. figures, each Mode state eZ80® system clock cycles duration. Figures also illustrate assertion WAIT state (TWAIT) external peripheral during each Mode cycle.
System Clock TCLK
ADDR[23:0]
DATA[7:0]
WAIT
MREQ IORQ
Figure Mode Read Timing Example
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System Clock
TCLK
ADDR[23:0]
DATA[7:0]
WAIT
MREQ IORQ
Figure Mode Write Timing Example
Intel Mode
Chip selects configured Intel Mode modify eZ80® signals duplicate four-state memory transfer similar that found Intel-style microprocessors. signals eZ80L92 pins mapped illustrated Figure Intel Mode, user select either multiplexed nonmultiplexed address data buses. nonmultiplexed operation, address data buses separate. multiplexed operation, lower byte address, ADDR[7:0], also appears data bus, DATA[7:0], during State Intel Mode cycle. During multiplexed operation, lower byte address also appears address addition data bus.
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Mode Controller eZ80 Mode Signals (Pins) INSTRD WAIT MREQ IORQ ADDR[23:0] ADDR[7:0] Multiplexed Controller Intel Signal Equvalents READY MREQ IORQ ADDR[23:0]
DATA[7:0]
DATA[7:0]
Figure IntelBus Mode Signal Mapping
Intel Mode (Separate Address Data Buses) During Read operations with separate address data buses, Intel Mode employs states (T1, described Table
Table IntelBus Mode Read States (Separate Address Data Buses) STATE Read cycle begins State drives address onto address associated Chip Select signal asserted. drives signal High beginning During middle drives facilitate latching address. During State asserts signal. Depending instruction, either MREQ IORQ signal asserted.
STATE
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Table IntelBus Mode Read States (Separate Address Data Buses) STATE During State signals altered. external ReadY (WAIT) driven least eZ80® system clock cycle prior beginning State additional WAIT states (TWAIT) asserted until ReadY driven High. latches Read data beginning State deasserts signal completes Intel Mode cycle.
STATE
During Write operations with separate address data buses, Intel Mode employs states (T1, described Table
Table IntelBus Mode Write States (Separate Address Data Buses) STATE Write cycle begins State drives address onto address bus, associated Chip Select signal asserted, data driven onto data bus. drives signal High beginning During middle drives facilitate latching address. During State asserts signal. Depending instruction, either MREQ IORQ signal asserted. During State signals altered. external ReadY (WAIT) driven least eZ80® system clock cycle prior beginning State additional WAIT states (TWAIT) asserted until ReadY driven High. deasserts signal beginning State holds data address buses through cycle completed
STATE STATE
STATE
Intel Mode timing illustrated Read operation Figure Write operation Figure ReadY signal (external WAIT pin) driven prior beginning State additional WAIT states (TWAIT) asserted until ReadY signal driven High. Intel Mode states configured eZ80® system clock cycles. figures, each IntelBus Mode state eZ80® system clock cycles duration. Figures also illustrate assertion WAIT state (TWAIT) selected peripheral.
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System Clock
TWAIT
ADDR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure IntelBus Mode Read Timing Example (Separate Address Data Buses)
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Clock
TWAIT
DR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure IntelBus Mode Write Timing Example (Separate Address Data Buses)
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IntelBus Mode (Multiplexed Address Data Bus) During Read operations with multiplexed address data, IntelBus Mode employs states (T1, described Table
Table IntelBus Mode Read States (Multiplexed Address Data Bus) STATE Read cycle begins State drives address onto DATA associated Chip Select signal asserted. drives signal High beginning During middle drives facilitate latching address. During State removes address from DATA asserts signal. Depending upon instruction, either MREQ IORQ signal asserted. During State signals altered. external ReadY (WAIT) driven least eZ80® system clock cycle prior beginning State additional WAIT states (TWAIT) asserted until ReadY driven High. latches Read data beginning State deasserts signal completes IntelBus Mode cycle.
STATE
STATE
STATE
During Write operations with multiplexed address data, IntelBus Mode employs states (T1, described Table
Table IntelBus Mode Write States (Multiplexed Address Data Bus) STATE Write cycle begins State drives address onto DATA drives signal High beginning During middle drives facilitate latching address. During State removes address from DATA drives Write data onto DATA bus. signal asserted indicate Write operation. During State signals altered. external ReadY (WAIT) driven least eZ80® system clock cycle prior beginning State additional WAIT states (TWAIT) asserted until ReadY driven High. deasserts Write signal beginning identifying Write operation. holds data address buses through cycle completed
STATE
STATE
STATE
Signal timing IntelBus Mode with multiplexed address data illustrated Read operation Figure Write operation Figure figures, each
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IntelBus Mode state eZ80® system clock cycles duration. Figures also illustrate assertion WAIT state (TWAIT) selected peripheral.
System Clock
TWAIT
ADDR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure IntelBus Mode Read Timing Example (Multiplexed Address Data Bus)
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System Clock
TWAIT
ADDR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure IntelBus Mode Write Timing Example (Multiplexed Address Data Bus)
Motorola Mode
Chip selects configured Motorola Mode modify eZ80® signals duplicate eight-state memory transfer similar that found Motorola-style microprocessors. signals (and eZ80L92 pins) mapped illustrated Figure
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Mode Controller eZ80 Mode Signals (Pins) INSTRD WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Motorola Signal Equvalents DTACK MREQ IORQ ADDR[23:0] DATA[7:0]
Figure Motorola Mode Signal Mapping
During Write operations, Motorola Mode employs states (S0, described Table
Table Motorola Mode Read States STATE STATE STATE STATE STATE Read cycle starts state drives High identify Read cycle. Entering state drives valid address address bus, ADDR[23:0]. rising edge state asserts During state signals altered. During state waits cycle termination signal DTACK (WAIT), peripheral signal. termination signal asserted least full clock period prior rising clock edge inserts WAIT (TWAIT) states until DTACK asserted. Each WAIT state full mode cycle. During state signals altered.
STATE
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Table Motorola Mode Read States (Continued) STATE STATE During state data from external peripheral device driven onto data bus. rising edge clock entering state latches data from addressed peripheral device deasserts peripheral device deasserts DTACK this time.
eight states Write operation Motorola Mode described Table
Table Motorola Mode Write States STATE STATE STATE STATE STATE Write cycle starts drives High preceding Write cycle leaves Low). Entering drives valid address address bus. rising edge asserts drives Low. During data driven high-impedance state data written placed bus. rising edge asserts waits cycle termination signal DTACK (WAIT). termination signal asserted least full clock period prior rising clock edge inserts WAIT (TWAIT) states until DTACK asserted. Each WAIT state full mode cycle. During signals altered. During signals altered. Upon entering deasserts clock rises drives High. peripheral device deasserts DTACK this time.
STATE STATE STATE
Signal timing Motorola Mode illustrated Read operation Figure Write operation Figure these figures, each Motorola Mode state eZ80® system clock cycles duration.
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System Clock
ADDR[23:0]
DATA[7:0]
DTACK
MREQ IORQ
Figure Motorola Mode Read Timing Example
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System Clock
ADDR[23:0]
DATA[7:0]
DTACK
MREQ IORQ
Figure Motorola Mode Write Timing Example
Switching Between Modes Each time mode controller must switch from mode another, there one-cycle eZ80® system clock delay. extra clock cycle required repeated accesses modes; required when eZ80L92 switches eZ80 Mode. extra clock cycles shown timing examples. asynchronous nature these protocols, extra delay does impact peripheral communication.
Chip Select Registers
Chip Select Lower Bound Registers Memory Chip Selects, Chip Select Lower Bound register, detailed Table defines lower bound address range which corresponding Memory Chip
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Select enabled) active. Chip Selects, this register defines address which ADDR[15:8] compared generate Chip Select. Chip Select lower bound registers reset 00h.
Table Chip Select Lower Bound Registers (CS0_LBR 00A8h, CS1_LBR 00ABh, CS2_LBR 00AEh, CS3_LBR 00B1h) CS0_LBR Reset CS1_LBR Reset CS2_LBR Reset CS3_LBR Reset Access
Note: Read/Write.
Position [7:0] CSx_LBR
Value Description 00h- Memory Chip Selects (CSx_IO This byte specifies lower bound Chip Select address range. upper byte address bus, ADDR[23:16], compared values contained these registers determining whether Memory Chip Select signal should generated. Chip Selects (CSx_IO This byte specifies Chip Select address value. ADDR[15:8] compared values contained these registers determining whether Chip Select signal should generated.
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Chip Select Upper Bound Registers Memory Chip Selects, Chip Select Upper Bound registers, detailed Table defines upper bound address range which corresponding Chip Select enabled) active. Chip Selects, this register produces effect. reset state Chip Select Upper Bound register FFh, while reset state other Chip Select upper bound registers 00h.
Table Chip Select Upper Bound Registers (CS0_UBR 00A9h, CS1_UBR 00ACh, CS2_UBR 00AFh, CS3_UBR 00B2h) CS0_UBR Reset CS1_UBR Reset CS2_UBR Reset CS3_UBR Reset Access
Note: Read/Write.
Position [7:0] CSx_UBR
Value Description 00h- Memory Chip Selects (CSx_IO This byte specifies upper bound Chip Select address range. upper byte address bus, ADDR[23:16], compared values contained these registers determining whether Chip Select signal should generated. Chip Selects (CSx_IO effect.
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Chip Select Control Registers Chip Select Control register, detailed Table enables Chip Selects, specifies type Chip Select, sets number WAIT states. reset state Chip Select Control register E8h, while reset state other Chip Select control registers 00h.
Table Chip Select Control Registers (CS0_CTL 00AAh, CS1_CTL 00ADh, CS2_CTL 00B0h, CS3_CTL 00B3h) CS0_CTL Reset CS1_CTL Reset CS2_CTL Reset CS3_CTL Reset Access
Note: Read/Write; Read Only.
Position [7:5] CSx_WAIT*
Value Description WAIT states asserted when this Chip Select active. WAIT state asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. Chip Select configured Memory Chip Select. Chip Select configured Chip Select. Chip Select disabled. Chip Select enabled. Reserved.
CSx_IO CSx_EN [2:0]
Note: *These WAIT state settings apply only default eZ80 mode. Table
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Chip Select Mode Control Registers Chip Select Mode register, detailed Table configures Chip Select eZ80®, Z80, IntelTM, Motorola Modes. Changing mode allows eZ80L92 interface peripherals based Z80-, IntelTM-, Motorola-style asynchronous interfaces. When mode other than eZ80® programmed particular Chip Select, CSx_WAIT setting that Chip Select Control Register ignored.
Table Chip Select Mode Control Registers (CS0_BMC 00F0h, CS1_BMC 00F1h, CS2_BMC 00F2h, CS3_BMC 00F3h) CS0_BMC Reset CS1_BMC Reset CS2_BMC Reset CS3_BMC Reset Access
Note: Read/Write; Read Only.
Position [7:6] BUS_MODE
Value Description eZ80® mode. mode. Intelbus mode. Motorola mode. Separate address data. Multiplexed address data-appears data DATA[7:0]. Reserved.
AD_MUX
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Position [3:0] BUS_CYCLE
Value Description 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 valid. Each mode state eZ80® clock cycle duration.1, Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration. Each mode state eZ80® clock cycles duration.
Notes: Setting BUS_CYCLE Intel Mode causes function properly. external WAIT input Mode requires that BUS_CYCLE value greater than These BUS_CYCLE values valid eZ80 mode. Table
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Watch-Dog Timer
Watch-Dog Timer Overview
Watch-Dog Timer (WDT) helps protect against corrupt unreliable software, power faults, other system-level problems which place eZ80® into unsuitable operating states. eZ80L92 features:
Four programmable time-out periods: 218, 222, 225, clock cycles selectable clock sources: system clock Real-Time Clock source (on-chip crystal oscillator 50/60 signal) selectable time-out response: time-out configured generate either RESET nonmaskable interrupt (NMI) time-out RESET indicator flag
Figure illustrates block diagram Watch-Dog Timer.
Data[7:0]
Control Register/ Reset Register WDT_CLK
Clock 28-Bit Upcounter System Clock Control Logic
Time-Out Compare Logic {WDT_PERIOD} RESET eZ80
Figure Watch-Dog Timer Block Diagram
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Watch-Dog Timer Operation
Enabling Disabling Watch-Dog Timer disabled upon system reset (RESET). enable WDT, application program must WDT_EN (bit WDT_CTL register. When enabled, cannot disabled without RESET. Time-Out Period Selection There four choices time-out periods WDT-218, 222, 225, system clock cycles. time-out period defined WDT_PERIOD field WDT_CTL register (WDT_CTL[1:0]). approximate time-out periods different clock sources listed Table
Table Watch-Dog Timer Approximate Time-Out Delays Clock Source 32.768 Crystal Oscillator 32.768 Crystal Oscillator 32.768 Crystal Oscillator 32.768 Crystal Oscillator 20MHz System Clock 20MHz System Clock 20MHz System Clock 20MHz System Clock System Clock System Clock System Clock System Clock Divider Value Time Delay 8.00 1024 4096 13.1 209.7 1.68 6.71 83.9 0.67 2.68
RESET Generation Upon time-out, RST_FLAG WDT_CTL register addition, cause RESET send nonmaskable interrupt (NMI) signal CPU. default operation cause RESET. asserts/deasserts rising edge clock. RST_FLAG polled determine source RESET event. NMI_OUT WDT_CTL register then upon time-out, asserts processing. RST_FLAG polled
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determine source event, provided that last RESET caused WDT.
Watch-Dog Timer Registers
Watch-Dog Timer Control Register Watch-Dog Timer Control register, detailed Table 8-bit Read/Write register used enable Watch-Dog Timer, time-out period, indicate source most recent RESET, select required operation upon time-out.
Table Watch-Dog Timer Control Register (WDT_CTL 0093h) Reset Access
Note: Read only; Read/Write.
Position WDT_EN NMI_OUT RST_FLAG*
Value Description disabled. enabled. When enabled, cannot disabled without full RESET. time-out resets CPU. time-out generates nonmaskable interrupt (NMI) CPU. RESET caused external full-chip reset reset. RESET caused time-out. This flag time-out, even NMI_OUT flag poll this determine source RESET NMI. clock source system clock. clock source Real-Time Clock source (32KHz on-chip oscillator 50/60Hz input RTC_CTRL[4]) Reserved. Reserved. Reserved.
[4:3] WDT_CLK
RESERVED
Note: *RST_FLAG only cleared non-WDT RESET.
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Position [1:0] WDT_PERIOD
Value Description time-out period clock cycles. time-out period clock cycles. time-out period clock cycles. time-out period clock cycles.
Note: *RST_FLAG only cleared non-WDT RESET.
Watch-Dog Timer Reset Register Watch-Dog Timer Reset register, detailed Table 8-bit Write-Only register. Watch-Dog Timer reset when value followed written this register. amount time occur between writing value value, long time-out does occur prior completion.
Table Watch-Dog Timer Reset Register (WDT_RR 0094h) Reset Access
Note: Undefined; Write only.
Position [7:0] WDT_RR
Value Description first Write value required reset prior timeout. second Write value required reset prior time-out. A5h, sequence written WDT_RR, timer reset initial count value, counting resumes.
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Programmable Reload Timers
Programmable Reload Timers Overview
eZ80L92 features Programmable Reload Timers (PRT). Each contains 16bit downcounter 16-bit reload register. addition, each features clock prescaler with four selectable taps 256. Each timer individually enabled operate either SINGLE PASS CONTINUOUS mode. timer programmed start, stop, restart from current value, restart from initial value, generate interrupts CPU. Four Programmable Reload Timers (timers 0-3) feature selectable clock source input. input these timers either system clock Real-Time Clock (RTC) source. Timers also used event counting, with their inputs received from GPIO port pin. Output from timers directed GPIO port pin. Each PRTs available eZ80L92 controlled individually. They share same counters, reload registers, control registers, interrupt signals. simplified block diagram programmable reload timer illustrated Figure
Data[7:0]
Data[7:0]
Reload Registers {TMRx_RR_H, TMRx_RR_L}
Control Register TMRx_CTL
System Clock Source GPIO Data Registers {TMRx_DR_H, TMRx_DR_L} TOUT_EN (Timers only) Adjustable Clock Prescaler 16-Bit Down Counter Control Logic eZ80 Timer
TMRx_IN TMRx_CTL[3:2] (Timers only)
Data[7:0]
Figure Programmable Reload Timer Block Diagram
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Programmable Reload Timer Operation
Setting Timer Duration There three factors consider when determining Programmable Reload Timer duration-clock frequency, clock divider ratio, initial count value. Minimum duration timer achieved loading 0001h. Maximum duration achieved loading 0000h, because timer first rolls over FFFFh then continues counting down 0000h. time-out period returned following equation:
Time-Out Period Clock Divider Ratio Reload Value System Clock Frequency
calculate time-out period with above equation when using initial value 0000h, enter reload value 65536 (FFFFh Minimum time-out duration times longer than input clock period generated setting clock divider ratio reload value 0001h. Maximum time-out duration (16,777,216) times longer than input clock period generated setting clock divider ratio 1:256 reload value 0000h. SINGLE PASS Mode SINGLE PASS mode, when end-of-count value, 0000h, reached, counting halts, timer disabled, PRT_EN resets restart timer, must reenable timer setting PRT_EN example operating SINGLE PASS mode illustrated Figure Timer register information indicated Table
CLKEN IOWRN
tCNTH7:0] CNTL7:0]
Figure Single Pass Mode Operation Example
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Programmable Reload Timers
eZ80L92
Table SINGLE PASS Mode Operation Example Parameter Enabled Reload Restart Enabled Clock Divider SINGLE PASS Mode Interrupt Enabled Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] TMRx_CTL[6] {TMRx_RR_H, TMRx_RR_L} Value 0004h
CONTINUOUS Mode CONTINUOUS mode, when end-of-count value, 0000h, reached, timer automatically reloads 16-bit start value from Timer Reload registers, TMRx_RR_H TMRx_RR_L. Downcounting continues next clock edge. CONTINUOUS mode, continues count until disabled. example operating CONTINUOUS mode illustrated Figure Timer register information indicated Table
CLKEN IOWRN
tCNTH7:0] CNTL7:0]
Figure CONTINUOUS Mode Operation Example
Table CONTINUOUS Mode Operation Example Parameter Enabled Reload Restart Enabled Clock Divider Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] Value
PS013012-1004
PRELIMINARY
Programmable Reload Timers
eZ80L92
Table CONTINUOUS Mode Operation Example (Continued) Parameter CONTINUOUS Mode Interrupt Enabled Reload Value Control Register(s) TMRx_CTL[4] TMRx_CTL[6] {TMRx_RR_H, TMRx_RR_L} Value 0004h
Reading Current Count Value capable reading current count value while timer running. This Read event does affect timer operation. High byte current count value latched during Read byte. Timer Interrupts timer interrupt flag, PRT_IRQ, whenever timer reaches end-of-count value, 0000h, SINGLE PASS mode, when timer reloads start value CONTINUOUS mode. interrupt flag only when timer reaches 0000h reloads) from 0001h. timer interrupt flag when timer loaded with value 0000h, which selects maximum time-out period. programmed poll PRT_IRQ time-out event. Alternatively, interrupt service request signal sent setting IRQ_EN Then, when end-of-count value, 0000h, reached PRT_IRQ interrupt service request signal passed CPU. PRT_IRQ cleared interrupt service request signal inactivated whenever reads from timer control registers, TMRx_CTL. Timer Input Source Selection Timers feature programmable input source selection. default, input taken from eZ80L92's system clock. Alternatively, Timers take their input from port input pins (Timers (Timers Timers also Real-Time Clock clock source (50, 32768Hz) their clock sources. When timer clock source Real-Time Clock signal, timer decrements second rising edge system clock following falling edge RTC_XOUT pin. input source these timers using Timer Input Source Select register. Event Counter When Timers configured take their inputs from port input pins PB1, they function event counters. event counting, clock prescaler bypassed. counters decrement every rising edge port pin. port pins must configured inputs. input sampling pins, event input signal frequency limited one-half system clock frequency. Input sampling port pins results
PS013012-1004
PRELIMINARY
Programmable Reload Timers
eZ80L92
counter being updated fifth rising edge system clock after rising edge occurs port pin. Timer Output Programmable Reload Timers (Timers directed GPIO Port output pins (PB4 PB5, respectively). enable Timer feature, GPIO port must configured alternate functions. After reset, Timer Output feature disabled default. GPIO output toggles each time reaches end-of-count value. CONTINUOUS mode operation, disabling Timer Output feature results Timer Output signal period that twice time-out period. Examples Timer Output operation illustrated Figure Table these examples, GPIO output assumed when Timer Output function enabled.
Clock (Clock
IOWRN Count Value Timer Output
Write TMRx_CTL Enables
Figure Timer Output Operation Example
Table Timer Operation Example Parameter Enabled Reload Restart Enabled Clock Divider CONTINUOUS Mode Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] {TMRx_RR_H, TMRx_RR_L} Value 0003h
PS013012-1004
PRELIMINARY
Programmable Reload Timers
eZ80L92
Programmable Reload Timer Registers
Each programmable reload timer controlled using five 8-bit registers. These registers Timer Control register, Timer Reload Byte register, Timer Reload High Byte register, Timer Data Byte register, Timer Data High Byte register. Timer Control register read written timer reload registers WriteOnly located same address timer data registers, which ReadOnly. Timer Control Registers Timer Control register, detailed Table used control operation timer, including enabling timer, selecting clock divider, enabling interrupt, selecting between CONTINUOUS SINGLE PASS modes, enabling auto-reload feature.
Table Timer Control Registers (TMR0_CTL 0080h, TMR1_CTL 0083h, TMR2_CTL 0086h, TMR3_CTL 0089h, TMR4_CTL 008Ch, TMR5_CTL 008Fh) Reset Access
Note: Read only; Read/Write.
Position PRT_IRQ
Value
Description timer does reach end-of-count value. This reset every time TMRx_CTL register read. timer reaches end-of-count value. IRQ_EN interrupt signal sent CPU. This remains until TMRx_CTL register read. Timer interrupt requests disabled. Timer interrupt requests enabled. Reserved. timer operates SINGLE PASS mode. PRT_EN (bit reset counting stops when end-of-count value reached. timer operates CONTINUOUS mode. timer reload value written counter when end-of-count value reached.
IRQ_EN
PRT_MODE
PS013012-1004
PRELIMINARY
Programmable Reload Timers
eZ80L92
[3:2] CLK_DIV
Clock timer input source. Clock timer input source. Clock timer input source. Clock timer input source. reload restart function disabled. reload restart function enabled. When written RST_EN, values reload registers loaded into downcounter timer restarts. programmable reload timer disabled. programmable reload timer enabled.
RST_EN
PRT_EN
Timer Data Registers-Low Byte This Read-Only register returns byte current count value selected timer. Timer Data Register-Low Byte, detailed Table read while timer operation. Reading current count value does affect timer operation. read 16-bit data current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read Timer Data Register-Low Byte then read Timer Data Register- High Byte. Timer Data Register-High Byte value latched when Read Timer Data Register-Low Byte occurs. Note: Timer Data registers Timer Reload registers share same address space.
Table Timer Data Registers-Low Byte (TMR0_DR_L 0081h, TMR1_DR_L 0084h, TMR2_DR_L 0087h, TMR3_DR_L 008Ah, TMR4_DR_L 008Dh, TMR5_DR_L 0090h) Reset Access
Note: Read only.
Position [7:0] TMRx_DR_L
Value
Description
00h-FFh These bits represent byte 2-byte timer data value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. 16-bit timer data value. (lsb) 16bit timer data value.
PS013012-1004
PRELIMINARY
Programmable Reload Timers
eZ80L92
Timer Data Registers-High Byte This Read-Only register returns High byte current count value selected timer. Timer Data Register-High Byte, detailed Table read while timer operation. Reading current count value does affect timer operation. read 16-bit data current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first read Timer Data Register-Low Byte then read Timer Data Register- High Byte. Timer Data Register-High Byte value latched when Read Timer Data Register-Low Byte occurs. Note: timer data registers timer reload registers share same address space.
Table Timer Data Registers-High Byte (TMR0_DR_H 0082h, TMR1_DR_H 0085h, TMR2_DR_H 0088h, TMR3_DR_H 008Bh, TMR4_DR_H 008Eh, TMR5_DR_H 0091h) Reset Access
Note: Read only.
Position
Value
Description
[7:0] 00h-FFh These bits represent High byte 2-byte timer data TMRx_DR_H value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. (msb) 16-bit timer data value. 16-bit timer data value.
PS013012-1004
PRELIMINARY
Programmable Reload Timers
eZ80L92
Timer Reload Registers-Low Byte Timer Reload Register-Low Byte, detailed Table stores least significant byte (LSB) 2-byte timer reload value. CONTINUOUS mode, timer reload value reloaded into timer upon end-of-count. When RST_EN (TMRx_CTL[1]) enable automatic reload restart function, timer reload value written timer next rising edge clock. Note: Timer Data registers Timer Reload registers share same address space.
Table Timer Reload Registers-Low Byte (TMR0_RR_L 0081h, TMR1_RR_L 0084h, TMR2_RR_L 0087h, TMR3_RR_L 008Ah, TMR4_RR_L 008Dh, TMR5_RR_L 0090h) Reset Access
Note: Write only.
Position [7:0] TMRx_RR_L
Value
Description
00h-FFh These bits represent byte 2-byte timer reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. 16-bit timer reload value. (lsb) 16-bit timer reload value.
PS013012-1004
PRELIMINARY
Programmable Reload Timers
eZ80L92
Timer Reload Registers-High Byte Timer Reload Register-High Byte, detailed Table stores most significant byte (MSB) 2-byte timer reload value. CONTINUOUS mode, timer reload value reloaded into timer upon end-of-count. When RST_EN (TMRx_CTL[1]) enable automatic reload restart function, timer reload value written timer next rising edge clock. Note: Timer Data registers Timer Reload registers share same address space.
Table Timer Reload Registers-High Byte (TMR0_RR_H 0082h, TMR1_RR_H 0085h, TMR2_RR_H 0088h, TMR3_RR_H 008Bh, TMR4_RR_H 008Eh, TMR5_RR_H 0091h) Reset Access
Note: Write only.
Position [7:0] TMRx_RR_
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