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eZ80F92/eZ80F93 PRELIMINARY PS015309-1004 ZiLOG Worldwide He


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eZ80Acclaim!Flash Microcontrollers
eZ80F92/eZ80F93
PRELIMINARY PS015309-1004
ZiLOG Worldwide Headquarters Race Street Jose, 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
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Race Street Jose, 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.zilog.com
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2004 ZiLOG, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZiLOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. ZiLOG ALSO DOES ASSUME LIABILITY INTELLECTUAL PROPERTY INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. Except with express written approval ZiLOG, information, devices, technology critical components life support systems authorized. licenses other rights conveyed, implicitly otherwise, this document under intellectual property rights.
PS015309-1004
PRELIMINARY
eZ80F92/eZ80F93
Revision History
Each instance Table reflects change this document from previous revision. more detail, click appropriate link table.
Table Revision History this Document; Revision Level Section Page
Date October. 2004
Description
Formatted current publication standards Timer Control Register Figure Figure Real-Time Clock Oscillator Source Selection Clarified RST_EN descriptions. Corrected rise time label from Corrected rise time label from Clarified language describing drive frequency.
PS015309-1004
PRELIMINARY
Revision History
eZ80F92/eZ80F93
Table Contents
Revision History .iii List Figures .viii List Tables Architectural Overview Features Block Diagram Description Characteristics Register eZ80® Core Features Reset Reset Operation Power-On Reset Voltage Brown-Out Reset Low-Power Modes Overview SLEEP Mode HALT Mode Clock Peripheral Power-Down Registers General-Purpose Input/Output GPIO Overview GPIO Operation GPIO Interrupts GPIO Control Registers
Interrupt Controller Maskable Interrupts Nonmaskable Interrupts Chip Selects Wait States Memory Chip Selects Memory Chip Select Operation Chip Select Operation Wait States WAIT Input Signal
PS015309-1004
PRELIMINARY
Table Contents
eZ80F92/eZ80F93
Chip Selects During Request/Bus Acknowledge Cycles Mode Controller eZ80 Mode Mode IntelBus Mode Motorola Mode Chip Select Registers Watch-Dog Timer Watch-Dog Timer Overview Watch-Dog Timer Operation Watch-Dog Timer Registers Programmable Reload Timers Programmable Reload Timers Overview Programmable Reload Timer Operation Programmable Reload Timer Registers Real-Time Clock Real-Time Clock Overview Real-Time Clock Alarm Real-Time Clock Oscillator Source Selection Real-Time Clock Battery Backup Real-Time Clock Recommended Operation Real-Time Clock Registers Universal Asynchronous Receiver/Transmitter UART Functional Description UART Functions UART Interrupts UART Recommended Usage Baud Rate Generator Control Registers UART Registers Infrared Encoder/Decoder Functional Description Transmit Receive Receiver Frequency Divider Jitter Infrared Encoder/Decoder Signal Pins Loopback Testing
PS015309-1004
PRELIMINARY
Table Contents
eZ80F92/eZ80F93
Serial Peripheral Interface Signals Functional Description Flags Baud Rate Generator Data Transfer Procedure with Configured Master Data Transfer Procedure with Configured Slave Registers Serial Interface General Characteristics Transferring Data Clock Synchronization Operating Modes Registers ZiLOG Debug Interface Introduction ZDI-Supported Protocol Clock Data Conventions Start Condition Register Addressing Write Operations Read Operations Operation eZ80F92 Device During Breakpoints Requests During DEBUG Mode Write Only Registers Read Only Registers Register Definitions On-Chip Instrumentation Introduction On-Chip Instrumentation Activation Interface Information Requests
Random Access Memory Control Registers Flash Memory Flash Memory Arrangement eZ80F92 Flash Memory Arrangement eZ80F93 Flash Memory Overview Programming Flash Memory
PS015309-1004
PRELIMINARY
Table Contents
eZ80F92/eZ80F93
Erasing Flash Memory Flash Control Registers eZ80® Instruction Op-Code On-Chip Oscillators Primary Crystal Oscillator Operation Real-Time Clock Crystal Oscillator Operation Electrical Characteristics Absolute Maximum Ratings Characteristics Electrical Characteristics Typical Current Consumption Under Various Operating Conditions Characteristics External Memory Read Timing External Memory Write Timing External Read Timing External Write Timing Wait State Timing Read Operations Wait State Timing Write Operations General Purpose Port Input Sample Timing External Acknowledge Timing External System Clock Driver (PHI) Timing ZiLOG Debug Interface Timing
Packaging Ordering Information Part Number Description Precharacterization Product Document Information Document Number Description Change Index Customer Feedback Form
PS015309-1004
PRELIMINARY
Table Contents
eZ80F92/eZ80F93
viii
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure eZ80F92 Block Diagram 100-Pin LQFP Configuration eZ80F92 Device GPIO Port Block Diagram Example: Memory Chip Select Wait Input Sampling Block Diagram Example: Mode Write Timing IntelBus Mode Signal Mapping Example: IntelBus Mode Read Timing-Separate Address Data Buses Example: IntelBus Mode Write Timing-Separate Address Data Buses Example: IntelBus Mode Read Timing-Multiplexed Address Data Example: IntelBus Mode Write Timing-Multiplexed Address Data Motorola Mode Signal Mapping Watch-Dog Timer Block Diagram Single Pass Mode Operation Example UART Block Diagram Infrared System Block Diagram Master Device Slave Device Clock Data Relationship START STOP Conditions Protocol Acknowledge Clock Synchronization Protocol Typical Debug Setup Schematic Building Target Board ZPAK Connector Write Timing Read Timing Address Write Timing eZ80F92 On-Chip Memory Addressing Example eZ80F93 On-Chip Memory Addressing Example
PS015309-1004
PRELIMINARY
List Figures
eZ80F92/eZ80F93
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Recommended Crystal Oscillator Configuration (20MHz operation) Recommended Crystal Oscillator Configuration (32KHz operation) Versus WAIT States Function Frequency Versus Frequency Function WAIT States Versus Temperature Function Frequency Versus Frequency HALT Mode Versus Temperature SLEEP Mode External Memory Write Timing External Read Timing External Write Timing Wait State Timing Read Operations Wait State Timing Write Operations Port Input Sample Timing
PS015309-1004
PRELIMINARY
List Figures
eZ80F92/eZ80F93
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Revision History this Document. 100-Pin LQFP Identification eZ80F92 Device Characteristics eZ80F92 Device Register Clock Peripheral Power-Down Register. Clock Peripheral Power-Down Register GPIO Mode Selection Port Data Registers Port Data Direction Registers Port Alternate Registers Port Alternate Registers Interrupt Vector Sources Priority. Vectored Interrupt Operation Register Values Memory Chip Select Example Figure Mode Read States Mode Write States IntelBus Mode Read States (Separate Address Data Buses) IntelBus Mode Write States (Separate Address Data Buses) IntelBus Mode Read States (Multiplexed Address Data Bus). IntelBus Mode Write States (Multiplexed Address Data Bus) Motorola Mode Read States Motorola Mode Write States Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register Chip Select Mode Control Register Watch-Dog Timer Approximate Time-Out Delays Watch-Dog Timer Control Register Watch-Dog Timer Reset Register. Single Pass Mode Operation Example Continuous Mode Operation Example Continuous Mode Operation Example Timer Operation Example
PS015309-1004
PRELIMINARY
List Tables
eZ80F92/eZ80F93
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Timer Control Register Timer Data Register-Low Byte Timer Data Register-High Byte Timer Reload Register-Low Byte Timer Reload Register-High Byte Timer Input Source Select Register Real-Time Clock Seconds Register Real-Time Clock Minutes Register Real-Time Clock Hours Register Real-Time Clock Day-of-the-Week Register Real-Time Clock Day-of-the-Month Register Real-Time Clock Month Register. Real-Time Clock Year Register Real-Time Clock Century Register. Real-Time Clock Alarm Seconds Register Real-Time Clock Alarm Minutes Register Real-Time Clock Alarm Hours Register. Real-Time Clock Alarm Day-of-the-Week Register Real-Time Clock Alarm Control Register Real-Time Clock Control Register UART Baud Rate Generator Register-Low Bytes UART Baud Rate Generator Register-High Bytes UART Receive Buffer Registers UART Transmit Holding Registers UART Interrupt Enable Registers. UART Interrupt Identification Registers UART Interrupt Status Codes. UART FIFO Control Registers. UART Line Control Registers UART Character Parameter Definition Parity Select Definition Multidrop Communications UART Modem Control Registers UART Line Status Registers. UART Modem Status Registers UART Scratch Registers IrDA Physical Layer Pulse Durations Specifications
PS015309-1004
PRELIMINARY
List Tables
eZ80F92/eZ80F93
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106.
Frequency Divider Values GPIO Mode Selection when using IrDA Encoder/Decoder Infrared Encoder/Decoder Control Registers Clock Phase Clock Polarity Operation Baud Rate Generator Register-Low Byte Control Register Baud Rate Generator Register-High Byte (SPI_BRG_H 00B9h) Status Register Transmit Shift Register Receive Buffer Register Master Transmit Status Codes Master Transmit Status Codes Data Bytes 10-Bit Master Transmit Status Codes Master Receive Status Codes Master Receive Status Codes Data Bytes Register Descriptions Slave Address Registers. Data Registers Extended Slave Address Registers. Control Registers Status Registers Status Codes Clock Control Registers Software Reset Register Recommended Clock System Clock Frequency Write Only Registers. Read Only Registers Address Match Registers. BREAK Control Register Master Control Register Write Data Registers Read/Write Control Register Functions Control Register Instruction Store Registers Write Memory Register. eZ80 Product Byte Register
PS015309-1004
PRELIMINARY
List Tables
eZ80F92/eZ80F93
xiii
Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142.
eZ80 Product High Byte Register eZ80 Product Revision Register Status Register. Read Register Low, High Upper Control Register Read Memory Register Pins Control Register Address Upper Byte Register Flash Register Flash Address Upper Byte Register Flash Data Register Flash Control Register Flash Frequency Divider Values. Flash Frequency Divider Register Flash Write/Erase Protection Register Flash Interrupt Control Register Flash Select Register Flash Page Select Register Flash Column Select Register. Flash Program Control Register Arithmetic Instructions Manipulation Instructions Block Transfer Compare Instructions Exchange Instructions. Input/Output Instructions Load Instructions Logical Instructions Processor Control Instructions Program Control Instructions Rotate Shift Instructions. Code Map-First Code Code Map-Second Code after 0CBh Code Map-Second Code After 0DDh Code Map-Second Code After 0EDh Code Map-Second Code After 0FDh
PS015309-1004
PRELIMINARY
List Tables
eZ80F92/eZ80F93
Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159.
Code Map-Fourth Byte After 0DDh, 0CBh, Code Map-Fourth Byte After 0FDh, 0CBh, Recommended Crystal Oscillator Specifications. Recommended Crystal Oscillator Specifications. Absolute Maximum Ratings Characteristics Electrical Characteristics Characteristics External Read Timing External Write Timing External Read Timing. External Write Timing GPIO Port Output Timing. Acknowledge Timing System Clock Timing Timing Specifications Ordering Information
PS015309-1004
PRELIMINARY
List Tables
eZ80F92/eZ80F93
Architectural Overview
eZ80F92 device high-speed single-cycle instruction-fetch microcontroller with maximum clock speed MHz. first member ZiLOG's eZ80Acclaim!product family, which offers on-chip Flash program memory. eZ80F92 device operate Z80-compatible addressing mode full 24-bit addressing mode MB). rich peripheral eZ80F92 device makes suitable variety applications including industrial control, embedded communication, point-of-sale terminals. Note: Additionally, ZiLOG offers eZ80F93 device, which features scaled-down memory options. purposes clarity, this document refers both devices collectively eZ80F92 device, unless otherwise specified.
Features
Single-cycle instruction fetch, high-performance, pipelined eZ80® core1 eZ80F92 contains Flash memory SRAM eZ80F93 contains Flash memory SRAM power features including SLEEP mode, HALT mode, selective peripheral power-down control UARTs with independent baud rate generators with independent clock rate generator with independent clock rate generator IrDA-compliant infrared encoder/decoder DMA-like instructions efficient block data transfer Glueless external peripheral interface with Chip Selects, individual Wait State generators, external WAIT input pin-supports Z80-, Intel-, Motorola-style buses Fixed-priority vectored interrupts (both internal external) interrupt controller Real-Time Clock with on-chip oscillator, selectable 50/60 input, separate battery backup 16-bit Counter/Timers with clock dividers direct input/output drive Watch-Dog Timer
simplicity, term eZ80® referred bulk this document.
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
bits General-Purpose debug interfaces 100-pin LQFP package 3.0-3.6 supply voltage with tolerant inputs Operating Temperature Range: Standard: Extended:
Note: signals with overline active Low. example, B/W, which WORD active Low, B/W, which BYTE active Low. Power connections follow these conventional descriptions:
Connection Power Ground Circuit Device
Block Diagram
Figure illustrates block diagram eZ80F92 processor.
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Real-Time Clock 32KHz Oscillator
RTC_VDD RTC_XIN RTC_XOUT
Serial Interface Controller DATA[7:0]
BUSACK BUSREQ INSTRD IORQ MREQ
MISO MOSI
Serial Parallel Interface
eZ80®
RESET HALT_SLP
ADDR[23:0]
128KB/64KB Flash Memory
JTAG/ZDI Debug Interface
JTAG Signals
CTS0/1 DCD0/1 DSR0/1 DTR0/1 RI0/1 RTS0/1 RXD0/1 TXD0/1 UART Universal Asynchronous Receiver/ Transmitter
WAIT 8KB/4KB SRAM Interrupt Vector [7:0] Interrupt Controller Chip Select Wait State Generator DATA[7:0] ADDR[23:0] Watchdog Timer
IrDA Encoder/ Decoder
GPIO 8-bit General Purpose Port
Crystal Oscillator System Clock Generator
Programmable Reload Timer/Counter
Figure 1.eZ80F92 Block Diagram
PS015309-1004
PRELIMINARY
T4_OUT T5_OUT
IR_TxD
PB[7:0]
PC[7:0]
IR_RxD
PD[7:0]
T0_IN T1_IN T2_IN T3_IN
XOUT
Architectural Overview
eZ80F92/eZ80F93
Description
Figure illustrates layout eZ80F92 device 100-pin LQFP package. Table describes pins their functions.
PB7/MOSI PB6/MISO PB5/T5_OUT PB4/T4_OUT PB3/SCK PB2/SS PB1/T1_IN PB0/T0_IN XOUT PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 PC2//RTS1 PC1/RxD1 PC0/TxD1 PS015309-1004 ADDR21 ADDR22 ADDR23 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 IORQ MREQ INSTRD WAIT PRELIMINARY ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20
100-Pin LQFP
PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0 PD1/RxD0/IR_RxD PD0/TxD0/IR_TxD TRIGOUT RTC_VDD RTC_XOUT RTC_XIN HALT_SLP BUSACK BUSREQ RESET
Figure 2.100-Pin LQFP Configuration eZ80F92 Device
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device Symbol ADDR0 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR1
Address
Bidirectional
ADDR2
Address
Bidirectional
ADDR3
Address
Bidirectional
ADDR4
Address
Bidirectional
ADDR5
Address
Bidirectional
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol ADDR6 Function Power Supply Ground Address Bidirectional Signal Direction Description Power Supply. Ground. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR7
Address
Bidirectional
ADDR8
Address
Bidirectional
ADDR9
Address
Bidirectional
ADDR10
Address
Bidirectional
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol ADDR11 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Power Supply. Ground. Bidirectional Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR12
Address
Bidirectional
ADDR13
Address
Bidirectional
ADDR14
Address
Bidirectional
ADDR15
Power Supply Ground Address
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol ADDR16 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects.
ADDR17
Address
Bidirectional
ADDR18
Address
Bidirectional
ADDR19
Address
Bidirectional
ADDR20
Address
Bidirectional
ADDR21
Address
Bidirectional
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol ADDR22 Function Address Signal Direction Bidirectional Description Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. Configured output normal operation. address selects location memory space read written. Configured input during acknowledge cycles. Drives Chip Select/Wait State Generator block generate Chip Selects. indicates that access occurring defined memory address space. indicates that access occurring defined memory address space. indicates that access occurring defined memory address space. indicates that access occurring defined memory address space. Power Supply. Ground. Bidirectional data transfers data from memory devices. eZ80Acclaim!drives these lines only during Write cycles when master. data transfers data from memory devices. drives these lines only during Write cycles when master.
ADDR23
Address
Bidirectional
Chip Select
Output, Active
Chip Select
Output, Active
Chip Select
Output, Active
Chip Select
Output, Active
DATA0
Power Supply Ground Data
DATA1
Data
Bidirectional
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol DATA2 Function Data Signal Direction Bidirectional Description data transfers data from memory devices. drives these lines only during Write cycles when master. data transfers data from memory devices. drives these lines only during Write cycles when master. data transfers data from memory devices. drives these lines only during Write cycles when master. data transfers data from memory devices. drives these lines only during Write cycles when master. data transfers data from memory devices. drives these lines only during Write cycles when master. data transfers data from memory devices. drives these lines only during Write cycles when master. Power Supply. Ground. Bidirectional, Active IORQ indicates that accessing location space. indicate type access. input acknowledge cycles. MREQ indicates that accessing location memory. INSTRD signals indicate type access. input acknowledge cycles. indicates that reading from current address location. This tristated during acknowledge cycles.
DATA3
Data
Bidirectional
DATA4
Data
Bidirectional
DATA5
Data
Bidirectional
DATA6
Data
Bidirectional
DATA7
Data
Bidirectional
IORQ
Power Supply Ground Input/Output Request
MREQ
Memory Request
Bidirectional, Active
Read
Output, Active
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function Write Signal Direction Output, Active Description indicates that writing current address location. This tristated during acknowledge cycles. INSTRD (with MREQ indicates fetching instruction from memory. This tristated during acknowledge cycles. Driving WAIT forces wait additional clock cycles external peripheral external memory complete Read Write operation.
INSTRD
Instruction Output, Active Read Indicator
WAIT
WAIT Request Input, Active
RESET
System Reset Schmitt Trigger Input, This signal used initialize CPU. Active This input must minimum system clock cycles, must held until clock stable. This input includes Schmitt trigger allow rise times. Nonmaskable Schmitt Trigger Input, input higher priority input than Interrupt Active maskable interrupts. always recognized instruction, regardless state interrupt enable control bits. This input includes Schmitt trigger allow rise times. Request Input, Active External devices request release memory interface their use, driving this Low. responds BUSREQ, tristating address, data, control signals, driving BUSACK line Low. During acknowledge cycles ADDR[23:0], IORQ, MREQ inputs. this indicates that entered either HALT SLEEP mode because execution either HALT instruction. Power Supply. Ground. Input This input low-power crystal oscillator Real-Time Clock.
BUSREQ
BUSACK
Acknowledge
Output, Active
HALT_SLP
HALT SLEEP Indicator Power Supply Ground Real-Time Clock Crystal Input
Output, Active
RTC_XIN
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function Signal Direction Bidirectional Description This output from low-power crystal oscillator Real-Time Clock. This input when configured operate from 50/60 input clock signals crystal oscillator disabled. Power supply Real-Time Clock associated oscillator. Isolated from power supply remainder chip. battery connected this supply constant power Real-Time Clock oscillator. Ground. Input Input JTAG Mode Select Input. JTAG clock input. Active High trigger event indicator. JTAG data input pin. Functions data when JTAG disabled. JTAG data output pin. Power Supply. Bidirectional This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART transmit asynchronous serial data. This signal multiplexed with PD0. This used IrDA encoder/ decoder transmit serial data. This signal multiplexed with PD0.
RTC_XOUT Real-Time Clock Crystal Output
RTC_VDD
Real-Time Clock Power Supply
TRIGOUT
Ground JTAG Test Mode Select JTAG Test Clock
JTAG Test Output Trigger Output JTAG Test Data JTAG Test Data Power Supply GPIO Port Bidirectional Output
TxD0
UART Output Transmit Data IrDA Transmit Output Data
IR_TxD
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART receive asynchronous serial data. This signal multiplexed with PD1. This used IrDA encoder/ decoder receive serial data. This signal multiplexed with PD1. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal from UART. This signal multiplexed with PD2. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD3.
RxD0
Receive Data
Input
IR_RxD
IrDA Receive Data GPIO Port
Input
Bidirectional
RTS0
Request Send GPIO Port
Output, Active Bidirectional
CTS0
Clear Send Input, Active
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal UART. This signal multiplexed with PD4. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD5. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD6. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PD7.
DTR0
Data Terminal Output, Active Ready GPIO Port Bidirectional
DSR0
Data Ready GPIO Port
Input, Active Bidirectional
DCD0
Data Carrier Detect GPIO Port
Input, Active Bidirectional
Ring Indicator Input, Active
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART transmit asynchronous serial data. This signal multiplexed with PC0. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. This used UART receive asynchronous serial data. This signal multiplexed with PC1. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal from UART. This signal multiplexed with PC2.
TxD1
Transmit Data Output
GPIO Port
Bidirectional
RxD1
Receive Data
Input
GPIO Port
Bidirectional
RTS1
Request Send
Output, Active
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC3. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem control signal UART. This signal multiplexed with PC4. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC5. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC6.
CTS1
Clear Send Input, Active GPIO Port Bidirectional
DTR1
Data Terminal Output, Active Ready GPIO Port Bidirectional
DSR1
Data Ready GPIO Port
Input, Active Bidirectional
DCD1
Data Carrier Detect
Input, Active
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Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Port multiplexed with UART. Modem status signal UART. This signal multiplexed with PC7. Ground. This input onboard crystal oscillator primary system clock. external oscillator used, clock output should connected this pin. When crystal used, should connected between XOUT. This output onboard crystal oscillator. When used, crystal should connected between XOUT. Power Supply. Bidirectional This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Alternate clock source Programmable Reload Timers This signal multiplexed with PB0.
Ring Indicator Input, Active Ground System Clock Input Oscillator Input
XOUT
System Clock Output Oscillator Output Power Supply GPIO Port
T0_IN
Timer
Input
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Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Alternate clock source Programmable Reload Timers This signal multiplexed with PB1. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. slave select input line used select slave device mode. This signal multiplexed with PB2. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. serial clock. This signal multiplexed with PB3. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Programmable Reload Timer timer-out signal. This signal multiplexed with PB4.
T1_IN
Timer
Input
GPIO Port
Bidirectional
Slave Select
Input, Active
GPIO Port
Bidirectional
Serial Clock GPIO Port
Bidirectional Bidirectional
T4_OUT
Timer
Output
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Architectural Overview
eZ80F92/eZ80F93
Table 100-Pin LQFP Identification eZ80F92 Device (Continued) Symbol Function GPIO Port Signal Direction Bidirectional Description This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. Programmable Reload Timer timer-out signal. This signal multiplexed with PB5. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. MISO line configured input when master device output when slave device. This signal multiplexed with PB6. This used general-purpose individually programmed input output also used individually interrupt input. Each Port pin, when programmed output, selected open-drain opensource output. MOSI line configured output when master device input when slave device. This signal multiplexed with PB7. Power Supply. Ground. This carries data signal. This used receive transmit clock. This output driven internal system clock.
T5_OUT
Timer GPIO Port
Output Bidirectional
MISO
Master Slave
Bidirectional
GPIO Port
Bidirectional
MOSI
Master Out, Slave
Bidirectional
Power Supply Ground Serial Data Bidirectional Serial Clock Bidirectional
System Clock Output
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Architectural Overview
eZ80F92/eZ80F93
Characteristics
Table describes characteristics each eZ80F92 device's 100-pin LQFP package.
Table Characteristics eZ80F92 Device Schmitt Trigger Input
Symbol ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19
Reset Direction Direction
Active Low/High
Tristate Pull Output Up/Down
Open Drain/ Source
Note: Input, Output, Input Output, Undefined.
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Architectural Overview
eZ80F92/eZ80F93
Table Characteristics eZ80F92 Device (Continued) Schmitt Trigger Input
Symbol ADDR20 ADDR21 ADDR22 ADDR23 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 IORQ MREQ INSTRD WAIT RESET
Reset Direction Direction
Active Low/High
Tristate Pull Output Up/Down
Open Drain/ Source
Note: Input, Output, Input Output, Undefined.
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Architectural Overview
eZ80F92/eZ80F93
Table Characteristics eZ80F92 Device (Continued) Schmitt Trigger Input
Symbol BUSREQ BUSACK HALT_SLP RTC_XIN RTC_XOUT RTC_VDD TRIGOUT
Reset Direction Direction
Active Low/High
Tristate Pull Output Up/Down
Open Drain/ Source
Rising (In) Falling (Out) High
Note: Input, Output, Input Output, Undefined.
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Architectural Overview
eZ80F92/eZ80F93
Table Characteristics eZ80F92 Device (Continued) Schmitt Trigger Input
Symbol XOUT
Reset Direction Direction
Active Low/High
Tristate Pull Output Up/Down
Open Drain/ Source
Note: Input, Output, Input Output, Undefined.
PS015309-1004
PRELIMINARY
Architectural Overview
eZ80F92/eZ80F93
Register
on-chip peripheral registers accessed address space. operations employ 16-bit addresses. upper byte 24-bit address undefined during operations (ADDR[23:16] UU). operations using 16-bit addresses within range 0080h-00FFh routed on-chip peripherals. External Chip Selects generated address space programmed Chip Selects overlaps 0080h-00FFh address range. Registers unused addresses within 0080h-00FFh range assigned on-chip peripherals implemented. Read access such addresses returns unpredictable values Write access produces effect. Table diagrams register eZ80F92 device.
Table Register Address (hex) Mnemonic Reset (hex) Page Access
Name
Programmable Reload Counter/Timers 0080 0081 TMR0_CTL TMR0_DR_L TMR0_RR_L 0082 TMR0_DR_H TMR0_RR_H 0083 0084 TMR1_CTL TMR1_DR_L TMR1_RR_L 0085 TMR1_DR_H TMR1_RR_H 0086 TMR2_CTL Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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Register
eZ80F92/eZ80F93
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Page Access
Name
Programmable Reload Counter/Timers (continued) 0087 TMR2_DR_L TMR2_RR_L 0088 TMR2_DR_H TMR2_RR_H 0089 008A TMR3_CTL TMR3_DR_L TMR3_RR_L 008B TMR3_DR_H TMR3_RR_H 008C 008D TMR4_CTL TMR4_DR_L TMR4_RR_L 008E TMR4_DR_H TMR4_RR_H 008F 0090 TMR5_CTL TMR5_DR_L TMR5_RR_L 0091 TMR5_DR_H TMR5_RR_H 0092 TMR_ISS Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Control Register Timer Data Register-Low Byte Timer Reload Register-Low Byte Timer Data Register-High Byte Timer Reload Register-High Byte Timer Input Source Select Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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Register
eZ80F92/eZ80F93
Table Register (Continued) Address (hex) Mnemonic Watch-Dog Timer 0093 0094 WDT_CTL WDT_RR Watch-Dog Timer Control Register1 Watch-Dog Timer Reset Register 00/20 Reset (hex) Page Access
Name
General-Purpose Input/Output Ports 009A 009B 009C 009D 009E 009F 00A0 00A1 00A2 00A3 00A4 00A5 PB_DR PB_DDR PB_ALT1 PB_ALT2 PC_DR PC_DDR PC_ALT1 PC_ALT2 PD_DR PD_DDR PD_ALT1 PD_ALT2 Port Data Register2 Port Data Direction Register Port Alternate Register Port Alternate Register Port Data Register2 Port Data Direction Register Port Alternate Register Port Alternate Register Port Data Register2 Port Data Direction Register Port Alternate Register Port Alternate Register
Chip Select/Wait State Generator 00A8 00A9 00AA 00AB 00AC 00AD CS0_LBR CS0_UBR CS0_CTL CS1_LBR CS1_UBR CS1_CTL Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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eZ80F92/eZ80F93
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Page Access
Name
Chip Select/Wait State Generator (continued) 00AE 00AF 00B0 00B1 00B2 00B3 CS2_LBR CS2_UBR CS2_CTL CS3_LBR CS3_UBR CS3_CTL Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register Chip Select Lower Bound Register Chip Select Upper Bound Register Chip Select Control Register
On-Chip Control 00B4 00B5 RAM_CTL RAM_ADDR_U Control Register Address Upper Byte Register
Serial Peripheral Interface (SPI) Block 00B8 00B9 00BA 00BB 00BC SPI_BRG_L SPI_BRG_H SPI_CTL SPI_SR SPI_TSR SPI_RBR Baud Rate Generator Register-Low Byte Baud Rate Generator Register-High Byte Control Register Status Register Transmit Shift Register Receive Buffer Register
Infrared Encoder/Decoder Block 00BF IR_CTL Infrared Encoder/Decoder Control
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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Register
eZ80F92/eZ80F93
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Page Access
Name
Universal Asynchronous Receiver/Transmitter (UART0) Block 00C0 UART0_RBR UART0_THR UART0_BRG_L 00C1 UART0_IER UART0_BRG_H 00C2 UART0_IIR UART0_FCTL 00C3 00C4 00C5 00C6 00C7 Block 00C8 00C9 00CA 00CB 00CC I2C_SAR I2C_XSAR I2C_DR I2C_CTL I2C_SR I2C_CCR 00CD I2C_SRR Slave Address Register Extended Slave Address Register Data Register Control Register Status Register Clock Control Register Software Reset Register UART0_LCTL UART0_MCTL UART0_LSR UART0_MSR UART0_SPR UART Receive Buffer Register UART Transmit Holding Register UART Baud Rate Generator Register- Byte UART Interrupt Enable Register UART Baud Rate Generator Register- High Byte UART Interrupt Identification Register UART FIFO Control Register UART Line Control Register UART Modem Control Register UART Line Status Register UART Modem Status Register UART Scratch Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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Register
eZ80F92/eZ80F93
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Page Access
Name
Universal Asynchronous Receiver/Transmitter (UART1) Block 00D0 UART1_RBR UART1_THR UART1_BRG_L 00D1 UART1_IER UART1_BRG_H 00D2 UART1_IIR UART1_FCTL 00D3 00D4 00D5 00D6 00D7 UART1_LCTL UART1_MCTL UART1_LSR UART1_MSR UART1_SPR UART Receive Buffer Register UART Transmit Holding Register UART Baud Rate Generator Register- Byte UART Interrupt Enable Register UART Baud Rate Generator Register- High Byte UART Interrupt Identification Register UART FIFO Control Register UART Line Control Register UART Modem Control Register UART Line Status Register UART Modem Status Register UART Scratch Register
Low-Power Control 00DB 00DC CLK_PPD1 CLK_PPD2 Clock Peripheral Power-Down Register Clock Peripheral Power-Down Register
Real-Time Clock 00E0 00E1 00E2 00E3 RTC_SEC RTC_MIN RTC_HRS RTC_DOW Seconds Register3 Minutes Register3 Register3 Hours Register3 Day-of-the-Week
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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Register
eZ80F92/eZ80F93
Table Register (Continued) Address (hex) Mnemonic Real-Time Clock (continued) 00E4 00E5 00E6 00E7 00E8 00E9 00EA 00EB 00EC 00ED RTC_DOM RTC_MON RTC_YR RTC_CEN RTC_ASEC RTC_AMIN RTC_AHRS RTC_ADOW RTC_ACTRL RTC_CTRL Day-of-the-Month Register3 Month Register3 Register3 Year Register3 Century x0xxx000b/ x0xxxx10b Reset (hex) Page Access
Name
Alarm Seconds Register Alarm Minutes Register Alarm Hours Register Alarm Day-of-the-Week Register Alarm Control Register Control Register4
Chip Select Mode Control 00F0 00F1 00F2 00F3 CS0_BMC CS1_BMC CS2_BMC CS3_BMC Chip Select Mode Control Register Chip Select Mode Control Register Chip Select Mode Control Register Chip Select Mode Control Register
Flash Memory Control Registers 00F5 00F6 00F7 00F8 00F9 00FA FLASH_KEY FLASH_DATA Flash Register Flash Data Register Register5
FLASH_ADDR_U Flash Address Upper Byte Register FLASH_CTRL FLASH_FDIV FLASH_PROT Flash Control Register Flash Frequency Divider Register5 Flash Write/Erase Protection
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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Register
eZ80F92/eZ80F93
Table Register (Continued) Address (hex) Mnemonic Reset (hex) Page Access
Name
Flash Memory Control Registers (continued) 00FB 00FC 00FD 00FE 00FF FLASH_IRQ FLASH_PAGE FLASH_ROW FLASH_COL FLASH_PGCTL Flash Interrupt Control Register Flash Page Select Register Flash Select Register Flash Column Select Register Flash Program Control Register
Notes: After external reset, Watch-Dog Timer Control register reset 00h. After Watch-Dog Timer timeout reset, Watch-Dog Timer Control register reset 20h. When reads this register, current sampled value port read. Read Only registers locked; Read/Write registers unlocked. After external reset Watch-Dog Timer reset, Control register reset x0xxxx00b. After Alarm sleep-mode recovery reset, Control register reset x0xxxx10b. Read Only Flash Memory locked. Read/Write Flash Memory unlocked.
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Register
eZ80F92/eZ80F93
eZ80® Core
eZ80® first 8-bit support linear addressing. Each software module task under real-time executive operating system operate Z80-compatible mode full 24-bit address mode. instruction superset instruction sets Z180 CPUs. Z180 programs executed eZ80® with little modification.
Features
Code-compatible with Z180 products 24-bit linear address space Single-cycle instruction fetch Pipelined fetch, decode, execute Dual Stack Pointers (24-bit) (16-bit) memory modes 24-bit registers (Arithmetic Logic Unit) Debug support Nonmaskable Interrupt (NMI), plus support maskable vectored interrupts
more information about eZ80® instruction set, please refer eZ80 User Manual (UM0077).
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eZ80® Core
eZ80F92/eZ80F93
Reset
Reset Operation
Reset controller within eZ80F92 device provides consistent reset function types resets that affect system. system reset, referred this document RESET, returns eZ80F92 device defined state. internal registers affected RESET return their default conditions. RESET configures GPIO port pins inputs clears CPU's Program Counter 000000h. Program code execution ceases during RESET. events that cause RESET are:
Power-On Reset (POR) Low-Voltage Brown-Out (VBO) External RESET assertion Watch-Dog Timer (WDT) time-out when configured generate RESET Real-Time Clock alarm with low-power SLEEP mode Execution debug reset command
During RESET, internal RESET mode timer holds system RESET mode system clock (SCLK) cycles. RESET mode timer begins incrementing next rising edge SCLK following deactivation RESET events. Note: user must determine SCLK cycles provides sufficient time primary crystal oscillator stabilize.
Power-On Reset
Power-On Reset (POR) occurs each time supply voltage part rises from below voltage brown-out threshold above voltage threshold (VPOR). internal bandgap-referenced voltage detector sends continuous RESET signal Reset controller until supply voltage (VCC) exceeds voltage threshold. After rises above VPOR, on-chip analog delay element briefly maintains RESET signal Reset controller (TANA). After this analog delay, eZ80F92 device RESET mode until RESET mode timer expires. operation illustrated Figure signals this figure drawn scale illustration purposes only.
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Reset
eZ80F92/eZ80F93
VPOR VVBO 0.0V
3.3V
Program Execution
System Clock
Oscillator Startup Internal RESET Signal RESET mode timer delay
Figure 3.Power-On Reset Operation
Voltage Brown-Out Reset
after program execution begins, supply voltage (VCC) drops below Voltage Brown-Out threshold (VVBO), eZ80F92 device resets. protection circuitry detects supply voltage initiates RESET Reset controller. eZ80F92 device remains RESET mode until supply voltage again returns above voltage threshold (VPOR) Reset controller releases internal RESET signal. circuitry rejects very short negative brown-out pulses prevent spurious RESET events. operation illustrated Figure signals this figure drawn scale illustration purposes only.
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Reset
eZ80F92/eZ80F93
3.3V VPOR VVBO Program Execution Voltage Brown-out
3.3V
Program Execution
System Clock
Internal RESET Signal RESET mode timer delay
TANA
Figure 4.Voltage Brown-Out Reset Operation
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PRELIMINARY
Reset
eZ80F92/eZ80F93
Low-Power Modes
Overview
eZ80F92 device provides range power-saving features. highest level power reduction provided SLEEP mode. next level power reduction provided HALT instruction. lowest level power reduction provided clock peripheral power-down registers.
SLEEP Mode
Execution CPU's SLEEP instruction (SLP) places eZ80F92 device into SLEEP mode. SLEEP mode, operating characteristics are:
primary crystal oscillator disabled system clock disabled idle Program Counter (PC) stops incrementing crystal oscillator continues operate drive Real-Time Clock Watch-Dog Timer configured operate from oscillator)
brought SLEEP mode following operations:
RESET external RESET driven RESET Real-Time Clock alarm RESET execution Debug Reset command
After exiting SLEEP mode, standard RESET delay occurs allow primary crystal oscillator stabilize. Refer Reset section page more information. Caution: During SLEEP mode, freezes last address drives address with this value. GPIO ports remain configured user. Prior entering SLEEP mode, data driven control signals MREQ, CS3:0, INSTRD, BUSACK, IOREQ,RD, driven High.
HALT Mode
Execution CPU's HALT instruction places eZ80F92 device into HALT mode. HALT mode, operating characteristics are:
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Low-Power Modes
eZ80F92/eZ80F93
Primary crystal oscillator enabled continues operate system clock enabled continues operate idle Program Counter (PC) stops incrementing
brought HALT mode following operations: nonmaskable interrupt (NMI) maskable interrupt RESET external RESET driven Watch-Dog Timer time-out configured generate either RESET upon time-out) RESET execution Debug RESET command
minimize current HALT mode, system clock should disabled unused on-chip peripherals Clock Peripheral Power-Down Registers. Caution: During HALT mode, freezes last address drives address with this value. GPIO Ports remain configured user. Prior entering HALT mode, data driven control signals MREQ, CS3:0, INSTRD, BUSACK, IOREQ, driven High.
Clock Peripheral Power-Down Registers
reduce power, Clock Peripheral Power-Down Registers allow system clock disabled unused on-chip peripherals. Upon RESET, peripherals enabled. clock unused peripherals disabled setting appropriate Clock Peripheral Power-Down Registers When powered down, peripherals completely disabled. reenable, Clock Peripheral Power-Down Registers must cleared Many peripherals feature separate enable/disable control bits that must appropriately operation. These peripheral specific enable/disable bits provide same level power reduction Clock Peripheral Power-Down Registers. When powered down, standard peripheral control registers accessible Read Write access. Tables
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Low-Power Modes
eZ80F92/eZ80F93
Table Clock Peripheral Power-Down Register (CLK_PPD1 00DBh) Reset Access
Note: Read/Write; Read Only.
Position GPIO_D_OFF
Value Description System clock GPIO Port powered down. Port alternate functions operate correctly. System clock GPIO Port powered System clock GPIO Port powered down. Port alternate functions operate correctly. System clock GPIO Port powered System clock GPIO Port powered down. Port alternate functions operate correctly. System clock GPIO Port powered Reserved. System clock powered down. System clock powered System clock powered down. System clock powered System clock UART1 powered down. System clock UART1 powered System clock UART0 IrDA endec powered down. System clock UART0 IrDA endec powered
GPIO_C_OFF
GPIO_B_OFF
SPI_OFF I2C_OFF UART1_OFF UART0_OFF
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Low-Power Modes
eZ80F92/eZ80F93
Table Clock Peripheral Power-Down Register (CLK_PPD2 00DCh) Reset Access
Note: Read/Write; Read Only.
Position PHI_OFF PRT5_OFF PRT4_OFF PRT3_OFF PRT2_OFF PRT1_OFF PRT0_OFF
Value Description Clock output disabled (output high-impedance). Clock output enabled. Reserved. System clock PRT5 powered down. System clock PRT5 powered System clock PRT4 powered down. System clock PRT4 powered System clock PRT3 powered down. System clock PRT3 powered System clock PRT2 powered down. System clock PRT2 powered System clock PRT1 powered down. System clock PRT1 powered System clock PRT0 powered down. System clock PRT0 powered
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Low-Power Modes
eZ80F92/eZ80F93
General-Purpose Input/Output
GPIO Overview
eZ80F92 device features General-Purpose Input/Output (GPIO) pins. GPIO pins assembled three 8-bit ports- Port Port Port port signals configured either inputs outputs. addition, port pins used vectored interrupt sources CPU.
GPIO Operation
GPIO operation same GPIO ports (Ports Each port features eight GPIO port pins. operating mode each controlled four bits that divided between four 8-bit registers. These GPIO mode control registers are:
Port Data Register (Px_DR) Port Data Direction Register (Px_DDR) Port Alternate Register (Px_ALT1) Port Alternate Register (Px_ALT2)
where representing three GPIO ports mode each controlled setting each register pertinent configured. example, operating mode Port (PB7), values contained PB_DR[7], PB_DDR[7], PB_ALT1[7], PB_ALT2[7]. combination GPIO control register bits allows individual configuration each port nine modes. modes, reading Port Data register returns sampled state, level, signal corresponding pin. Table indicates function each port signal based upon these four register bits. After RESET event, GPIO port pins configured standard digital inputs, with interrupts disabled.
Table GPIO Mode Selection GPIO Mode Px_ALT2 Bits7:0 Px_ALT1 Px_DDR Px_DR Bits7:0 Bits7:0 Bits7:0 Port Mode Output Output Input from Input from
Output High impedance High impedance
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General-Purpose Input/Output
eZ80F92/eZ80F93
Table GPIO Mode Selection (Continued) GPIO Mode Px_ALT2 Bits7:0 Px_ALT1 Px_DDR Px_DR Bits7:0 Bits7:0 Bits7:0 Port Mode Open-drain output Open-drain Open-source Open-source output Reserved Interrupt-dual edge triggered
Output High impedance High impedance High impedance High impedance
Port D-alternate function controls port I/O. Port D-alternate function controls port I/O. Interrupt-active Interrupt-active High High impedance High impedance
Interrupt-falling edge triggered High impedance Interrupt-rising edge triggered High impedance
GPIO Mode port configured standard digital output pin. value writ-
Port Data register (Px_DR) presented pin.
GPIO Mode port configured standard digital input pin. output
tristated (high impedance). value stored Port Data register produces effect. modes, Read from Port Data register returns pin's value. GPIO Mode default operating mode following RESET.
GPIO Mode port configured open-drain I/O. GPIO pins feature
internal pull-up supply voltage. employ GPIO OPEN-DRAIN mode, external pull-up resistor must connect supply voltage. Writing Port Data register outputs pin. Writing Port Data register results high-impedance output.
GPIO Mode port configured open-source I/O. GPIO pins fea-
ture internal pull-down supply ground. employ GPIO OPENSOURCE mode, external pull-down resistor must connect supply ground. Writing Port Data register outputs High pin. Writing Port Data register results high-impedance output.
GPIO Mode Reserved. This produces high-impedance output.
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General-Purpose Input/Output
eZ80F92/eZ80F93
GPIO Mode This enables dual edge-triggered interrupt mode. Both rising
falling edge cause interrupt request sent CPU. Writing Port Data register position resets corresponding interrupt request. Writing produces effect. programmer must Port Data register before entering edge-triggered interrupt mode.
GPIO Mode Ports port configured pass control over
alternate (secondary) functions assigned pin. example, alternate mode function alternate mode function Timer Out. When GPIO Mode enabled, output data tristated control come from alternate function's data output tristate control, respectively. value Port Data register produces effect operation. Note: Input signals sampled system clock before being passed alternate function input.
GPIO Mode port configured level-sensitive interrupt modes. interrupt
request generated when level same level stored Port Data register. port value sampled system clock. input must held selected interrupt level minimum clock periods initiate interrupt. interrupt request remains active long this condition maintained external source.
GPIO Mode port configured single edge-triggered interrupt mode.
value Port Data register determines positive negative edge causes interrupt request. Port Data register sets selected generate interrupt request falling edges. Port Data register sets selected generate interrupt request rising edges. interrupt request remains active until written corresponding interrupt request Port Data register bit. Writing produces effect operation. programmer must Port Data register before entering edge-triggered interrupt mode. simplified block diagram GPIO port illustrated Figure
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General-Purpose Input/Output
eZ80F92/eZ80F93
GPIO Register Data (Input)
System Clock Mode Mode Data System Clock GPIO Register Data (Output) Mode Mode Port
Figure 5.GPIO Port Block Diagram
GPIO Interrupts
Each port used interrupt source. Interrupts either level- edgetriggered. Level-Triggered Interrupts When port configured level-triggered interrupts, corresponding port tristated. interrupt request generated when level same level stored Port Data register. port value sampled system clock. input must held selected interrupt level minimum consecutive clock cycles initiate interrupt. interrupt request remains active long this condition maintained external source. example, programmed low-level interrupt forced consecutive clock cycles, interrupt request signal generated from that port sent CPU. interrupt request signal remains active until external device driving forces High. Edge-Triggered Interrupts When port configured edge-triggered interrupts, corresponding port tristated. receives correct edge from external device, port generates interrupt request signal CPU. time port configured edge-triggered
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General-Purpose Input/Output
eZ80F92/eZ80F93
interrupt, writing that pin's Port Data register causes reset edge-detected interrupt. programmer must Port Data register before entering either single dual edge-triggered interrupt mode that port pin. When configured dual edge-triggered interrupt mode (GPIO Mode both rising falling edge cause interrupt request sent CPU. When configured single edge-triggered interrupt mode (GPIO Mode value Port Data register determines positive negative edge causes interrupt request. Port Data register sets selected generate interrupt request falling edges. Port Data register sets selected generate interrupt request rising edges.
GPIO Control Registers
GPIO Control Registers operate groups four with each Port Each GPIO port features Port Data register, Port Data Direction register, Port Alternate register Port Alternate register Port Data Registers When port pins configured output modes, data written Port Data registers, detailed Table driven corresponding pins. modes, reading from Port Data registers always returns current sampled value corresponding pins. When port pins configured edge-triggered interrupt sources, writing corresponding Port Data register clears interrupt signal that sent CPU. When port pins configured edge-selectable interrupts level-sensitive interrupts, value written Port Data register selects interrupt edge interrupt level. Table more information.
Table Port Data Registers (PB_DR 009Ah, PC_DR 009Eh, PD_DR 00A2h) Reset Access
Note: Undefined; Read/Write.
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eZ80F92/eZ80F93
Port Data Direction Registers conjunction with other GPIO Control Registers, Port Data Direction registers, detailed Table control operating modes GPIO port pins. Table more information.
Table Port Data Direction Registers (PB_DDR 009Bh, PC_DDR 009Fh, PD_DDR 00A3h) Reset Access
Note: Read/Write.
Port Alternate Register conjunction with other GPIO Control Registers, Port Alternate Register detailed Table control operating modes GPIO port pins. Table more information.
Table Port Alternate Registers (PB_ALT1 009Ch, PC_ALT1 00A0h, PD_ALT1 00A4h) Reset Access
Note: Read/Write.
Port Alternate Register conjunction with other GPIO Control Registers, Port Alternate Register detailed Table control operating modes GPIO port pins. Table more information.
Table Port Alternate Registers (PB_ALT2 009Dh, PC_ALT2 00A1h, PD_ALT2 00A5h) Reset Access
Note: Read/Write.
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PRELIMINARY
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eZ80F92/eZ80F93
Interrupt Controller
interrupt controller eZ80F92 device routes interrupt request signals from internal peripherals external devices (via GPIO pins) CPU.
Maskable Interrupts
eZ80F92 device, maskable interrupts CPU's vectored interrupt function. Table lists low-byte vector each maskable interrupt sources. maskable interrupt sources listed order priority, with vector being highest-priority interrupt. full 16-bit interrupt vector located starting address {I[7:0], IVECT[7:0]} where I[7:0] CPU's Interrupt Page Address Register.
Table Interrupt Vector Sources Priority Vector Source Unused Unused Unused Unused Flash UART Vector Source UART Unused Unused Unused Unused Unused Unused Unused Unused Port Port Vector Source Port Port Port Port Port Port Port Port Port Port Port Port Port Vector Source Port Port Port Port Port Port Port Port Port Unused Unused Unused Unused
Note: Absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, reserved hardware reset, NMI, instruction.
user's program should store starting address interrupt service routine (ISR) two-byte interrupt vector locations. example, mode two-byte address interrupt service routine would stored {00h, I[7:0], 1Eh} {00h, I[7:0], 1Fh}. mode, two-byte address interrupt service rou-
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PRELIMINARY
Interrupt Controller
eZ80F92/eZ80F93
tine would stored {MBASE[7:0], I[7:0], 1Eh} {MBASE, I[7:0], 1Fh}. leastsignificant byte stored lower address. When more interrupt requests (IRQs) become active, interrupt request generated interrupt controller sent CPU. corresponding 8-bit interrupt vector highest-priority interrupt placed 8-bit interrupt vector bus, IVECT[7:0]. interrupt vector internal eZ80F92 device therefore visible externally. response time interrupt request function current instruction being executed well number wait states being asserted. interrupt vector, {I[7:0], IVECT[7:0]}, visible address bus, ADDR[15:0], when interrupt service routine begins. response vectored interrupt eZ80F92 device explained Table Interrupt sources required active until interrupt service routine starts. recommended that Interrupt Page Address Register value changed user from default value this address create conflicts between nonmaskable interrupt vector, instruction addresses, maskable interrupt vectors.
Table Vectored Interrupt Operation Memory Mode Mode MADL Operation Read interrupt vector placed internal vectored interrupt bus, IVECT [7:0], interrupting peripheral. IEF1 IEF2 Starting Program Counter effectively {MBASE, PC[15:0]} Push 2-byte return address PC[15:0] onto ({MBASE,SPS}) stack mode remains cleared interrupt vector address located {MBASE, I[7:0], IVECT[7:0]} PC[15:0] ({MBASE, I[7:0], IVECT[7:0]}) ending Program Counter effectively {MBASE, PC[15:0]} interrupt service routine must with RETI Read interrupt vector placed internal vectored interrupt bus, IVECT [7:0], interrupting peripheral. IEF1 IEF2 Starting Program Counter PC[23:0] Push 3-byte return address, PC[23:0], onto stack mode remains interrupt vector address located {00h, I[7:0], IVECT[7:0]} PC[15:0] ({00h, I[7:0], IVECT[7:0]}) ending Program Counter {00h, PC[15:0]} interrupt service routine must with RETI
Mode
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PRELIMINARY
Interrupt Controller
eZ80F92/eZ80F93
Table Vectored Interrupt Operation (Continued) Memory Mode Mode MADL Operation Read interrupt vector placed internal vectored interrupt bus, IVECT[7:0], interrupting peripheral. IEF1 IEF2 Starting Program Counter effectively {MBASE, PC[15:0]} Push 2-byte return address, PC[15:0], onto stack Push byte onto stack indicate interrupt from mode (because mode interrupt vector address located {00h, I[7:0], IVECT[7:0]} PC[15:0] ({00h, I[7:0], IVECT[7:0]}) ending Program Counter {00h, PC[15:0]} interrupt service routine must with RETI.L Read interrupt vector placed internal vectored interrupt bus, IVECT [7:0], interrupting peripheral. IEF1 IEF2 Starting Program Counter PC[23:0] Push 3-byte return address, PC[23:0], onto stack Push byte onto stack indicate restart from mode (because mode remains interrupt vector address located {00h, I[7:0], IVECT[7:0]} PC[15:0] ({00h, I[7:0], IVECT[7:0]}) ending Program Counter {00h, PC[15:0]} interrupt service routine must with RETI.L
Mode
Nonmaskable Interrupts
active input generates interrupt request CPU. This nonmaskable interrupt always serviced regardless state Interrupt Enable flags (IEF1 IEF2). nonmaskable interrupt prioritized higher than maskable interrupts. response nonmaskable interrupt described detail eZ80 User Manual (UM0077).
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Interrupt Controller
eZ80F92/eZ80F93
Chip Selects Wait States
eZ80F92 device generates four Chip Selects external devices. Each Chip Select programmed access either memory space space. Memory Chip Selects individually programmed boundary. Chip Selects each choose 256-byte section space. addition, each Chip Select programmed wait states.
Memory Chip Selects
Each Chip Selects enabled either memory address space address space, both. select memory address space particular Chip Select, CSX_IO (CSx_CTL[4]) must reset select address space particular Chip Select, CSX_IO must After RESET, default Chip Selects configured memory address space. either memory address space address space, individual Chip Selects must enabled setting CSx_EN (CSx_CTL[3])
Memory Chip Select Operation
Operation each Memory Chip Selects controlled three control registers. enable particular Memory Chip Select, following conditions must met:
Chip Select enabled setting CSx_EN Chip Select configured Memory clearing CSX_IO address associated Chip Select range:
CSx_LBR[7:0] ADDR[23:16] CSx_UBR[7:0]
higher priority (lower number) Chip Select meets above conditions memory access instruction must executing
foregoing conditions generate Memory Chip Select, then following actions occur: appropriate Chip Select-CS0, CS1, CS2, CS3-is asserted (driven Low) MREQ asserted (driven Low) Depending upon instruction, either asserted (driven Low)
upper lower bounds same value (CSx_UBR CSx_LBR), then particular Chip Select valid single page.
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Memory Chip Select Priority lower-numbered Chip Select granted priority over higher-numbered Chip Select. example, address space Chip Select overlaps Chip Select address space, Chip Select active. Reset States RESET, Chip Select active addresses, because Lower Bound register resets Upper Bound register resets FFh. other Chip Select Lower Upper Bound registers reset 00h. Memory Chip Select Example Memory Chip Selects demonstrated Figure associated control register values indicated Table this example, Chip Selects enabled configured memory addresses. Also, overlaps with CS0. Because prioritized higher than CS1, active much defined address space.
Memory Location CS3_UBR CS3_LBR CS2_UBR CS2_LBR CS1_UBR Active Address Space Active Address Space Active Address Space FFFFFFh D00000h CFFFFFh A00000h 9FFFFFh 800000h 7FFFFFh
CS0_UBR
Active Address Space
CS0_LBR CS1_LBR
000000h
Figure 6.Example: Memory Chip Select
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eZ80F92/eZ80F93
Table Register Values Memory Chip Select Example Figure Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO CSx_LBR CSx_UBR Description enabled Memory Chip Select. Valid addresses range from 000000h- 7FFFFFh. enabled Memory Chip Select. Valid addresses range from 800000h- 9FFFFFh. enabled Memory Chip Select. Valid addresses range from A00000h- CFFFFFh. enabled Memory Chip Select. Valid addresses range from D00000h- FFFFFFh.
Chip Select Operation
Chip Selects only active when performing instructions. Because space separate from memory space eZ80F92 device, there never conflict between memory addresses. eZ80F92 device supports 16-bit address. Chip Select logic decodes High byte address, ADDR[15:8]. Because upper byte address bus, ADDR[23:16], ignored, devices always accessed from within memory mode (ADL Z80). MBASE offset value used setting MEMORY mode page also always ignored. Four Chip Selects available with eZ80F92 device. generate particular Chip Select, following conditions must met:
Chip Select enabled setting CSX_EN Chip Select configured setting CSX_IO Chip Select address match occurs-ADDR[15:8] CSx_LBR[7:0] higher-priority (lower-number) Chip Select meets above conditions address within on-chip peripheral address range 0080h-00FFh. On-chip peripheral registers assume priority addresses where:
0080h ADDR[15:0] 00FFh
instruction must executing
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eZ80F92/eZ80F93
foregoing conditions generate Chip Select, then following actions occur:
appropriate Chip Select-CS0, CS1, CS2, CS3-is asserted (driven Low) IORQ asserted (driven Low) Depending upon instruction, either asserted (driven Low)
WAIT States
each Chip Selects, programmable WAIT states asserted provide external devices with additional clock cycles complete their Read Write operations. number WAIT states particular Chip Select controlled 3-bit field CSx_WAIT (CSx_CTL[7:5]). WAIT states independently programmed provide WAIT states each Chip Select. WAIT states idle specified number system clock cycles.
WAIT Input Signal
Similar programmable WAIT states, external peripheral drive WAIT input force provide additional clock cycles complete Read Write operation. Driving WAIT stalls CPU. resumes operation first rising edge internal system clock following deassertion WAIT pin. Caution: WAIT driven external device, corresponding Chip Select device must programmed provide least WAIT state. input sampling WAIT input (shown Figure programmable WAIT state required allow external peripheral sufficient time assert WAIT pin. recommended that corresponding Chip Select external device programmed provide maximum number WAIT states (seven).
Wait
eZ80
System Clock
Figure 7.Wait Input Sampling Block Diagram
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eZ80F92/eZ80F93
example WAIT state operation illustrated Figure this example, Chip Select configured provide single WAIT state. external peripheral being accessed drives WAIT request assertion additional WAIT state. WAIT asserted additional system clock cycles, WAIT states added until WAIT deasserted (High).
TCLK
TWAIT
ADDR[23:0]
DATA[7:0] (output)
MREQ
INSTRD
Figure 8.Example: Wait State Operation Read Operation
Chip Selects During Request/Bus Acknowledge Cycles
When relinquishes address external peripheral response external request (BUSREQ), drives acknowledge (BUSACK) Low. external peripheral then drive address (and data bus). continues generate Chip Select signals response address bus. External devices cannot access internal registers eZ80F92 device.
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eZ80F92/eZ80F93
Mode Controller
mode controller allows address data timing signal formats eZ80F92 device configured connect seamlessly with external eZ80®, Z80-, Intel-, Motorola-compatible devices. modes each chip selects configured independently using Chip Select Mode Control Registers. number system clock cycles mode state also independently programmable. Intelbus mode, multiplexed address data selected which lower byte address data byte both data bus, DATA[7:0]. Each modes explained more detail following sections.
eZ80 Mode
Chip selects configured eZ80 mode modify signals from CPU. timing diagrams external Memory Read Write operations shown Characteristics section page 228. default mode each chip select eZ80 mode.
Mode
Chip selects configured mode modify signals match microprocessor address data interface signal format timing. During read operations, mode employs three states (T1, described Table
Table Mode Read States STATE STATE Read cycle begins State drives address onto address associated Chip Select signal asserted. During State signal asserted. Depending upon instruction, either MREQ IORQ signal asserted. external WAIT driven least system clock cycle prior State additional WAIT states (TWAIT) asserted until WAIT driven High. During State signals altered. data latched eZ80F92 device rising edge system clock State
STATE
During Write operations, mode employs states (T1, described Table
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eZ80F92/eZ80F93
Table Mode Write States STATE STATE Write cycle begins State drives address onto address bus, associated Chip Select signal asserted. During State signal asserted. Depending upon instruction, either MREQ IORQ signal asserted. external WAIT driven least system clock cycle prior State additional WAIT states (TWAIT) asserted until WAIT driven High. During State signals altered.
STATE
mode Read Write timing illustrated Figures mode states configured system clock cycles. figures, each mode state system clock cycles duration. Figures also illustrate assertion wait state (TWAIT) external peripheral during each mode cycle.
System Clock TCLK
ADDR[23:0]
DATA[7:0]
WAIT
MREQ IORQ
Figure 9.Example: Mode Read Timing
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eZ80F92/eZ80F93
System Clock
TCLK
ADDR[23:0]
DATA[7:0]
WAIT
MREQ IORQ
Figure 10.Example: Mode Write Timing
IntelBus Mode
Chip selects configured Intelbus mode modify signals duplicate four-state memory transfer similar that found Intel-style microcontrollers. signals eZ80F92 device pins mapped illustrated Figure Intelbus mode, user select either multiplexed nonmultiplexed address data buses. nonmultiplexed operation, address data buses separate. multiplexed operation, lower byte address, ADDR[7:0], also appears data bus, DATA[7:0], during State Intelbus mode cycle. During multiplexed operation, lower byte address also appears address addition data bus.
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eZ80F92/eZ80F93
Mode Controller eZ80 Mode Signals (Pins) INSTRD WAIT MREQ IORQ ADDR[23:0] ADDR[7:0] Multiplexed Controller Intel Signal Equvalents READY MREQ IORQ ADDR[23:0]
DATA[7:0]
DATA[7:0]
Figure 11.IntelBus Mode Signal Mapping
IntelBus Mode (Separate Address Data Buses) During Read operations with separate address data buses, Intelbus mode employs states (T1, described Table
Table IntelBus Mode Read States (Separate Address Data Buses) STATE Read cycle begins State drives address onto address associated Chip Select signal asserted. drives signal High beginning During middle drives facilitate latching address. During State asserts signal. Depending instruction, either MREQ IORQ signal asserted.
STATE
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eZ80F92/eZ80F93
Table IntelBus Mode Read States (Separate Address Data Buses) STATE During State signals altered. external READY (WAIT) driven least system clock cycle prior beginning State additional wait states (TWAIT) asserted until READY driven High. latches Read data beginning State deasserts signal completes Intelbus mode cycle.
STATE
During Write operations with separate address data buses, Intelbus mode employs states (T1, described Table
Table IntelBus Mode Write States (Separate Address Data Buses) STATE Write cycle begins State drives address onto address bus, associated Chip Select signal asserted, data driven onto data bus. drives signal High beginning During middle drives facilitate latching address. During State asserts signal. Depending instruction, either MREQ IORQ signal asserted. During State signals altered. external READY (WAIT) driven least system clock cycle prior beginning State additional WAIT states (TWAIT) asserted until READY driven High. deasserts signal beginning State holds data address buses through cycle completed
STATE STATE
STATE
Intelbus mode timing illustrated Read operation Figure Write operation Figure READY signal (external WAIT pin) driven prior beginning State additional wait states (TWAIT) asserted until READY signal driven High. Intelbus mode states configured system clock cycles. figures, each Intelbus mode state system clock cycles duration. Figures also illustrate assertion WAIT state (TWAIT) selected peripheral.
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eZ80F92/eZ80F93
System Clock
TWAIT
ADDR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure 12.Example: IntelBus Mode Read Timing-Separate Address Data Buses
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eZ80F92/eZ80F93
System Clock
TWAIT
ADDR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure 13.Example: IntelBus Mode Write Timing-Separate Address Data Buses
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eZ80F92/eZ80F93
IntelBus Mode (Multiplexed Address Data Bus) During Read operations with multiplexed address data, Intelbus mode employs states (T1, described Table
Table IntelBus Mode Read States (Multiplexed Address Data Bus) STATE Read cycle begins State drives address onto DATA associated Chip Select signal asserted. drives signal High beginning During middle drives facilitate latching address. During State removes address from DATA asserts signal. Depending upon instruction, either MREQ IORQ signal asserted. During State signals altered. external READY (WAIT) driven least system clock cycle prior beginning State additional WAIT states (TWAIT) asserted until READY driven High. latches Read data beginning State deasserts signal completes Intelbus mode cycle.
STATE
STATE
STATE
During Write operations with multiplexed address data, Intelbus mode employs states (T1, described Table
Table IntelBus Mode Write States (Multiplexed Address Data Bus) STATE Write cycle begins State drives address onto DATA drives signal High beginning During middle drives facilitate latching address. During State removes address from DATA drives Write data onto DATA bus. signal asserted indicate Write operation. During State signals altered. external READY (WAIT) driven least system clock cycle prior beginning State additional wait states (TWAIT) asserted until READY driven High. deasserts Write signal beginning identifying Write operation. holds data address buses through cycle completed
STATE
STATE
STATE
Signal timing Intelbus mode with multiplexed address data illustrated Read operation Figure Write operation Figure figures, each
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Chip Selects Wait States
eZ80F92/eZ80F93
Intelbus mode state system clock cycles duration. Figures also illustrate assertion wait state (TWAIT) selected peripheral.
System Clock
TWAIT
ADDR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure 14.Example: IntelBus Mode Read Timing-Multiplexed Address Data
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Chip Selects Wait States
eZ80F92/eZ80F93
System Clock
TWAIT
ADDR[23:0]
DATA[7:0]
READY
MREQ IORQ
Figure 15.Example: IntelBus Mode Write Timing-Multiplexed Address Data
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Chip Selects Wait States
eZ80F92/eZ80F93
Motorola Mode
Chip selects configured Motorola mode modify signals duplicate eight-state memory transfer similar that found Motorola-style microcontrollers. signals (and eZ80F92 pins) mapped illustrated Figure
Mode Controller eZ80 Mode Signals (Pins) INSTRD WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Motorola Signal Equvalents DTACK MREQ IORQ ADDR[23:0] DATA[7:0]
Figure 16.Motorola Mode Signal Mapping
During Write operations, Motorola mode employs states (S0, described Table
Table Motorola Mode Read States STATE STATE STATE STATE Read cycle starts state drives High identify Read cycle. Entering state drives valid address address bus, ADDR[23:0]. rising edge state asserts During state signals altered.
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Chip Selects Wait States
eZ80F92/eZ80F93
Table Motorola Mode Read States (Continued) STATE During state waits cycle termination signal DTACK (WAIT), peripheral signal. termination signal asserted least full clock period prior rising clock edge inserts WAIT (TWAIT) states until DTACK asserted. Each WAIT state full mode cycle. During state signals altered. During state data from external peripheral device driven onto data bus. rising edge clock entering state latches data from addressed peripheral device deasserts peripheral device deasserts DTACK this time.
STATE STATE STATE
eight states Write operation Motorola mode described Table
Table Motorola Mode Write States STATE STATE STATE STATE STATE Write cycle starts drives High preceding Write cycle leaves Low). Entering drives valid address address bus. rising edge asserts drives Low. During data driven high-impedance state data written placed bus. rising edge asserts waits cycle termination signal DTACK (WAIT). termination signal asserted least full clock period prior rising clock edge inserts WAIT (TWAIT) states until DTACK asserted. Each WAIT state full mode cycle. During signals altered. During signals altered. Upon entering deasserts clock rises drives High. peripheral device deasserts DTACK this time.
STATE STATE STATE
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eZ80F92/eZ80F93
Signal timing Motorola mode illustrated Read operation Figure Write operation Figure these figures, each Motorola mode state system clock cycles duration.
System Clock
ADDR[23:0]
DATA[7:0]
DTACK
MREQ IORQ
Figure 17.Example: Motorola Mode Read Timing
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eZ80F92/eZ80F93
System Clock
ADDR[23:0]
DATA[7:0]
DTACK
MREQ IORQ
Figure 18.Example: Motorola Mode Write Timing
Switching Between Modes Each time mode controller must switch from mode another, there one-cycle system clock delay. extra clock cycle required repeated access modes; required when eZ80F92 device switches eZ80 mode. extra clock cycles shown timing examples. asynchronous nature these protocols, extra delay does impact peripheral communication.
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Chip Selects Wait States
eZ80F92/eZ80F93
Chip Select Registers
Chip Select Lower Bound Register Memory Chip Selects, Chip Select Lower Bound register, detailed Table defines lower bound address range which corresponding Memory Chip Select enabled) active. Chip Selects, this register defines address which ADDR[15:8] compared generate Chip Select. Chip Select lower bound registers reset 00h.
Table Chip Select Lower Bound Register (CS0_LBR 00A8h, CS1_LBR 00ABh, CS2_LBR 00AEh, CS3_LBR 00B1h) CS0_LBR Reset CS1_LBR Reset CS2_LBR Reset CS3_LBR Reset Access
Note: Read/Write.
Position [7:0] CSx_LBR
Value Description 00h- Memory Chip Selects (CSX_IO This byte specifies lower bound Chip Select address range. upper byte address bus, ADDR[23:16], compared values contained these registers determining whether Memory Chip Select signal should generated. Chip Selects (CSX_IO This byte specifies Chip Select address value. ADDR[15:8] compared values contained these registers determining whether Chip Select signal should generated.
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Chip Selects Wait States
eZ80F92/eZ80F93
Chip Select Upper Bound Register Memory Chip Selects, Chip Select Upper Bound registers, detailed Table defines upper bound address range which corresponding Chip Select enabled) active. Chip Selects, this register produces effect. reset state Chip Select Upper Bound register FFh, while reset state other Chip Select upper bound registers 00h.
Table Chip Select Upper Bound Register (CS0_UBR 00A9h, CS1_UBR 00ACh, CS2_UBR 00AFh, CS3_UBR 00B2h) CS0_UBR Reset CS1_UBR Reset CS2_UBR Reset CS3_UBR Reset Access
Note: Read/Write.
Position [7:0] CSx_UBR
Value Description 00h- Memory Chip Selects (CSx_IO This byte specifies upper bound Chip Select address range. upper byte address bus, ADDR[23:16], compared values contained these registers determining whether Chip Select signal should generated. Chip Selects (CSx_IO effect.
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eZ80F92/eZ80F93
Chip Select Control Register Chip Select Control register, detailed Table enables Chip Selects, specifies type Chip Select, sets number WAIT states. reset state Chip Select Control register E8h, while reset state other Chip Select control registers 00h.
Table Chip Select Control Register (CS0_CTL 00AAh, CS1_CTL 00ADh, CS2_CTL 00B0h, CS3_CTL 00B3h) CS0_CTL Reset CS1_CTL Reset CS2_CTL Reset CS3_CTL Reset Access
Note: Read/Write; Read Only.
Position [7:5] CSx_WAIT
Value Description WAIT states asserted when this Chip Select active. WAIT state asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. WAIT states asserted when this Chip Select active. Chip Select configured Memory Chip Select. Chip Select configured Chip Select. Chip Select disabled. Chip Select enabled. Reserved.
CSX_IO
CSx_EN [2:0]
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eZ80F92/eZ80F93
Chip Select Mode Control Register+The Chip Select Mode register, detailed Table configures Chip Select eZ80, Z80, IntelTM, Motorola modes. Changing mode allows eZ80F92 device interface peripherals based Z80-, Intel-, Motorola-style asynchronous interfaces. When mode other than programmed particular Chip Select, CSx_WAIT setting that Chip Select Control Register ignored.
Table Chip Select Mode Control Register (CS0_BMC 00F0h, CS1_BMC 00F1h, CS2_BMC 00F2h, CS3_BMC 00F3h) CS0_BMC Reset CS1_BMC Reset CS2_BMC Reset CS3_BMC Reset Access
Note: Read/Write; Read Only.
Position [7:6] BUS_MODE
Value Description eZ80 mode. mode. Intelbus mode. Motorola mode. Separate address data. Multiplexed address data-appears data DATA[7:0]. Reserved.
AD_MUX
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eZ80F92/eZ80F93
Position [3:0] BUS_CYCLE
Value Description 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 valid. Each mode state clock cycle duration.1, Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration. Each mode state clock cycles duration.
Notes: Setting BUS_CYCLE Intelbus mode causes function properly. external WAIT input mode requires that BUS_CYCLE value greater than BUS_CYCLE produces effect eZ80 mode.
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Chip Selects Wait States
eZ80F92/eZ80F93
Watch-Dog Timer
Watch-Dog Timer Overview
Watch-Dog Timer (WDT) helps protect against corrupt unreliable software, power faults, other system-level problems which place into unsuitable operating states. eZ80F92 features:
Four programmable time-out periods: 218, 222, 225, clock cycles selectable clock sources: system clock Real-Time Clock source (on-chip crystal oscillator 50/60 signal) selectable time-out response: time-out configured generate either RESET nonmaskable interrupt (NMI) time-out RESET indicator flag
Figure illustrates block diagram Watch-Dog Timer.
Data[7:0]
Control Register/ Reset Register WDT_CLK
Clock 28-Bit Upcounter System Clock Control Logic
Time-out Compare Logic (WDT_PERIOD) RESET eZ80
Figure 19.Watch-Dog Timer Block Diagram
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Watch-Dog Timer
eZ80F92/eZ80F93
Watch-Dog Timer Operation
Enabling Disabling Watch-Dog Timer disabled upon RESET. enable WDT, application program must WDT_EN (bit WDT_CTL register. When enabled, cannot disabled without RESET. Time-Out Period Selection There four choices time-out periods WDT-218, 222, 225, system clock cycles. time-out period defined WDT_PERIOD field WDT_CTL register (WDT_CTL[1:0]). approximate time-out periods different clock sources listed Table
Table Watch-Dog Timer Approximate Time-Out Delays Clock Source 32.768 Crystal Oscillator 32.768 Crystal Oscillator 32.768 Crystal Oscillator 32.768 Crystal Oscillator System Clock System Clock System Clock System Clock System Clock System Clock System Clock System Clock Divider Value Time Delay 8.00 1024 4096 13.1 209.7 1.68 6.71 83.9 0.67 2.68
Note: *WDT time-out values should sufficiently long allow Flash operations complete.
RESET Generation Upon time-out, RST_FLAG WDT_CTL register addition, cause RESET send nonmaskable interrupt (NMI) signal CPU. default operation cause RESET. asserts/deasserts rising edge clock. RST_FLAG polled determine source RESET event.
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Watch-Dog Timer
eZ80F92/eZ80F93
NMI_OUT WDT_CTL register then upon time-out, asserts processing. NMI_FLAG polled determine source event.
Watch-Dog Timer Registers
Watch-Dog Timer Control Register Watch-Dog Timer Control register, detailed Table 8-bit Read/Write register used enable Watch-Dog Timer, time-out period, indicate source most recent RESET, select required operation upon time-out.
Table Watch-Dog Timer Control Register (WDT_CTL 0093h) Reset Access
Note: Read only; Read/Write.
Position WDT_EN
Value Description disabled. enabled. When enabled, cannot disabled without RESET. time-out resets CPU. time-out generates nonmaskable interrupt (NMI) CPU. RESET caused external full-chip reset reset. RESET caused time-out. This flag time-out, even NMI_OUT flag poll this determine source RESET NMI. clock source system clock. clock source Real-Time Clock source on-chip oscillator 50/60Hz input RTC_CTRL[4]). Reserved. Reserved. Reserved.
NMI_OUT
RST_FLAG*
[4:3] WDT_CLK
Note: *RST_FLAG only cleared non-WDT RESET.
PS015309-1004
PRELIMINARY
Watch-Dog Timer
eZ80F92/eZ80F93
Position [1:0] WDT_PERIOD
Value Description time-out period clock cycles. time-out period clock cycles. time-out period clock cycles. time-out period clock cycles.
Note: *RST_FLAG only cleared non-WDT RESET.
Watch-Dog Timer Reset Register Watch-Dog Timer Reset register, detailed Table 8-bit Write Only register. Watch-Dog Timer reset when value followed written this register. amount time occur between writing value value, long time-out does occur prior completion.
Table Watch-Dog Timer Reset Register (WDT_RR 0094h) Reset Access
Note: Undefined; Write only.
Position [7:0] WDT_RR
Value Description first Write value required reset prior timeout. second Write value required reset prior time-out. A5h, sequence written WDT_RR, timer reset initial count value, counting resumes.
PS015309-1004
PRELIMINARY
Watch-Dog Timer
eZ80F92/eZ80F93
Programmable Reload Timers
Programmable Reload Timers Overview
eZ80F92 device features Programmable Reload Timers (PRT). Each contains 16-bit downcounter 16-bit reload register. addition, each features clock divider with four selectable taps 256. Each timer individually enabled operate either SINGLE PASS CONTINUOUS mode. timer programmed start, stop, restart from current value, restart from initial value, generate interrupts CPU. Four Programmable Reload Timers (timers 0-3) feature selectable clock source input. input these timers either system clock Real-Time Clock (RTC) source. Timers also used event counting, with their inputs received from GPIO port pin. Output from timers directed GPIO port pin. Each PRTs available eZ80F92 device controlled individually. They share same counters, reload registers, control registers, interrupt signals. simplified block diagram programmable reload timer illustrated Figure
Data[7:0]
Data[7:0]
Reload Registers {TMRx_RR_H, TMRx_RR_L}
Control Register TMRx_CTL
System Clock Source GPIO Data Registers {TMRx_DR_H, TMRx_DR_L} TOUT_EN (Timers only) Adjustable Clock Prescaler 16-Bit Down Counter Control Logic eZ80 Timer
TMRx_IN TMRx_CTL[3:2] (Timers only)
Data[7:0]
Figure 20.Programmable Reload Timer Block Diagram
PS015309-1004
PRELIMINARY
Programmable Reload Timers
eZ80F92/eZ80F93
Programmable Reload Timer Operation
Setting Timer Duration There three factors consider when determining Programmable Reload Timer duration-clock frequency, clock divider ratio, initial count value. Minimum duration timer achieved loading 0001h. Maximum duration achieved loading 0000h, because timer first rolls over FFFFh then continues counting down 0000h. time-out period returned following equation:
Time-Out Period Clock Divider Ratio Reload Value System Clock Frequency
calculate time-out period with above equation when using initial value 0000h, enter reload value 65536 (FFFFh Minimum time-out duration times longer than input clock period generated setting clock divider ratio reload value 0001h. Maximum time-out duration (16,777,216) times longer than input clock period generated setting clock divider ratio 1:256 reload value 0000h. Single Pass Mode SINGLE PASS mode, when end-of-count value, 0000h, reached, counting halts, timer disabled, PRT_EN resets restart timer, must reenable timer setting PRT_EN Timer Control Register. downcounter value reload registers, RST_EN must Timer Control Register. example operating SINGLE PASS mode illustrated Figure Timer register information indicated Table
PS015309-1004
PRELIMINARY
Programmable Reload Timers
eZ80F92/eZ80F93
CLKEN IOWRN
CNTH [7:0] CNTL [7:0]
Figure 21.PRT SINGLE PASS Mode Operation Example
Table SINGLE PASS Mode Operation Example Parameter Enabled Reload Restart Enabled Clock Divider SINGLE PASS Mode Interrupt Enabled Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] TMRx_CTL[6] {TMRx_RR_H, TMRx_RR_L} Value 0004h
Continuous Mode CONTINUOUS mode, when end-of-count value, 0000h, reached, timer automatically reloads 16-bit start value from Timer Reload registers, TMRx_RR_H TMRx_RR_L. Downcounting continues next clock edge. CONTINUOUS mode, continues count until disabled. example operating CONTINUOUS mode illustrated Figure Timer register information indicated Table
PS015309-1004
PRELIMINARY
Programmable Reload Timers
eZ80F92/eZ80F93
Clock (Clock IOWRN Count Value Interrupt Request Write TMRx_CTL Enables
Table CONTINUOUS Mode Operation Example
Table CONTINUOUS Mode Operation Example Parameter Enabled Reload Restart Enabled Clock Divider CONTINUOUS Mode Interrupt Enabled Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] TMRx_CTL[6] {TMRx_RR_H, TMRx_RR_L} Value 0004h
Reading Current Count Value capable reading current count value while timer running. This Read event does affect timer operation. High byte current count value latched during Read byte. Timer Interrupts timer interrupt flag, PRT_IRQ, whenever timer reaches end-of-count value, 0000h, SINGLE PASS mode, when timer reloads start value CONTINUOUS mode. interrupt flag only when timer reaches 0000h reloads) from 0001h. timer interrupt flag when timer loaded with value 0000h, which selects maximum time-out period. programmed poll PRT_IRQ time-out event. Alternatively, interrupt service request signal sent setting IRQ_EN
PS015309-1004
PRELIMINARY
Programmable Reload Timers
eZ80F92/eZ80F93
Then, when end-of-count value, 0000h, reached PRT_IRQ interrupt service request signal passed CPU. PRT_IRQ cleared interrupt service request signal inactivated whenever reads from timer control registers, TMRx_CTL. Timer Input Source Selection Timers feature programmable input source selection. default, input taken from eZ80F92 device's system clock. Alternatively, Timers take their input from port input pins (Timers (Timers Timers also Real-Time Clock source (50, 32768Hz) their clock sources. When timer clock source Real-Time Clock signal, timer decrements second rising edge system clock following falling edge RTC_XOUT pin. input source these timers using Timer Input Source Select register. Event Counter When Timers configured take their inputs from port input pins PB1, they function event counters. event counting, clock divider bypassed. counters decrement every rising edge port pin. port pins must configured inputs. input sampling pins, event input signal frequency limited one-half system clock frequency. Input sampling port pins results counter being updated fifth rising edge system clock after rising edge occurs port pin. Timer Output Programmable Reload Timers (Timers directed GPIO Port output pins (PB4 PB5, respectively). enable Timer feature, GPIO port must configured alternate functions. After reset, Timer Output feature disabled default. GPIO output toggles each time reaches end-of-count value. CONTINUOUS mode operation, disabling Timer Output feature results Timer Output signal period that twice time-out period. Examples Timer Output operation illustrated Figure Table these examples, GPIO output assumed when Timer Output function enabled.
PS015309-1004
PRELIMINARY
Programmable Reload Timers
eZ80F92/eZ80F93
Clock (Clock
IOWRN Count Value Timer Output
Write TMRx_CTL Enables
Figure 22.PRT Timer Output Operation Example Table Timer Operation Example Parameter Enabled Reload Restart Enabled Clock Divider CONTINUOUS Mode Reload Value Control Register(s) TMRx_CTL[0] TMRx_CTL[1] TMRx_CTL[3:2] TMRx_CTL[4] {TMRx_RR_H, TMRx_RR_L} Value 0003h
Programmable Reload Timer Registers
Each programmable reload timer controlled using five 8-bit registers. These registers Timer Control register, Timer Reload Byte register, Timer Reload High Byte register, Timer Data Byte register, Timer Data High Byte register. Timer Control register read written timer reload registers Write Only located same address timer data registers, which Read Only. Timer Control Register Timer Control register, detailed Table used control operation timer, including enabling timer, selecting clock divider, enabling interrupt, selecting between CONTINUOUS SINGLE PASS modes, enabling auto-reload feature.
PS015309-1004
PRELIMINARY
Programmable Reload Timers
eZ80F92/eZ80F93
Table Timer Control Register (TMR0_CTL 0080h, TMR1_CTL 0083h, TMR2_CTL 0086h, TMR3_CTL 0089h, TMR4_CTL 008Ch, TMR5_CTL 008Fh) Reset Access
Note: Read only; Read/Write.
Position PRT_IRQ
Value
Description timer does reach end-of-count value. This reset every time TMRx_CTL register read. timer reaches end-of-count value. IRQ_EN interrupt signal sent CPU. This remains until TMRx_CTL register read. Timer interrupt requ

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