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XRT56L85 FEATURES Power (Typical 14mA) Single Supply 2.048 Mbps O


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Power Line Interface
XRT56L85
FEATURES Power (Typical 14mA) Single Supply 2.048 Mbps Operation Both Directions Receiver Input Balanced Transformer Coupled Capacitively (Twisted Pair) Single Coaxial Capacitive Coupling
APPLICATIONS CEPT Interfaces
GENERAL DESCRIPTION XRT56L85 line interface chip. consists both transmit receive circuitry package. maximum rate chip handle 2.048 Mbps signal level received ORDERING INFORMATION
Part XRT56L85P XRT56L85D
attenuated 10dB cable loss half rate. Total current consumption between 12-16mA +5V.
Package Lead PDIP Lead JEDEC SOIC
Operating Temperature Range -40°C +85°C -40°C +85°C
BLOCK DIAGRAM
Positive Threshold Comparator Negative Threshold Comparator
Buffer RPOS Buffer RCLK
RXDATA+ RXDATA-
Peak Detector
Buffer
RNEG TANK BIAS
Bias RXVCC RXGND TXVCC TPOS TCLK TNEG TXGND
Bias Buffer
BIAS
TXDATA+ Buffer TXDATA-
Figure Block Diagram
Rev. 2.11
E2000
EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017
XRT56L85
CONFIGURATION
RXDATA+ RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC
TXVCC TPOS TCLK TXDATA+ TXGND TXDATATNEG RPOS RNEG
RXDATA+ RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC
TXVCC TPOS TCLK TXDATA+ TXGND TXDATATNEG RPOS RNEG
Lead PDIP (0.300")
Lead SOIC (Jedec, 0.300")
DESCRIPTION
Symbol RXDATA+ Type Description Peak Detector Capacitor. This should connected 0.1µF capacitor Receive Analog Input Positive. signal received from line applied this DATA(-) pin. Data clock from signal applied these pins recovered output RPOS, RNEG, RCLK pins, respectively. Receive Analog Input Negative. description DATA(+). Tank Excitation Output. This output connects side tank circuitry. Bias. This should tied ground through 0.1µF capacitor. Tank Reference. tank circuitry biased this output. Receiver Ground. minimize ground interference separate used ground receiver section. Recovered Receive Clock. Recovered clock signal from signal received DATA(+) DATA(-) pins. This signal output terminal equipment. Receive Supply Voltage. supply voltage Receive Section. Receive Negative Data Output. signal this corresponds receipt negative pulse DATA(+)/RX DATA(-) pins. This compatible signal output terminal equipment. Receive Positive Data Output. signal this corresponds receipt positive pulse DATA(+)/RX DATA pins. This compatible signal outputed terminal equipment. Transmit Negative Data Input. input negative polarity pulse (the negative portion pulse train) transmitted line DATA(+) DATA pins. Transmit Negative Data Output. This pin, along with DATA(+) pin, forms differential driver output, this used drive data down line transformer. Note: This open-collector output. Transmit Ground. Transmit Positive Data Output. Please description DATA(-). Transmit Clock. TPOS TNEG sampled rising edge TCLK. Transmit Positive Data Input. input positive polarity pulse (the positive portion pulse train) transmitted line DATA(+) DATA(-) pins. Transmit Supply Voltage. supply voltage transmit section.
RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC RNEG
RPOS
TNEG TXDATA-
TXGND TXDATA+ TCLK TPOS TXVcc
Rev. 2.11
XRT56L85
ELECTRICAL CHARACTERISTICS
Test Conditions: -40°C +85°C, Unless Otherwise Specified
Parameters Electrical Characteristics Supply Voltage Supply Current Receiver Section Tank Drive Current Clock Output Clock Output High Data Output Data Output High Transmitter Section Driver Output Output Leakage Current Input High Voltage Input Voltage Input Current Input High Current Output Current Electrical Characteristices Receiver Section Input Level Loss Input Signal Alarm Level Input Impedance 2.048MHz Clock Duty Cycle Clock Rise Fall Time Data Pulse Width clock period Measured Between Measured Between Alarm Pull Data/Clock Output High Measured Between With Sinewave Input Measured 2.0V Level Measured 15pF Measured Level, Cable Loss -1.6 Measured =-40mA Measured State Output Pull-up +20V Measured -40mA, 1.0V Measured Output Measured Input Voltage 0.4V Measured Input Voltage 0.4V Measured VOL= 1.0V Measured VCC= Measured 1.6mA Measured =400µA Measured =1.6mA Measured =400µA 4.75 5.25 Total Current (Transmitter Outputs Open Ones Pattern) Min. Typ. Max. Unit Conditions
Transmitter Section Pulse Width 2.048MHz Output Rise Time Output Fall Time Output Fall Imbalance Rev. 2.11 Measured Figure Figure Figure Output Level
XRT56L85
ABSOLUTE MAXIMUM RATINGS Supply Voltage +20V SYSTEM DESCRIPTION Receiver incoming bipolar signal, which attenuated distorted cable applied receiver input, consisting DATA(+) DATA(-) pins, either through balanced transformer, balanced capacitively coupled terminal single-ended coaxial cable (see Figure peak detector following input generates reference positive negative threshold comparator extract positive negative data pulses). Information positive negative data pulses outputed compatible signals pins RPOS RNEG, respectively. More specifically, output signal present RPOS indicates that positive pulse received DATA(+)/RX DATA(-) pins, from incoming bipolar data stream. Likewise output signal present RNEG indicates that negative pulse received DATA(+)/RX DATA(-) pins. This conversion from bipolar signal compatible signals allows digital processing clock data signals terminal equipment. example waveforms compatible recovered clock data output receiver portion chip presented Figure Figure Figure tank circuit tuned Storage Temperature -65°C 150°C appropriate frequency added externally provide appropriate frequency-selective filtering received clock signal. Transmitter transmitter portion chip receives compatible signals transmits corresponding bipolar data stream down line (See Figure TPOS TNEG compatible signals that dictate polarity pulse generated transmitted output bipolar data stream. Both TPOS TNEG inputs sampled rising edge transmit clock, TCLK. DATA(+) DATA(-) pins form differential driver output, this used drive data down line transformer. DATA(+) DATA(-) pins open-collector outputs. When logic "high" signal applied TPOS pin, positive pulse (the positive portion bipolar data stream) will transmitted line DATA(+) DATA(-) pins. Likewise, when logic "high" signal applied TNEG pin, negative pulse will transmitted line DATA(+) DATA(-) pins. illustration waveforms involved this conversion process, Transmitter portion chip presented Figure
Rev. 2.11
XRT56L85
VCC=5V
0.1µF
Output CL=15pF
2.048Mbps Pulse Generator Input
XRT56L85
Figure
244ns <5ns Input Pulse from Generator 1.5V 1.5V 15ns Typ. Output from 15ns Typ. <5ns
Fall Time Pulse Width Rise Time
Figure
Rev. 2.11
XRT56L85
RXDATA+
RCLK Output RPOS Output RNEG Output
TCLK Clock TPOS
TNEG
Bipolar Signal Transformer Output
Figure Receiver Timing Diagram With 1-1-1-1-1-1 Pattern
Rev. 2.11
XRT56L85
RCACON
0.1µF 0.1µF 0.1µF RING 0.1µF 4.7µF TANK BIAS TCLK TPOS TNEG RPOS RNEG RCLK TCLK TPOS TNEG RPOS RNEG RCLK RXDATA+ RXDATABIAS T.E. TXDATA+ TXDATA15 PE65415 1:1:1 RING
XRT56L85
TGND
RING 0.1µF 0.1µF 0.1µF
0.1µF 0.1µF RVCC RGND 56L85TA
0.1µF
L=Tank Coil 415-0804 (1.544 2.048 Mbs) Device 1.544Mbs 60µH 175pF 2.048Mbs 60µH 100pF
Figure Application Circuit XRT56L85
Rev. 2.11
XRT56L85
LEAD PLASTIC DUAL-IN-LINE (300 PDIP)
Rev. 1.00
Seating Plane
INCHES SYMBOL 0.145 0.015 0.115 0.014 0.030 0.008 0.845 0.300 0.240 0.210 0.070 0.195 0.024 0.070 0.014 0.925 0.325 0.280
MILLIMETERS 3.68 0.38 2.92 0.36 0.76 0.20 21.46 7.62 6.10 5.33 1.78 4.95 0.56 1.78 0.38 23.50 8.26 7.11
0.100 0.300 0.310 0.115 0.430 0.160
2.54 7.62 7.87 2.92 10.92 4.06
Note: control dimension inch column
Rev. 2.11
XRT56L85
LEAD SMALL OUTLINE (300 JEDEC SOIC)
Rev. 1.00
Seating Plane
INCHES SYMBOL 0.093 0.004 0.013 0.009 0.447 0.291 0.394 0.016 0.104 0.012 0.020 0.013 0.463 0.299 0.419 0.050
MILLIMETERS 2.35 0.10 0.33 0.23 11.35 7.40 10.00 0.40 2.65 0.30 0.51 0.32 11.75 7.60 10.65 1.27
0.050
1.27
Note: control dimension millimeter column
Rev. 2.11
XRT56L85 Notes
Rev. 2.11
XRT56L85 Notes
Rev. 2.11
XRT56L85
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed inaccuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 2000 EXAR Corporation Datasheet October 2000 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
Rev. 2.11

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