XE88LC01 Sensing Machine Data Acquisition Ultra Low-Power Microco

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XE88LC01 Sensing Machine Data Acquisition Ultra Low-Power Microco

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Data Sheet XE88LC01 Data Acquisition Microcontroller
XE88LC01 Sensing Machine
Data Acquisition Ultra Low-Power Microcontroller
XE88LC01 ultra low-power microcontroller unit (MCU) associated with versatile analog-to-digital converter (ADC) including programmable offset gain pre-amplifier (PGA) XE88LC01 available with chip Multiple-Time-Programmable (MTP) Flash program memory ROM.
product Features
Low-power, high resolution ZoomingADC
1000 gain with offset cancellation bits input multiplexer MIPS supply voltage MIPS, supply
Low-voltage low-power controller operation
Applications
Internet connected appliances Portable, battery operated instruments Piezoresistive bridge sensors HVAC control Motor control
kByte kInstruction) MTP, Byte crystal oscillators reset, interrupt, event sources years Flash retention 55°C
Ordering Information
Reference
XE88LC01MI000 XE88LC01MI027 XE88LC01MI032 XE88LC01RI000 XE88LC01RI027
Memory type Temperature
Flash Flash Flash -40°C 85°C -40°C 85°C -40°C 85°C -40°C 125°C -40°C 125°C
Package
LQFP44 PLL-44L LQFP44
Cool Solutions Wireless Connectivity
XEMICS email: info@xemics.com web: www.xemics.com
Cool Solutions Wireless Connectivity
XEMICS email: info@xemics.com web: www.xemics.com
Data Sheet XE88LC01 Data Acquisition Microcontroller
Detailed Description
packaging date
N9K1444 9920
XE88LC01MI
XEMICS
production identification
device type
Figure 1.1:
Pinout XE88LC01 LQFP44 package
Position TQFP44
Function name
PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) VPP/TEST AC_R(3) AC_R(2) AC_A(7) AC_A(6) AC_A(5) AC_A(4)
Second function name
Type
Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Description
Input Port Input Port Input Port Input-Output Port Input-Output Port Input-Output Port Input-Output Port Input-Output Port Input-Output Port Input-Output Port Input-Output Port Input-Output-Analog Port Data output test programing/ output Input-Output-Analog Port output Input-Output-Analog Port Input-Output-Analog Port Output USRT Input-Output-Analog Port Clock USRT Input-Output-Analog Port Data input input-output USRT Input-Output-Analog Port Emission UART Input-Output-Analog Port Reception UART Test mode/High voltage programing Highest potential node reference Lowest potential node reference input node input node input node input node
testout
Input/Output/Analog Input/Output/Analog Input/Output/Analog
Vhigh
Input/Output/Analog Input/Output/Analog Input/Output/Analog Input/Output/Analog Input/Output/Analog Special Analog Analog Analog Analog Analog Analog
Table 1.1:
Pin-out XE88LC01 LQFP44 (see Table pins performances" page drive capabilities pins)
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Position TQFP44
Function name
AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) Vbat Vreg RESET Vmult OscIn OscOut PA(0)
Second function name
Type
Analog Analog Analog Analog Analog Analog Power Power Analog Input Analog
Description
input node input node input node input node Highest potential node reference Lowest potential node reference Negative power supply, connected substrate Positive power supply Regulated supply Reset (active high) optional voltage multiplier capacitor Connection Xtal/ CoolRISC clock test programing Connection Xtal/ Peripheral clock test programing Input Port Data input test programing/ Counter input Input Port Data clock test programing/ Counter input Input Port Counter input/ Counter capture input Input Port Counter input/ Counter capture input Input Port
ck_cr ptck testin
Analog/Input Analog/Input Input
PA(1) PA(2) PA(3) PA(4)
testck
Input Input Input Input
Table 1.1:
Pin-out XE88LC01 LQFP44 (see Table pins performances" page drive capabilities pins)
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Absolute maximum ratings
Stresses beyond these listed this chapter cause permanent damage device. functional operation implied beyond these conditions. Exposure these conditions extended period affect device reliability.
Parameter
VBAT with respect Input voltage input Storage temperature Storage temperature programmed devices
-0.3V 6.0V VSS-0.3V VBAT+0.3V -55°C 125°C -40°C 85°C
Table 2.1:
Absolute maximum ratings These devices sensitive. Although these devices feature proprietary protection structures, permanent damage occur devices subjected high energy electrostatic discharges. Proper precautions have taken avoid performance degradation loss functionality.
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Electrical Characteristics
specification -40°C 85°C unless otherwise noted. operates 125°C.
Operation conditions
Power supply Operating speed Instruction cycle version version instruction running MIPS running Xtal, halt, timer Xtal, halt, timer Xtal, ready halt, Xtal timer halt, bits halt, bits kHz, gain MIPS, bits MIPS, bits kHz, gain MIPS, bits kHz, gain MIPS, bits kHz, gain 1000 Voltage level detection Prog. voltage Erase time Write/Erase cycles Data retention
0.032
Unit
Remarks
Current requirement
3,4,6
Current requirement
3,4,6
3,4,6
1100 10.8
years years
3,4,6
Flash memory
10.3
85°C, 55°C,
Table 3.1: Note:
Specifications current requirement XE88LC01 Power supply: temperature 27°C. erase cycles. Output loaded. Current requirement divided factor reducing speed accordingly. More cycles possible during development, with restraint retention Power supply: 3.0V, 27°C; chapter Power Consumption page variation current with voltage clock speed variation With clock, instructions using exactly clock cycle Longer erase time degrade retention
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
XE88LC01 power RISC core. internal registers efficient implementation compiler. instruction made generic instructions, coded bits, with addressing modes. instructions executed clock cycle, including conditional jumps multiplication.
complete tool suite development available from XEMICS, including programmer, Ccompiler, assembler, simulator, linker, integrated modern efficient graphical user interface.
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Memory organisation
uses Harvard architecture, that memory organised separated fields: program memory data memory. both memory separated, central processing unit read/write data same time loads instruction. Peripherals system control registers mapped data memory space.
Program memory fitted onto page. Data made several bytes pages.
0h1FFF 01hBFF Program address Data address 0h027F Bytes 0h0080 Peripherals Instruction pipeline bits wide Figure 5.1: Memory organization registers 0h0010 bits wide 0h0000
Program memory instructions instructions
0h0000
Program memory
program memory implemented Multiple Time Programmable (MTP) Flash memory. power consumption memory linear with access frequency significant static current).
Size Flash memory 8192 bits kBytes) Size memory 6144 bits kBytes)
block
size
8192 6144
address
H0000 H1FFF H0000 H1BFF
Table 5.1:
Program addresses memory
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Data memory
data memory implemented static Random-Access Memory (RAM). size bits plus power bytes that require very current when addressed. Programs using low-power instead will even less current.
block
size
address
H0000 H0007 H0080 H027F
Table 5.2:
addresses
Registers list
Left column include register name address. Right columns include name, access read, always when read, write, cleared writing value, cleared writing reset status signal. Empty bits reserved future should written, neither should their read value used purpose change without notice.
Peripherals mapping
block
System control Port Port Port Reserved Event Interrupts control reserved UART Counters Zooming Reserved Reserved Other (VLD) RAM1 RAM2 RAM3
size
16x8 12x8 128x8 256x8 128x8
address
H0000-H0007 H0010-H001F H0020-H0027 H0028-H002F H0030-H0033 H0034-H0037 H0038-H003B H003C-H003F H0040-H0047 H0048-H004F H0050-H0057 H0058-H005F H0060-H0067 H0068-H0073 H0074-H007B H007C-H007F H0080 H00FF H0100 H01FF H0200 H027F
Page
Page
Page Page
Table 6.1:
Peripherals addresses
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Resets
reset source name simplified following registers description. Name mapping next table.
reset source
resetsystem resetSynch resetPOR resetCold resetPad resetPconf resetSleep
name this document
global
cold pconf sleep
Table 6.2:
Reset signal name mapping
power
power small additionnal area with extremely power requirement.
Name Address h0000 h0001 h0002 h0003 h0004 h0005 h0006 h0007
Table 6.3:
power
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
System, oscillators, prescaler watchdog
SleepEn Sleep cold CpuSel sleep
Name Address
RegSysCtrl
EnResWD cold ResWD cold BiasRC cold
EnRes-PConf EnBus-Error cold ResPor ExtClk cold cold ResBus-Error cold EnExtClk cold
h0010, type
RegSysReset
h0011, type
RegSysClock
ResPortA cold ColdXtal sleep RCOnPA0 sleep
ResPad-Deb cold ColdRC sleep DebFast sleep
ResPad cold EnableXtal sleep OutputCkXtal sleep EnableRC sleep OutputCkCPU sleep
h0012, type
RegSysMisc
h0013, type
RegSysWD
h0014
RegSysPre0
WatchDog(3) WatchDog(2) WatchDog(1) WatchDog(0) special special special special ResPre ClearLowPrescal cold RCFreqRange cold RCFreqFine(5) cold RCFreqFine(4) cold RCFreqCoarse(3) cold RCFreqFine(3) cold RCFreqCoarse(2) cold RCFreqFine(2) cold RCFreqCoarse(1) cold RCFreqFine(1) cold RCFreqCoarse(0) cold RCFreqFine(0) cold
h0015
RegSysRCTrim1
h001B
RegSysRCTrim2
h001C
Table 6.4:
System control registers
PortA
PAIn(7) PADeb(7) pconf PAEdge(7) global pconf PARes0(7) global PARes1(7) global
Name Address
RegPAIn
RegPAIn(6) PADeb(6) pconf PAEdge(6) global pconf PARes0(6) global PARes1(6) global
PAIn(5) PADeb(5) pconf PAEdge(5) global pconf PARes0(5) global PARes1(5) global
PAIn(4) PADeb(4) pconf PAEdge(4) global pconf PARes0(4) global PARes1(4) global
PAIn(3) PADeb(3) pconf PAEdge(3) global pconf PARes0(3) global PARes1(3) global
PAIn(2) PADeb(2) pconf PAEdge(2) global pconf PARes0(2) global PARes1(2) global
PAIn(1) PADeb(1) pconf PAEdge(1) global pconf PARes0(1) global PARes1(1) global
PAIn(0) PADeb(0) pconf PAEdge(0) global pconf PARes0(0) global PARes1(0) global
h0020
RegPADebounce
h0021
RegPAEdge
h0022
RegPAPullup
PAPullUp(7) PAPullUp(6) PAPullUp(5) PAPullUp(4) PAPullUp(3) PAPullUp(2) PAPullUp(1) PAPullUp(0)
h0023, type
RegPARes0
h0024
RegPARes1
h0025
Table 6.5:
Port registers
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
PortB
PBOut(7) pconf RegPBIn PBIn(7) RegPBDir PBDir(7) pconf PBOpen(7) pconf pconf
Name Address
RegPBOut
PBOut(6) pconf PBIn(6) PBDir(6) pconf PBOpen(6) pconf pconf
PBOut(5) pconf PBIn(5) PBDir(5) pconf PBOpen(5) pconf pconf
PBOut(4) pconf PBIn(4) PBDir(4) pconf PBOpen(4) pconf pconf
PBOut(3) pconf PBIn(3) PBDir(3) pconf PBOpen(3) pconf pconf PBAna(3) pconf
PBOut(2) pconf PBIn(2) PBDir(2) pconf PBOpen(2) pconf pconf PBAna(2) pconf
PBOut(1) pconf PBIn(1) PBDir(1) pconf PBOpen(1) pconf pconf PBAna(1) pconf
PBOut(0) pconf PBIn(0) PBDir(0) pconf PBOpen(0) pconf pconf PBAna(0) pconf
h0028 h0029 h002A
RegPBOpen
h002B
RegPBPullup
PBPullUp(7) PBPullUp(6) PBPullUp(5) PBPullUp(4) PBPullUp(3) PBPullUp(2) PBPullUp(1) PBPullUp(0)
h002C
RegPBAna
h002D
Table 6.6:
Port registers
PortC
PCOut(7) pconf PCIn(7) RegPCDir PCDir(7) pconf
Name Address
RegPCOut
PCOut(6) pconf PCIn(6) PCDir(6) pconf
PCOut(5) pconf PCIn(5) PCDir) pconf
PCOut(4) pconf PCIn(4) PCDir(4) pconf
PCOut(3) pconf PCIn(3) PCDir(3) pconf
PCOut(2) pconf PCIn(2) PCDir(2) pconf
PCOut(1) pconf PCIn(1) PCDir(1) pconf
PCOut(0) pconf PCIn(0) PCDir(0) pconf
h0030
RegPCIn
h0031 h0032
Table 6.7:
Port registers
Name Address
RegEEP
h0038
RegEEP1
RegEEP2 special special
special special
special special
special special
special special
special special
special special
special special
h0039 h003A
RegEEP3
h003B
Table 6.8:
control registers
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Events
EvnCntA rc1, global EvnEnCntA global global
Name Address
RegEvn
EvnCntC rc1, global EvnEnCntC global global
EvnPre1 rc1, global EvnEnPre1 global global
EvnPA(1) rc1, global EvnEnPA(1) global global
EvnCntB rc1, global EvnEnCntB global global
EvnCntD rc1, global EvnEnCntD global global
EvnPre2 rc1, global EvnEnPre2 global global EvnHigh global
EvnPA(0) rc1, global EvnEnPA(0) global global EvnLow global
h003C
RegEvnEn
h003D
RegEvnPriority
EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0)
h003E
RegEvnEvn
h003F
Table 6.9:
Events control registers
6.10
Interrupts
IrqAc rc1, global
Name Address
RegIrqHig
IrqPre1 rc1, global
IrqCntA rc1, global
IrqCntC rc1, global IrqPre2 rc1, global IrqPA(3) rc1, global IrqEnCntC global IrqEnPre2 global IrqEnPA(3) global IrqPriority(3) global
IrqUartTx rc1, global
IrqUartRx rc1, global IrqPA(0) rc1, global
h0040
RegIrqMid
IrqPA(5) rc1, global IrqPA(7) rc1, global IrqEnAc global IrqPA(6) rc1, global IrqEnPre1 global IrqEnPA(5) global IrqEnPA(7) global IrqPriority(7) global IrqEnPA(6) global IrqPriority(6) global IrqEnCntB global IrqPriority(5) global IrqCntB rc1, global
IrqPA(4) rc1, global IrqCntD rc1, global IrqEnCntA global IrqEnPA(4) global IrqEnCntD global IrqPriority(4) global
IrqVld rc1, global IrqPA(2) rc1, global
IrqPA(1) rc1, global
h0041
RegIrqLow
h0042
RegIrqEnHig
IrqEnUartTx global IrqEnVld global IrqEnPA(2) global IrqPriority(2) global IrqHig global IrqPriority(1) global IrqMid global IrqEnPA(1) global
IrqEnUartRx global IrqEnPA(0) global
h0043
RegIrqEnMid
h0044
RegIrqEnLow
h0045
RegIrqPriority
IrqPriority(0) global IrqLow global
h0046
RegIrqIrq
h0047
Table 6.10:
Interrupts control registers
6.11
USRT
UsrtSin global UsrtScl global UsrtWaitS0 global UsrtEnWaitCond1 global UsrtEnWaitS0 global UsrtEnable global UsrtData UsrtEdgeScl global
Name Address
RegUsrtSin
h0048
RegUsrtScl
h0049
RegUsrtCtrl
h004A
RegUsrtData
h004D
RegUsrtEdgeScl
h004E
Table 6.11:
USRT control registers
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
6.12
UART
UartEcho global SelXtal global UartTx(7) global
Name Address
RegUartCtrl
UartEnRx global UartWakeup global UartTx(6) global
UartEnTx global UartRCSel(2) global UartTx(5) global
UartXRx global UartRCSel(1) global UartTx(4) global
UartXTx global UartRCSel(0) global UartTx(3) global
UartBR(2) global UartPM global UartTx(2) global
UartBR(1) global UartPE global UartTx(1) global UartTxBusy global
UartBR(0) global UartWL global UartTx(0) global UartTxFull global UartRx(0) UartRxFull
h0050
RegUartCmd
h0051
RegUartTx
h0052
RegUartTxSta
h0053
RegUartRx UartRx(7) UartRx(6) UartRx(5) UartRxSErr UartRx(4) UartRxPErr UartRx(3) UartRxFErr UartRx(2) UartRxOErr
UartRx(1) UartRxBusy
h0054
RegUartRxSta
h0055
Table 6.12:
UART control registers
6.13
Counters
CounterA(7) CounterB(7) RegCntC CounterC(7) CounterD(7) CntDSel(1) CapSel(1) global
Name Address
RegCntA
CounterA(6) CounterB(6) CounterC(6) CounterD(6) CntDSel(0) CapSel(0) global
CounterA(5) CounterB(5) CounterC(5) CounterD(5) CntCSel(1) CapFunc(1) global
CounterA(4) CounterB(4) CounterC(4) CounterD(4) CntCSel(0) CapFunc(0) global
CounterA(3) CounterB(3) CounterC(3) CounterD(3) CntBSel(1) CascadeCD CntDEnable global
CounterA(2) CounterB(2) CounterC(2) CounterD(2) CntBSel(0) CascadeAB CntCEnable global
CounterA(1) CounterB(1) CounterC(1) CounterD(1) CntASel(1) CntPWM1 global CntBEnable global
CounterA(0) CounterB(0) CounterC(0) CounterD(0) CntASel(0) CntPWM0 global CntAEnable global
h0058
RegCntB
h0059 h005A
RegCntD
h005B
RegCntCtrlCk
h005C
RegCntConfig1
CntDDownUp CntCDownUp CntBDownUp CntADownUp
h005D
RegCntConfig2
PWM1Size(1) PWM1Size(0) PWM0Size(1) PWM0Size(0)
h005E
RegCntOn
h005F
Table 6.13:
Counters control registers
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
6.14
Acquisition chain
AdcOutL(7) AdcOutM(7) Start r0w, global global Fin(1) global Pga1Gain global
Name Address
RegAcOutLsb
AdcOutL(6) AdcOutM(6) NelConv(1) global global Fin(0) global Pga3Gain(6) global Pga3Off(6) global
AdcOutL(5) AdcOutM(5) NelConv(0) global IbAmpPga(1) global Pga2Gain(1) global Pga3Gain(5) global Pga3Off(5) global AMux(4) global
AdcOutL(4) AdcOutM(4) OSR(2) global IbAmpPga(0) global Pga2Gain(0) global Pga3Gain(4) global Pga3Off(4) global AMux(3) global
AdcOutL(3) AdcOutM(3) OSR(1) global Enable(3) global Pga2Off(3) global Pga3Gain(3) global Pga3Off(3) global AMux(2) global
AdcOutL(2) AdcOutM(2) OSR(0) global Enable(2) global Pga2Off(2) global Pga3Gain(2) global Pga3Off(2) global AMux(1) global
AdcOutL(1) AdcOutM(1) Cont global Enable(1) global Pga2Off(1) global Pga3Gain(1) global Pga3Off(1) global AMux(0) global
AdcOutL(0) AdcOutM(0)
h0060
RegAcOutMsb
h0061
RegAcCfg0
h0062
RegAcCfg1
IbAmpADC(1) IbAmpAdc(0)
Enable(0) global Pga2Off(0) global Pga3Gain(0) global Pga3Off(0) global VMux global
h0063
RegAcCfg2
h0064
RegAcCfg3
h0065
RegAcCfg4
h0066
RegAcCfg5 Busy global
h0067
Table 6.14:
Acquisition chain control registers
6.15
Vmult registers
Enable VldMult cold global VldTune(2) cold VldIrq global
Name Address
RegVmultCfg0
Fin(1) global VldTune(1) cold VldValid global
Fin(0) global VldTune(0) cold VldEn global
h007C
RegVldCtrl
h007E
RegVldStat
h007F
Table 6.15:
Vmult control registers
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Peripherals
XE88LC01 includes usual microcontroller peripherals some other blocks more specific low-voltage mixed-signal operation. They parallel ports, input port (A), analog port with analog switching capabilities general purpose port (C). watchdog available, connected prescaler. Four 8-bit counters, with capture, chaining capabilities available. UART handle transmission speeds high 115kbaud. Low-power low-voltage blocks include voltage level detector, oscillators (one internal 0.1-2 oscillator crystal oscillator) specific regulation scheme that largely uncouples current requirement from external power supply (usual CMOS ASICs require much more current than they need This case XE88LC01). Analog blocks (ZoomingADC (acquisition path)) defined below. these blocks operate power supply range.
Counters
8-bit counters Daisy chain bits 8-16 bits Capture compare bits Events interrupts generation
Prescaler
Interrupt generated with second period ultra power hibernation mode
Watchdog
seconds watchdog
UART
full duplex operation with buffered receiver transmitter. Internal baudrate generator with programmable baudrate (300 115000 bauds). bits word length. even, odd, no-parity generation detection stop error receive detection Start, Parity, Frame Overrun receiver echo mode interrupts (receive full transmit empty) enable receive and/or transmit invert and/or
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Xtal clock
Xtal Oscillator operates with external crystal 32'768
symbol
f_clk32k st_x32k duty_clk32k fstab_1
description
nominal frequency oscillator start-up time duty cycle digital output relative frequency deviation from nominal, crystal with CL=8.2 temperature between -40° +85°C
32768
+300
unit
comments
full precision
-100
included: crystal frequency tolerance aging crystal frequency temperature dependence
Table 7.1: Note:
Xtal oscillator specifications. Board layout recommendations safer crystal oscillation lower current consumption: Keep lines xtal_in xtal_out short insert line between them. Connect package crystal VSS. noisy digital lines near xtal_in xtal_out. Insert guards where needed.
oscillator
Oscillator always turned power-on reset turned after optional Xtal oscillator been started. oscillator frequency ranges: sub-MHz (100KHz 1MHz) above-MHz (1MHz frequency). Inside range, frequency tuned software coarse fine adjustment.
Note:
external component required oscillator. oscillator modes. mode 1(RC on), oscillator bias mode ready), oscillator bias mode off), oscillator bias off. ready mode compromise between power consumption start-up time.
Figure 7.1:
frequencies programming example range (typical values)
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
symbol
range mult[3:0] tune[5:0]
description
frequency start-up range selection coarse tuning range fine tuning range fine tuning step start-up time overshoot start-up wakeup time overshoot wakeup jitter
0.65
unit
comments
multiplies bits, multiplies range bits, multiplies range mult
bias current off) bias current off) bias current ready) bias current ready)
Table 7.2:
specifications
Parallel ports
input port with interrupt, reset event generation. input-output-analog port with analog switching capabilities. input-output port
description
Port threshold limit Port high threshold limit output drop when sinking output drop when sourcing Port threshold limit Port high threshold limit output drop when sinking output drop when sinking output drop when sourcing output drop when sourcing Port threshold limit Port high threshold limit output drop when sinking output drop when sinking output drop when sourcing output drop when sourcing pull-up, pull-down resistor
condition
Vbat
unit
kohm
Comments
Vbat
Vbat
Table 7.3:
pins performances
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Voltage level detector
switched off, simultaneously with activities Generates interrupt power supply below pre-determined level
Voltage Level Detector monitors state system battery. returns logical high value interrupt) status register supplied voltage drops below user defined level.
symbol description
Note
unit
comments
trimming values: VldRange Note Note VldTune
Threshold voltage
1.53 1.44 1.36 1.29 1.22 1.16 1.11 1.06 3.06 2.88 2.72 2.57 2.44 2.33 2.22 2.13 1350
TEOM
duration measurement Minimum pulse width detected
Table 7.4: Note:
Voltage level detector operation Absolute precision threshold voltage ±10%. This timing respected case internal crystal oscillators selected. Refer clock block documentation case external clock used.
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
ZoomingADC
fully differential acquisition chain formed programmable gain (0.5 1000) offset amplifier programmable speed resolution (example: bits kHz, bits kHz). handle inputs with very full scale signal large offsets. AC_R(0) AC_R(1) AC_R(2) AC_R(3) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) AC_A(6) AC_A(7) reference selection
gain1 input selection gain2 offset2 gain3 offset3 mode output code
Figure 8.1:
Acquisition channel block diagram Input selection made from differential pairs seven single signal versus AC_A(0). Reference chosen from differential references. Acquisition path offset suppressed inverting input polarity. gain each amplifier programmed individually. Each amplifier powered command minimize total current requirement. blocks frequency operation lower their current requirement factor continuously (end conversion signalled interrupt, event pooling ready bit), started request.
symbol
GD_preci GD_TC Zin1 Zin1p
description
PGA1 Signal Gain Precision gain settings Temperature dependency gain settings input sampling frequency Input impedance Input impedance gain Input referred noise
1500
unit
ppm/°C sqrt(Hz)
Comments
28.6
Table 8.1: Note:
PGA1 Performances Measured with block connected inputs through AMUX block. Normalized input sampling frequency input impedance kHz. This figure multiplied kHz. Input referred noise input sample with gain 20.5 with gain This corresponds 28.6 nV/sqrt(Hz) gain
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
PGA2
GDoff2 GDoff2_step GD_preci GD_TC Zin2
description
PGA2 Signal Gain PGA2 Offset Gain GDoff2(code+1) GDoff2(code) Precision gain settings Temperature dependency gain settings Input sampling frequency Input impedance Input referred noise
0.18
0.22
unit
ppm/°C sqrt(Hz)
Comments
valid GDoff2
47.5
Table 8.2: Note:
PGA2 Performances Measured with block connected inputs through AMUX block. Normalized input sampling frequency input impedance kHz. This figure multiplied kHz. Input referred noise input sample with gain with gain 10.This corresponds 47.5 nV/sqrt(Hz) gain
PGA3
GDoff3 GD3_step GDoff3_step GD_preci GD_TC Zin3
description
PGA3 Signal Gain PGA3 Offset Gain GD3(code+1) GD3(code) GDoff2(code+1) GDoff2(code) Precision gain settings Temperature dependency gain settings Input sampling frequency Input impedance Input referred noise
0.075 0.075
0.085 0.085
unit
ppm/°C
Comments
0.08 0.08
valid GDoff3
51.0
sqrt(Hz)
Table 8.3: Note:
PGA3 Performances Measured with block connected inputs through AMUX block. Normalized input sampling frequency input impedance kHz. This figure multiplied kHz. Input referred noise imput sample with gain 36.5 with gain This corresponds 51.0 nV/sqrt(Hz) kHz.
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Analog digital converter (ADC)
whole analog digital conversion sequence basically made initialisation, Nelconv elementary incremental conversions finally termination phase(NumCONV bits RegACCfg0). result mean results elementary conversions.
input sample
smax
smax
smax
START conversion index
elementary conversion
elementary conversion
elementary conversion NumConv-1
elementary conversion NumConv
Figure 8.2:
Conversion sequence. smax oversampling rate.
Note: NumCONV elementary conversions performed, each elementary conversion being made smax input samples. NumCONV 2NELCONV smax 8*2OSR During elementary conversions, operation converter same sigma delta modulator. During conversion sequence, elementary conversions alternatively performed with direct crossed PGA-ADC differential inputs, that when elementary conversions more performed, offset converter cancelled.
Some additional clock cycles (NINIT+NEND) clock cycles used initiate terminate conversion properly.
performances
VINR Resol NResol smax NUMCONV Ninit Nend
description
Input range Resolution Numerical resolution Differential non-linearity Integral non-linearity sampling frequency Oversampling Ratio Number elementary conversions incremental mode Number periods incremental conversion initialization Number periods incremental conversion termination
-0.5 -0.1
1024
unit
Vref bits bits
Comments
bits bits
Table 8.4: Note: Note:
Performances Only powers defined deviation transfer curve from best straight line. This specifi-
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
cation holds over 100% full scale. NResol maximal readable resolution digital filter.
resolution
conditions
oversampling convertion conversion offset rejection) oversampling convertion conversion offset rejection) oversampling convertion conversion offset rejection) oversampling convertion convertions (offset rejection) oversampling convertion convertion offset rejection) oversampling convertion convertions (offset rejection) oversampling convertion 1024 convertions (offset rejection)
input frequency. convertion time. output frequency.
16.5
Table 8.5:
performances examples
Linearity
quantify linearity errors, Integral Non-Linearity (INL) Differential Non-Linearity (DNL) were measured alone gains 100, 1000, resolution bits bits. defined deviation LSB) transfer curve each individual code from best-fit straight line. This specification holds over full scale. defined difference LSB) between ideal LSB) measured code transitions successive codes. specified after gain offset errors have been removed.
Integral Non-Linearity (INL) Differential Non-Linearity (DNL) 12-bit resolution
bits converter PGA; only) (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter PGA; only) (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
0.50
Integral Non-Linearity (INL) [LSB]
-0.2 -0.4 -0.6 -0.8 -1.0 1000 1500 2000 2500
Differential Non-L inearity (DNL
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 1000 1500 2000 2500
[mV]
[mV]
Figure 8.3:
GAIN (ONLY ADC), setting
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
0.50
Integral Non-Linearity (INL) [LSB]
-0.5 -1.0 -1.5 -2.0 1000 1500 2000 2500
Differential Non-Linearity (DNL) [LSB]
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 1000 1500 2000 2500
[mV]
[mV]
Figure 8.4:
GAIN=1, setting
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits onve (GDtot rsion
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
0.50
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30
-0.5 -1.0 -1.5
[mV]
[mV]
Figure 8.5:
GAIN=5, setting
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
0.50
Integral Non-Linearity (INL) [LSB]
-0.5 -1.0 -1.5 -2.0
Differential Non-Linearity (DNL) [LSB]
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50
[mV]
[mV]
Figure 8.6:
GAIN=10, setting
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
0.60
Integral Non-Linearity (INL) [LSB]
-0.2 -0.4 -0.6 -0.8
Differential Non-Linearity (DNL) [LSB]
0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80
[mV]
[mV]
Figure 8.7:
GAIN=20, setting
bits converter (GDtot 100) (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot 100) (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
1.00
Integral Non-Linearity (INL) [LSB]
-1.0 -2.0 -3.0 -4.0
Differential Non-Linearity (DNL) [LSB]
0.50 0.00 -0.50 -1.00 -1.50
[mV]
[mV]
Figure 8.8:
GAIN=100, setting
bits converter (GDtot 1000) (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot 1000) (version v5a)
Vbat Vref 5.0V; 500kHz; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
Differential Non-L inearity (DNL
Integral Non-Linearity (INL) [LSB]
-2.0 -4.0 -6.0
-0.5 -1.0 -1.5 -2.0
10*VIN [mV]
10*V [mV]
Figure 8.9:
GAIN=1000, setting
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Integral Non-Linearity (INL) Differential Non-Linearity (DNL) 16-bit resolution
bits converter PGA; only) rsion
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits onve rter PGA; only) rsion
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
1000 1500 2000 2500
0.10
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
0.05 0.00 -0.05 -0.10 -0.15 1000 1500 2000 2500
[mV]
[mV]
Figure 8.10:
GAIN (ONLY ADC), setting
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
25.0 15.0 10.0 -5.0 -10.0 -15.0 -20.0 -25.0 1000 1500 2000 2500
0.10
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
20.0
0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 1000 1500 2000 2500
[mV]
[mV]
Figure 8.11:
GAIN=1, setting
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
10.0
0.15
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
-5.0 -10.0 -15.0 -20.0
0.10 0.05 0.00 -0.05 -0.10 -0.15
[mV]
[mV]
Figure 8.12:
GAIN=5, setting
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
0.25
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25
[mV]
[mV]
Figure 8.13:
GAIN=10, setting
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
Integral Non-Linearity (INL) [LSB]
Differential Non-Linearity (DNL) [LSB]
-0.2 -0.4 -0.6
[mV]
[mV]
Figure 8.14:
GAIN=20, setting
bits converter (GDtot 100) (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot 100) (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
-0.2 -0.4 -0.6 -0.8 -1.0
[mV]
[mV]
Figure 8.15:
GAIN=100, setting
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
bits converter (GDtot 1000) (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
bits converter (GDtot 1000) (version v5a)
Vbat Vref 5.0V; 500kHz; 512; NELCONV 2MHz; IB_AMP(1:0) Vinn=0V sweep 1201; average samples
Integral Non-Linearity (INL) [LSB]
Differential Non-Linearity (DNL) [LSB]
-0.5 -1.0 -1.5 -2.0
10*VIN [mV]
10*VIN [mV]
Figure 8.16:
GAIN=1000, setting
gain settings each stage plots above figure those table below.
Gain GDTOT (V/V)
1000
PGA1 Gain (V/V)
PGA2 Gain (V/V)
bypassed bypassed
PGA3 Gain (V/V)
bypassed bypassed bypassed bypassed bypassed
Table 8.6: Table 8.7:
Individual gains measurements
8.10 Noise
Ideally, constant input voltage should result constant output code. However, because circuit noise, output code vary fixed input voltage. figure shows distribution alone (PGA1, bypassed) several configurations PGAs. Quantization noise dominant this case only, and, thus, thermal noise negligible. considere points when computing final noise acquisition chain: this type amplifier (switched-cap with constant capacitive load) that maintains output noise when changing gain. Therefore input refered noise lowered when gain amplifier increased. oversampled, number samples taken lowers thermal noise
Total input refered noise computed using following equation: out1 out2 out3 gain1 gain1 gain2 gain1 gain2 gain3 -numconv smax
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Where Vn,outx output noise amplifier
Amplifier
PGA1 PGA2 PGA3
Symbol
Vn,out1 Vn,out2 Vn,out3
Typical output noise over-sample
Unit
uVrms uVrms uVrms
Typical output noise ZoomingADC preamplifiers
only
PGA1: PGA2: PGA3:
PGA1: PGA2: PGA3:
PGA1: PGA2: PGA3:
PGA1: PGA2: PGA3:
Figure 8.17:
Noise measured output ZoomingADC figures above, increase gain first amplifier lowers output noise constant global gain. also lowers sensitivity temperature drift offset better compensated first amplifier.
8.11 Gain Error Offset Error
Gain error defined amount deviation between ideal transfer function measured transfer function (with offset error removed). left figure shows gain error temperature different gains. curves expressed Full-Scale Range (FSR) normalized 25°C.
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Offset error defined output code error zero volt input (ideally, output code measured offset errors temperature curves different gains depicted right figure below. output offset error, expressed (LSB), normalized 25°C.
-0.1 -0.2 -0.3 -0.4
Output Offset Error [LSB]
Gain Error FSR]
Temperature [°C]
Temperature [°C]
Figure 8.18:
Gain offset error temperature several gains, normalized 25°C, offset cancellation disabled. When offset cancellation enabled, offset remains below temperature situations.
8.12 Power Consumption
Left figure below plots variation quiescent current consumption with supply voltage VDD, well distribution between stages ADC. shown right figure, quiescent current consumption greatly affected sampling frequency. seen that quiescent current varies about between 100kHz 2MHz. Quiescent current consumption temperature shown second figures, showing relative increase nearly between +85°C.
Quiescent Current
PGA1,
Quiescent Current
Sampling Frequency 500kHz
250kHz 62.5kHz
PGA1 only
PGA1 only
PGAs, only
Supply Voltage VDDA
Supply Voltage VDDA
Figure 8.19:
Quiescent current versus supply voltage different gains clock speed (not using power modes)
Supply
PGA1
PGA2
PGA3
TOTAL
Unit
Table 8.8:
Typical quiescent current distributions acquisition chain bits, 500kHz)
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Relative Quiescent Current Change IQ,25°C
Quiescent Current Temperature [°C]
Temperature [°C]
Figure 8.20:
Absolute relative change quiescent current consumption temperature
Relative Quiescent Current Change IQ,2MHz
1000 1500 2000 2500 3000 3500
Quiescent Current Frequency [kHz]
1000 1500 2000 2500 3000 3500
Frequency [kHz]
Figure 8.21:
Absolute relative change quiescent current consumption clock speed
8.13 Power Supply Rejection Ratio
Figure below shows power supply rejection ratio (PSRR) supply voltage, various gains. PSRR defined ratio voltage supply change change converter output PSRR depends both gain supply voltage VDD.
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
VDD=3V VDD=5V
PSRR [dB]
Gain [V/V]
Figure 8.22:
Power supply rejection ratio (PSRR)
Supply
GAIN
GAIN
GAIN
GAIN
GAIN =100
Unit
Table 8.9:
PSRR bits, VREF 2.5V, 500kHz)
8.14 Frequency Response
incremental XE88LC01 over-sampled converter with main blocks: analog modulator low-pass digital filter. main function digital filter remove quantization noise introduced modulator. shown below, this filter determines frequency response transfer function between output analog input VIN. Notice that frequency axes normalized elementary conversion period OSR/fS. plots below also show that frequency response changes with number elementary conversions NELCONV performed. particular, notches appear NELCONV These notches occur
NOTCH
ELCONV (Hz)for 1,2,., ELCONV
repeated every fS/OSR. Information location these notches particularly useful when specific frequencies must filtered acquisition system. example, consider 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection needed. Using above equation plots below, notch NELCONV 50Hz, i.e. 1.25fS/OSR 50Hz. sampling frequency then calculated 20.48kHz 512. Notice that this choice yields also good attenuation 50Hz harmonics.
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Normalized Magnitude
Normalized Magnitude
Normalized Frequency *(OSR/fS)
Normalized Frequency *(OSR/fS)
NELCONV
NELCONV
Normalized Magnitude
Normalized Magnitude
Normalized Frequency *(OSR/fS)
Normalized Frequency *(OSR/fS)
NELCONV
NELCONV
Figure 8.23:
Frequency response: normalized magnitude frequency different NELCONV
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
Physical description
LQFP44 package
Figure 9.1:
LQFP44 package, size
PLL-44L package
Figure 9.2:
PLL-44L package,
D0202-60
Data Sheet XE88LC01 Data Acquisition Microcontroller
form
Figure 9.3:
XE88LC01 die:
9.3.1 Bonding pads location
Coordinates start with point near bottom left border (with respect above picture). horizontal, vertical. size
Symbol
PA(4) PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) TEST AC_R(3)
52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 398.5 533.5 668.5 798.5 933.5 1063.5 1198.5 1328.5 1463.5 1934.1 2394.1 2854.1
4075.5 3795.5 3515.5 3235.5 2955.5 2675.5 2395.5 2115.5 1835.5 1555.5 1275.5 995.5 715.5 435.5 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6
Symbol
AC_R(2) AC_A(7) AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) Vbat Vreg RESET Vmult OscIn OscOut PA(0) PA(1) PA(2) PA(3)
3314.1 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3597.6 3332.6 3067.6 2802.6 2537.0 2007.6 1742.6 1477.6 1212.6 947.6 682.6 417.6
47.6 522.4 807.4 1092.4 1377.4 1662.4 1947.4 2232.4 2517.4 2802.4 3087.4 3372.4 3657.4 3942.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4
Table 9.1:
Bonding pads location. connect pads named Connect substrate Vss.
D0202-60

XE88LC01 Sensing Machine Data Acquisition Ultra Low-Power Microco

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