3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors 1999-

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3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors 1999-

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XRD9814/XRD9816
3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors
1999-1
FEATURES 16-Bit Converter (XRD9816) Missing Codes Triple-Channel, MSPS Color Scan Mode Single-Channel, MSPS Monochrome Scan Mode Triple Correlated Double Sampler Triple 10-Bit Programmable Gain Amplifier Triple 8-Bit Offset Compensation Fully Differential Single-Ended Inputs Mode Inverting Non-Inverting Mode Internal Voltage Reference Serial Control: Data Separate Pins 14-Bit 8-Bit (Nibble) Parallel Data Output (XRD9814) 16-Bit 8-Bit (Nibble) Parallel Data Output (XRD9816) Operation Compatibility Power CMOS: 500mW APPLICATIONS 48-Bit Color Scanners (XRD9816) 42-Bit Color Scanners (XRD9814) Color Imagers Gray Scale Scanners Film Scanners
GENERAL DESCRIPTION XRD9814/9816 fully integrated, high-performance analog signal processor/digitizer specifically designed 3-channel linear Charge Coupled Device (CCD) Contact Image Sensitive (CIS) imaging applications. Each channel XRD9814/9816 includes Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA) channel offset adjustment. After gain offset adjustment, analog inputs sequentially sampled digitized accurate 16-bit converter. analog front-end configured inverting/non-inverting input, sample-hold (S/H) mode, AC/DC coupling, making XRD9814/9816 suitable CCD, other data acquisition applications. mode operation supports both line pixel-clamp modes used achieve significant reduction system noise reset clock feed-through. mode internal DCrestore voltage clamp enabled disabled support AC-coupled inputs. Sampling mode, 10-bit gain (1024 linear steps), 8-bit channel offset (256 linear steps), input signal polarity programmable through serial interface. gain range channel offset range -300mV 300mV. Full-Scale Range (FSR) programmable
ORDERING INFORMATION
Part XRD9814ACV XRD9816ACV
Package Type 48-Lead TQFP 48-Lead TQFP
Temperature Range +70°C +70°C
Rev. P1.10
EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017 www@exar.com
XRD9814/9816
INTERNAL TIMING CONTROL
BSAMP VSAMP ADCCLK LCLMP
INSEL 10-BIT RED(+) RED(-) PROGRAMMABLE BUFFERED CONTROL CONFIGURATION REGISTERS OUTSEL SCLK LOAD
REGISTER
AGND1
8-BIT
TEST1 TEST2
REGISTER AVDD1 AVDD2 10-BIT GRN(+) GRN(-) PROGRAMMABLE BUFFERED AVDD3
REGISTER SGND VREF 1.24V AGND2 REGISTER REFIN OUTPUT PORT 14/16-BIT 10-BIT BLU(+) BLU(-) PROGRAMMABLE BUFFERED CAPP REGISTER CAPN VREF- VREF+ DB<13:0> DB<15:0>
8-BIT
14/16
8-BIT VCLAMP (Internal)
CREF DVDD
REGISTER DGND
Figure Block Diagram
Rev. P1.10
CONFIGURATION
XRD9814/9816
OUTSEL
DGND
DVDD
LOAD
SCLK
DB10
DB11
DB12
DB13
AVDD3
INSEL ADCCLK BSAMP VSAMP LCLMP AVDD1 AGND1 SGND CAPN CAPP CREF TEST2
XRD9814
GRN(+)
GRN(-)
RED(-)
BLU(+)
AGND2
RED(+)
AVDD2
BLU(-)
Note: Pins 17,20 should connected AGND2 improve noise immunity
DESCRIPTION XRD9814
Name AVDD3 AVDD2 AGND2 RED(+) Description Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Connect Connect Analog Power Supply Analog Power Supply Analog Ground (Substrate) Positive Analog Input
Rev. P1.10
TEST1
XRD9814/9816
DESCRIPTION XRD9814 (CONT'D)
Name RED(-) GRN(+) GRN(-) BLU(+) BLU(-) TEST1 TEST2 CREF CAPP CAPN SGND AGND1 AVDD1 LCLMP VSAMP BSAMP ADCCLK INSEL OUTSEL LOAD SCLK DGND DVDD DB13 DB11 DB10 Description
Negative Analog Input Connect, (Note Green Positive Analog Input Green Negative Analog Input Connect, (Note Blue Positive Analog Input Blue Negative Analog Input Connect, (Note Internal Only Internal Only Decoupling Reference Decoupling Positive Reference Decoupling Negative Reference Substrate Analog Ground (Substrate) Analog Power Supply Line Clamp Enable Video Level Sampling Clock Black Level Sampling Clock Converter Clock Input Mode Select (Note Output Mode Select (Note Data Output Enable Register Write Enable (Note Serial Data Input (Note Serial Shift Clock (Note Ground (Output Drivers Internal Decode Logic) Digital Power Supply (Output Drivers Internal Decode Logic) Data (Note Data (Note Data Output Data Output Data Output
Note INSEL=0 SCLK, SDI, LOAD pins active serial programming; INSEL=1 SCLK pins inactive, serial programming done through pins DB12 DB13 described Notes with LOAD tri-stating DB12 DB13. Note OUTSEL=0 14-bit parallel output mode select; OUTSEL=1 8-bit nibble output mode select. Note INSEL=1, DB12 becomes SCLK input during serial programming. Note INSEL=1, DB13 becomes input during serial programming. Note Pins connected AGND2 improve noise immunity.
Rev. P1.10
CONFIGURATION
DVDD DB11 DB12 DB13 DB14 DB15
XRD9814/9816
OUTSEL
DGND
LOAD
SCLK
DB10 AVDD3
INSEL ADCCLK BSAMP VSAMP LCLMP AVDD1 AGND1 SGND CAPN CAPP CREF TEST2
XRD9816
RED(-)
GRN(-)
RED(+)
GRN(+)
BLU(+)
BLU(-)
AVDD2
Note: Pins 17,20 should connected AGND2 improve noise immunity
Name DB10 AVDD3 AVDD2 AGND2 RED(+)
Description Data Output Data Output Bit9 Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Analog Power Supply Analog Power Supply Analog Ground (Substrate) Positive Analog Input
Rev. P1.10
AGND2
TEST1
XRD9814/9816
Configuration XRD9816
Name RED(-) GRN(+) GRN(-) BLU(+) BLU(-) TEST1 TEST2 CREF CAPP CAPN SGND AGND1 AVDD1 LCLMP VSAMP BSAMP ADCCLK INSEL OUTSEL LOAD SCLK DGND DVDD DB15 DB13 DB14 DB12 DB11 Description
Negative Analog Input Connect, (Note Green Positive Analog Input Green Negative Analog Input Connect, (Note Blue Positive Analog Input Blue Negative Analog Input Connect, (Note Internal Only Internal Only Decoupling Reference Decoupling Positive Reference Decoupling Negative Reference Substrate Analog Ground (Substrate) Analog Power Supply Line Clamp Enable Video Level Sampling Clock Black Level Sampling Clock Converter Clock Input Mode Select (Note Output Mode Select (Note Data Output Enable Register Write Enable (Note Serial Data Input (Note Serial Shift Clock (Note Ground (Output Drivers Internal Decode Logic) Digital Power Supply (Output Drivers Internal Decode Logic) Data (Note Data Output Data (Note Data Output Data Output
Note INSEL=0 SCLK, SDI, LOAD pins active serial programming; INSEL=1 SCLK pins inactive, serial programming done through pins DB14 DB15 described Notes with LOAD tri-stating DB14 DB15. Note OUTSEL=0 16-bit parallel output mode select; OUTSEL=1 8-bit nibble output mode select. Note INSEL=1, DB14 becomes SCLK input during serial programming. Note INSEL=1, DB15 becomes input during serial programming. Note Pins connected AGND2 improve noise immunity.
Rev. P1.10
XRD9814/9816
ELECTRICAL CHARACTERISTICS AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25oC unless otherwise specified
Parameter CONVERTER Resolution Resolution Maximum Conversion Rate Differential Non-Linearity Integral Non-Linearity Differential Non-Linearity Integral Non-Linearity Monotonicity Monotonicity Input Referred Offset Offset Drift Input Referred Gain Error Gain Error Drift Input Voltage Range Full-Scale Range Full-Scale Range SPECIFICATIONS Input Voltage Range Input Buffer Disabled (Note Input Buffer Enabled Input Bias Current Input Buffer Disabled (Note Input Buffer Enabled Input Switch -Resistance Input Switch -Resistance Internal Voltage Clamp Input (Inverting) Input (Non-Inverting) Vclamp Vclamp PB2=0, Config PB2=1, Config Roff 1000 Gain=1, PB1=0, Config TA=70o PB1=1, Config Clamp Enabled Clamp Disabled INVSRB AVDD-1 INVSR AGND AVDD Pixel Clamp, PB1=0, Config Line Clamp, PB1=1, Config PB5=0, Config PB5=1, Config +/-0.8 +/-3.0 0.003 uV/oC BITS BITS MSPS XRD9814 Best (XRD9814) XRD9816 Best (XRD9816) XRD9814 Missing Codes XRD9816 Missing Codes XRD9814 XRD9816 Symbol Unit Conditions
Note digitizing range (A/D Full-Scale Range/PGA Gain) Note switch capacitor input.
Rev. P1.10
XRD9814/9816
ELECTRICAL CHARACTERISTICS (CONT'D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter OFFSET SPECIFICATIONS Fine Offset Adjustment Fine Offset Adjustment Fine Offset Adjustment Step Gross Offset Adjustment Gross Offset Adjustment OFRES OFGR OFGR -300 +300 2.25 -400 +200 +200 2-Bit, Settings 8-Bit, Settings Symbol Unit Conditions
Gross Offset Adjustment Step OFGRES SPECIFICATIONS Gain Range (Absolute Value) GRAN
PB2=0, PB2=1, Config
Gain Range (Absolute Value) GRAN PB2=0, PB2=1, Config Gain Resolution GRES 0.0088 10-Bit 1024 Steps SYSTEM SPECIFICATIONS (Includes CDS, A/D) Differential Non-Linearity Gain= Gain= Integral Non-Linearity Gain= Gain Input Referred Noise Gain Gain Input Referred Offset Gain= Gain IROmin IRNmin IRNmax INLmin INLmax DNLmax
Rev. P1.10
XRD9814/9816
ELECTRICAL CHARACTERISTICS (CONT'D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter TIMING SPECIFICATIONS 3-Channel Conversion Period 1-Channel Conversion Period BSAMP Pulse Width BSAMP falling edge VSAMP falling edge. VSAMP falling edge BSAMP falling edge. VSAMP falling edge delay from rising ADCCLK. (All modes except Channel S/H). VSAMP falling edge delay from rising ADCCLK Channel S/H) VSAMP Pulse Width VSAMP TIMING OPTION VSAMP rising edge delay from falling ADCCLK (Note VSAMP TIMING OPTION VSAMP rising edge delay from rising ADCCLK (Note ADCCLK Pulse Width ADCCLK Period Mode) ADCCLK Period Mode) Settling Time accurate Sampling Aperture Delay WRITE SPECIFICATIONS Data Setup Time Data Hold Time Load Setup Time Load Hold Time Load Pulse Width tlcs tlch tplw tstl tvrcr taclk tcp1 tcp3 tvrcf required tvrcf tvrcr required, Config PB0=0 tpwv tvfcr Config PB2=1, PB7=1 tvfcr tvbf tcr3 tcr1 tpwb tbvf Symbol Unit Conditions
Note VSAMP Timing Option allows additional timing flexibility allowing rising edge VSAMP occur approximately one-half ADCCLK period earlier than Option Option only available 3-Channel Operation (PB4=0, PB3=0, Configuration Register #1).
Rev. P1.10
XRD9814/9816
ELECTRICAL CHARACTERISTICS (CONT'D) AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified
Parameter Symbol Unit Conditions
DATA READBACK SPECIFICATIONS Address Access Time Output Enable Access Time taoe
DIGITAL OUTPUT SPECIFICATIONS Output Delay 3-State Data Valid Output Enable High 3-State Latency inputs DIGITAL INPUTS Input High Logic Level Input Logic Level High Level Input Current Level Input Current Input Capacitance DIGITAL OUTPUTS (DVDD=5V) Output High Voltage Output Voltage Output Capacitance DIGITAL OUTPUTS (DVDD=3.3V) Output High Voltage Output Voltage Output Capacitance POWER SUPPLY Analog Power Supply Digital Power Supply Analog Supply Current Digital Supply Current Stand-By Mode Current AVDD DVDD IDDA IDDD PDoff Digital Output CLoad=30pF, pins. COUT IL=2ma IL=-2ma COUT IL=2ma IL=-2ma DVDD DVDD DVDD=3-5V DVDD=3-5V ADCCLK
Note Start valid data depends which timing becomes effective last, taoe taa.
Rev. P1.10
XRD9814/9816
Function Configuration Configuration Gain Green Gain Blue Gain Offset Green Offset Blue Offset
PB9-PB0 Configuration Register Configuration Register 10-Bit Gain 10-Bit Gain 10-Bit Gain 2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment 2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment 2-Bit Gross Offset Adjustment: 8-Bit Fine Offset Adjustment
Table XRD9814/9816 Register Overview
Address
Assignment Single Channel Power Save Mode Digital Reset Clamp Mode VSAMP Timing
PB9-PB0 Definition Unused channels powered down save power (single channel mode only) Unused channels powered Reset Resets registers default configuration pixel line clamp clamp line clamp reference reference channel color mode single channel mode Green single channel mode Blue single channel mode Inverted negative going signals Non-inverted positive going signals buffer coupled coupled inputs with pixel clamp mode Buffer enabled Coupled inputs line clamp clamp mode Timing option (see timing diagrams details) Timing option (see timing diagrams details)
Full Scale Range Color Select
Input Signal Polarity Input Buffer Enable
Table Configuration Register Definition (Default Configuration
Rev. P1.10
XRD9814/9816
Address Assignment Used Used Used Used Used
PB9-PB0 Definition
Normal This register should zero normal operation Normal Normal Normal Normal AVDD-0.8V AVDD-1.3V AVDD-1.8V AVDD-2.3V Normal This register should zero normal operation circuits active power mode digital outputs Read back mode (A2:A1:A0 select register data) This register should zero normal operation This register should zero normal operation This register should zero normal operation This register should zero normal operation
Clamp Voltage
Used Stand-By Mode Read Back Mode
Table Configuration Register Definition (Default Configuration
Rev. P1.10
XRD9814/9816
Function Gain Green Gain Blue Gain Offset PB9-PB8 gross PB7-PB0 fine
+200mV -200mV -400mV +200mV -200mV -400mV +200mV -200mV -400mV
Green Offset PB9-PB8 gross PB7-PB0 fine
Blue Offset PB9-PB8 gross PB7-PB0 fine
Table Gain Offset Registers (Default Configuration
Rev. P1.10
XRD9814/9816
GENERAL DESCRIPTION
Clamp Mode clamp mode setting determines conditions when internal clamp enabled (see Table pixel line-clamp modes used DCrestore coupled input signals common-mode input voltage while using correlated double sampling. line mode should used DCrestore coupled inputs which utilize correlated double sampling have only control input (VSAMP). No-clamp mode should used coupled inputs. Pixel Mode (CCD with CDS) input clamp active each pixel period with pulse-width determined Black- level Sampling Input (BSAMP). position BSAMP optimized eliminate effects reset pulse. Since input capacitor recharged clamp voltage each pixel, common-mode droop errors eliminated. Line Mode (CCD with CDS) input clamp enabled only beginning line gating BSAMP with LCLMP. Gating with LCLMP maintains ability position clamp pulse (BSAMP) away from reset varying LCLMP position width. Since input capacitor clamped only beginning each line larger input capacitor required satisfy common-mode input requirements analog front-end. (See Coupling Capacitor Requirements.) input buffer should enabled this mode (PB1=1, Register #1). Line Mode (S/H with Coupling) Line mode clamp used DC-restore coupled inputs which utilize CDS. VSAMP used sample hold input signal LCLMP performs clamp function. This differs from line pixel modes which BSAMP clamp reference level VSAMP hold video input. input buffer should enabled this mode (PB1=1, Register #1).
XRD9814/9816 contains circuitry required create complete 3-channel signal processor /digitizer CCD/CIS imaging systems. Each channel includes correlated double sampler, programmable gain amplifier channel offset adjustment. input stage also configured with inverting/non-inverting, coupled signals. order maximize flexibility, specific operating mode programmable through configuration registers. addition, gain offset each channel independently programmed through separate gain offset registers. Configuration register data loaded serially through 3-pin serial interface. Specific details register writes detailed below. After signal conditioning three outputs digitized 14-bit converter. Writing Registers Data XRD9814/9816 utilizes eight 10-Bit registers store configuration, gain offset information. Register data written though 3-pin serial interface consisting (serial data input), SCLK (serial shift clock) LOAD (positive edge write enable). write consists pulling LOAD low, shifting bits address (MSB first) bits data (MSB first). Data written rising edge LOAD. timing diagram writing registers shown timing diagrams. When INSEL=0, SCLK, SDI, LOAD pins active serial programming. When INSEL=1, SCLK pins inactive, serial programming done through pins DB12 DB13 while LOAD low. Configuration Register assignment definition this register detailed Configuration Register Definition Table. primary purpose this register configure analog input blocks operation.
Rev. P1.10
No-Clamp Mode (S/H with input) Used coupled inputs. coupled inputs must externally clamped proper common-mode input voltage XRD9814/9816.
Note: Pixel clamp default clamp mode.
Clamp Mode Pixel Line Clamp Line
XRD9814/9816
Clamp Enable
BSAMP BSAMP LCLMP Disabled LCLMP
Table Clamp Enable Definition
Clamp Enable BSAMP
LCLMP
Figure Clamp Enable Logic
Full-Scale Range This sets Full-Scale Range (FSR) converter Color Select color input corresponds signal input digitized converter. (default) input sequentially cycled through red, green blue channels. green channel synchronized rising edge first ADCCLK after falling edge VSAMP. single-channel mode, multiplexer will sequence converter input will continually connected channel that selected, RED, BLU.
Signal Polarity This configures analog inputs positive negative transitioning inputs. This required provide correct signal polarity input correct input clamp level. default configuration inverting mode (CCD input). Input Buffer Enable This enables input buffer amplifier required only coupled inputs operating line line clamp modes. Since this input buffer reduces input voltage range recommended under pixel-mode operation. input buffer disabled default configuration.
Rev. P1.10
XRD9814/9816
VSAMP Timing
Reading Register Data When INSEL LOAD must remain high during readback mode. order exit readback mode perform write configuration register PB0=0. When INSEL LOAD must tri-state output when addressing registers read-back mode. DB12 becomes SCLK DB13 becomes SDI. After read-back mode initiated, XRD9814/9816 designed automatically detect when registers being addressed read-back mode. XRD9814/9816 also detects when part being programmed read-back mode that there conflicts. (OUTSEL read-back mode output bypassed internal register data output most significant bits data output bus. Readback mode enabled setting Configruation Register equal LOAD must remain high read-back mode. order read specific register shift 3-bits address data (MSB first), followed dummy data bits. Register data will valid after 13th data shifted order exit read-back mode perform write configuration register PB0=0 write this register pulling LOAD high. (OUTSEL nibble mode, output limited 8-bits. Therefore, read-back mode, MSBs valid when ADCCLK high, LSBs valid when ADCCLK low. Configuring read-back mode done same manner OUTSEL order exit readback mode perform write configuration register PB0=0 write this register pulling LOAD high. Important: entire byte register written when LOAD pulled high will equal data loaded immediately preceeding positive edge LOAD. Gain Settings gain each color input individually programmable from 1024 linear steps.
This allows user select VSAMP timing controls. Timing Option allows rising edge VSAMP occur approximately one-half ADCCLK earlier than Option This does affect internal timing provided only allow additional flexibility external timing control. Timing Option available only 3-channel mode operation (See timing diagram). Configuration Register assignment definition this register detailed Configuration Register Definition Table. diagnostic read-back mode allows gain, offset configuration data output MSBs digital output depending selection OUTSEL (see Reading Register Data details). Additional bits used enable low-power stand-by state manufacturing test mode. Digital Reset Setting this resets registers zeros. Test Mode This reserved testing must writes Configuration Register Stand-By Mode Setting this forces circuit into low-power standby mode. Configuration, offset gain registers remain unchanged stand-by mode. Pull High DB<13:0> high impedance during stand-by mode. Read Back Mode This special diagnostic mode which debugging system designs. Setting this allows configuration, gain offset register contents output data output (explained below).
Rev. P1.10
XRD9814/9816
Code Gain 1024
where Code represents binary contents 10bit gain setting register. Channel Offset Adjustment offset correction each channel programmable from -300mV +300mV 8-Bit signmagnitude DAC.
Since process uses coupled inputs coupling capacitor must charged commonmode range analog front-end. This accomplished clamping coupling capacitor internal clamp voltage when reference level. This clamp occur during each pixel (Pixel Clamp), beginning each line (CDS Line Clamp). Line Clamp mode used input buffer (configuration register PB1) must enabled eliminate effects input bias current. Pixel mode selected input buffer required recommended. 3-Channel Mode This mode allows simultaneous red, green blue inputs Black-level sampling occurs each pixel equal width BSAMP sampling input. black level held falling edge BSAMP will immediately begin track signal input until falling edge VSAMP. VSAMP timing modes supported allow additional flexibility VSAMP pulse width (see timing diagrams). video sampling phase difference between reference video levels inverted, amplified offset depending contents gain offset registers. channels then sequentially converted high speed converter. converter data appears data output after ADCCLK cycles. Green channel synchronized rising edge first ADCCLK after falling edge VSAMP. power default mode sampling input (Pixel Clamp, Inverting input, input buffer). 1-Channel Mode 1-Channel mode allows high-speed acquisition processing single channel. timing, clamp buffer configurations similar 3channel mode described previously. select single channel input color bits configuration register must appropriate value. input will begin track selected color input next positive edge ADCCLK. configuration toggled from single color 3-channel mode scanning will occur until circuit resynchronized falling edge VSAMP.
Channel Offset
PB7=1 equals PB7=0 equals
Code 300mV
Code (PB6:PB0) 8-bit offset register. Theory Operation (Correlated Double Sampling) Correlated double sampling technique used level shift acquire output signals whose information equal difference between consecutive reference (black) signal (video) samples. process consists three steps: Sampling holding reference black level. Sampling video level. Subtracting samples extract video information. Once video information been extracted processed further through amplification and/or offset adjustment. Since system noise also stored subtracted during process, signals with bandwidths less than half sampling frequency will substantially attenuated. order reject higher frequency power supply noise which attenuated near sampling frequency XRD9814/9816 utilizes fully differential input structure.
Rev. P1.10
XRD9814/9816
3-Channel CIS/Sample Hold Mode
Power Supplies Digital XRD9814/9816 utilizes separate analog digital power supplies. digital pins 3V/5V compatible allow easy interfacing external digital ASICs. single supply systems analog digital supply pins separately connected bypassed reduce noise coupling from digital analog circuits. Coupling Capacitor Requirements size external coupling capacitors depends number items including clamp mode, pixel rate, channel gain, black-level variation system accuracy requirements. major limitation each clamp mode shown below:
Mode Pixel Clamp (Buffer Disabled) Black level pixel-pixel variation Initial charging Line Clamp (Buffer Enabled) Initial charging Capacitor droop (common-mode range) Capacitor droop range) (accuracy error) initial Charging Mode Applicable
XRD9814/9816 also supports operation Contact Image Sensor (CIS) applications. green channel synchronized rising edge first ADCCLK after falling edge VSAMP. DC-coupled inputs reference clamp input buffer should disabled input polarity should (non-inverting). this mode operation BSAMP input connected DGND input sampling occurs falling edge VSAMP. When using coupled inputs coupling capacitor must clamped required common-mode input voltage when signal source output reference level. This accomplished enabling Line clamp mode configuration register clamping input capacitor internal clamp voltage beginning each line LCLMP input. required width LCLMP signal dependent value coupling capacitor, XRD9814/9816 clamp resistance, source output resistance desired accuracy. This explained further Coupling Capacitor Requirements. coupling used input buffer (configuration register must enabled eliminate input-bias current errors inherent sampling process. input buffer required recommended coupled applications. 1-Channel CIS/ Sample Hold Mode 1-channel mode allows high-speed acquisition processing single channel. timing, clamp buffer configurations similar 3-channel mode with exception that VSAMP timing option supported. select single channel input color bits configuration register must appropriate value. input will begin track selected color input next positive edge ADCCLK. configuration toggled from single color 3-channel mode, scanning will occur until circuit resynchronized.
Table Coupling Capacitor Limitation
Rev. P1.10
Maximum Capacitance (CDS Pixel Mode)
XRD9814/9816
Limitation
Since black level clamped during each pixel period input bias current contributes insignificant amount droop during pixel period. However, pixel-pixel variations black level appear errors worst case gain -10, 10-bit accuracy error corresponds 200uV input-referred. Assuming pixel-pixel variation black level maximum coupling capacitor determined function clamping period internal clamp resistance.
Assuming that Vr=5V, Vc=4V, V=200uV, Rc=100, Rs=500, tpwb=100ns N=10 maximum allowable input capacitor equal 196pF. this case input capacitance limited pixel-pixel changes black level (first calculation). Minimum Capacitance (CDS Pixel Mode) minimum coupling capacitance limited parasitic effects including board capacitance. minimum value 68pF recommended. Maximum Capacitance (CDS Line Mode) Since coupling capacitor charged only beginning each line clamped each pixel, pixel-pixel variation black level effect capacitor size. maximum size will limited number clamp pulses, clamp pulse-width number lines allowed charge given accuracy.
tpwb
where tpwb=clamp pulse width (BSAMP) Rc=Clamp resistance Rs=Signal source-resistance
typical values tpwb=100ns, Rc=100, Rs=500, CMAX 72pF.
tpwb
clamp pulse width (BSAMP) number pixels allowed settle clamp resistance signal source-resistance black level XRD9814/9816 clamp voltage error voltage
Limitation
maximum input capacitance also limited time allowed charge input capacitor difference between black level clamp levels. capacitor value related number clamp pulses allowed before capacitor voltage settles within desired accuracy.
where tpwb
tpwb
Assuming that Vr=5V, Vc=4V, Ve=200uV, Rc=100W, Rs=500W, tpwb=100ns N=10 maximum allowable input capacitor equal 196pF. this case input capacitance limited pixel-pixel changes black level (first calculation). Minimum Capacitance (CDS Pixel Mode) minimum coupling capacitance limited parasitic effects including board capacitance. minimum value 68pF recommended.
where tpwb
clamp pulse width (BSAMP) number pixels allowed settle clamp resistance signal source-resistance black level XRD9814/9816 clamp voltage error voltage
Rev. P1.10
XRD9814/9816
tpwb
10nA 3000
7.5pF
where tpwb= clamp pulse width (BSAMP) number clamp pulses beginning each line. number lines clamp desired accuracy. clamp resistance Signal source-resistance black level XRD9814/9816 clamp voltage error voltage Assuming that Vr=5V, Vc=4V, Ve=200uV, Rc=100W, Rs=500W, tpwb=100ns N=10, maximum allowable input capacitor equal 392pF. desired settle within line (L=1) given capacitor value, number clamp pulses clamp pulse-width must increased using above equation. Minimum Capacitance (CDS Line Mode) general minimum value coupling capacitance limited amount droop which occur before input voltage range input amplifier exceeded. input capacitor droop related input bias current
Note: These absolute minimum capacitor requirements. stated pixel-mode, minimum value 68pF recommended.
Minimum Capacitance (S/H Line Mode) Unlike Line Pixel modes voltage droop across line appears absolute error dominant factor determining minimum coupling capacitor size.
Ibias
where Ibias=input bias current n=number pixels line Assuming n=3000, T=500nS, I=10nA Ve=200uV minimum required capacitor 75nF. Maximum Capacitance (S/H Line Mode) maximum capacitance determined amount time allowed charge coupling capacitor. order minimize charging time maximum capacitor minimum value previously calculated. this case time required charge capacitor
Vdroop
Ibias
where Ibias input bias current number pixels line pixel period minimum input voltage allowed equal input voltage XRD9814/9816, maximum allowable droop will equal clamp level minus difference between black video levels. example Vc=4V, video output relative black level maximum allowable droop equal Using previous equation assuming T=500ns, n=3000
where Cmin
clamp pulse width SYNCH clamp resistance signal source resistance input reference level XRD9814/9816 clamp voltage error voltage coupling capacitor
Assuming that Vr=.5 Vc=0V, V=200uV, Rc=100, Rs=500 C=75nF, minimum clamp period equal 352uS.
Rev. P1.10
XRD9814/9816
CCDIN tcp3 taclk taclk
ADCCLK tvfcr BSAMP tvrcr(2) tvrcf(1) tpwb
VSAMP tbvf tpwv tstl tcr3 Clamp (Internal XRD9814/XRD9816) tvbf
Figure Channel Mode Pixel Clamp
Configuration Register
Pixel Clamp (PB7=0, PB6=0) (PB4=0, PB3=0) Inverted Polarity (PB2=0) Input Buffer Disabled (PB1=0)
Rev. P1.10
XRD9814/9816
CCDIN
LCLMP tcp3 taclk taclk
ADCCLK tvfcr BSAMP tvrcr(2) tpwb VSAMP tbvf tpwv tstl tcr3 Clamp (Internal XRD9814/XRD9816) tvrcf(1) tvbf
Notes: VSAMP Timing Option uses tvrcf (tvrcr required) VSAMP Timing Option uses tvrcr (tvrcf required)
Figure 3-Channel Mode Line Clamp
Configuration Register Line (PB7=0, PB6=1) (PB4=0, PB3=0) Inverted Polarity (PB2=0) Input Buffer Enabled (PB1=1)
Rev. P1.10
XRD9814/9816
CCDIN taclk
tcp1 taclk
ADCCLK
tstl BSAMP
tvfcr
tpwb
VSAMP tcr1 tpwv tvbf tbvf
Clamp (Internal XRD9814/XRD9816)
Figure 1-Channel Mode Pixel Clamp
Configuration Register Pixel Clamp (PB7=0, PB6=0) Single Channel (PB4, PB3-RED Inverted Polarity (PB2=0) Input Buffer Disabled (PB1=0)
Rev. P1.10
XRD9814/9816
CCDIN
LCLMP taclk
tcp1 taclk
ADCCLK
tstl BSAMP
tvfcr
tpwb
VSAMP tcr1 tpwv tvbf tbvf
Clamp (Internal XRD9814/XRD9816)
Notes: Only VSAMP timing option supported 1-channel mode
Figure 1-Channel Mode Line Clamp
Configuration Register Line Clamp (PB7=0, PB6=1) Single Channel (PB4, PB3-RED Inverted Polarity (PB2=0) Input Buffer Enabled (PB1=1)
Rev. P1.10
XRD9814/9816
LCLMP tcp3 taclk taclk
tvfcr
ADCCLK tvrcf(1) VSAMP tstl tcr3 tpwv tvrcr(2)
Clamp (Internal XRD9814/XRD9816)
Figure 3-Channel Mode Line Clamp Coupled)
Configuration Register Line Clamp (PB7=1, PB6=1) (PB4=0, PB3=0) Non-Inverted Polarity (PB2=1) Input Buffer Enabled (PB1=1)
Rev. P1.10
XRD9814/9816
tcp3 taclk taclk tvfcr
ADCCLK tvrcf(1) VSAMP tstl tcr3 tpwv tvrcr(2)
Clamp (Internal XRD9814/XRD9816)
Notes: VSAMP Timing option uses tvrcf (tvrcr required) VSAMP Timing option uses tvrcr (tvrcf required)
Figure 3-Channel Mode Clamp Coupled)
Configuration Register Clamp (PB7=1, PB6=0) (PB4=0, PB3=0) Non-Inverted Polarity (PB2=1) Input Buffer Disabled (PB1=0)
Rev. P1.10
XRD9814/9816
LCLMP tcp1 taclk taclk
ADCCLK tstl VSAMP tvrcf(1) tpwv tcr1 tvfcr
Clamp (Internal XRD9814/XRD9816)
Figure 1-Channel Mode Line Clamp Coupled)
Configuration Register Line Clamp (PB7=1, PB6=1) Single Channel (PB4, PB3-RED Non-Inverted Polarity (PB2=1) Input Buffer Enabled (PB1=1)
Rev. P1.10
XRD9814/9816
tcp1 taclk taclk
ADCCLK tstl VSAMP tvrcf(1) tpwv tcr1 tvfcr
Clamp (Internal XRD9814/XRD9816)
Notes: Only VSAMP timing option supported 1-channel mode
Figure 1-Channel Mode Clamp Coupled)
Configuration Register Clamp (PB7=1, PB6=0) Single Channel (PB4, PB3-RED Non-Inverted Polarity (PB2=1) Input Buffer Disabled (PB1=0)
Rev. P1.10
XRD9814/9816
Pixel CCDOUT (Parallel RGB)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
ADCCLK Latency ADCCLK
BSAMP Samples Green VSAMP Pixel (n+1) Pixel Pixel (n+1) Pixel (n+1)
Pixel
Figure 3-Channel Pixel Clamp Synchronization Latency Timing
Pixel CCDOUT (Green Input)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5) Pixel (n+6) Pixel (n+7)
Pixel (n+8)
ADCCLK Latency
ADCCLK
BSAMP
VSAMP
Pixel (n-3)
Pixel (n-2)
Pixel (n-1)
Pixel Pixel
Figure 1-Channel Pixel Clamp Synchronization Latency Timing
Rev. P1.10
XRD9814/9816
Pixel CISOUT (Parallel RGB) Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
ADCCLK Latency ADCCLK Samples Green VSAMP Pixel (n+1) Pixel Pixel (n+1) Pixel (n+1)
Pixel
Figure 3-Channel Synchronization Latency Timing
Pixel CISOUT (Green Input)
Pixel (n+1)
Pixel (n+2)
Pixel (n+3)
Pixel (n+4)
Pixel (n+5) Pixel (n+6) Pixel (n+7)
Pixel (n+8)
ADCCLK Latency
ADCCLK
VSAMP
Pixel (n-3)
Pixel (n-2)
Pixel (n-1)
Pixel Pixel
Figure 1-Channel Synchronization Latency Timing
Rev. P1.10
XRD9814/9816
SCLK (Pin (Pin tlcs tlch LOAD (Pin tplw
Figure Write Timing (INSEL
SCLK/ DB12/DB14 (Pin SDI/ DB13/DB15 (Pin tlcs tlch LOAD (Pin tplw tlch
Figure Write Timing (INSEL
Rev. P1.10
XRD9814/9816
ADCCLK
DB13:0/ DB15:0 TRI-STATE DB13/15:0 (N-6)
TRI-STATE
DB13/15:DB0 (N-7)
LOAD
LOAD
Figure Digital Output Timing (OUTSEL
ADCCLK DB13:0/ DB15:0 TRI-STATE (LSB 6/8-BITS) (MSB 8-BITS)
(LSB 6/8-BITS) (MSB 8-BITS) TRI-STATE
LOAD
LOAD
Figure Digital Output Timing (OUTSEL
Rev. P1.10
XRD9814/9816
tstl VSAMP
ADCCLK ADCOUT Valid Data Dummy ADCCLK Latency
Figure XRD9814/XRD9816 Pipeline Latency
ADCCLK/SYNCHRONIZATION EVENTS
Necessary Sampling Events Occur Beginning Synchronization Samples Green (N-1) Converts Unkown Dummy Value Samples Blue (N-1) Converts Green (N-1) Samples Converts Blue (N-1) Synchronization Samples Green Converts Samples Blue Converts Green Samples (N+1) Converts Blue Synchronization Samples Green (N+1) Converts (N+1) Dummy Pixel (N-1) Valid Generated From ADCCLK Pixel (N-1) Valid Generated From ADCCLK Pixel (N-1) Valid Generated From ADCCLK Pixel Valid Generated From ADCCLK Pixel Valid Generated From ADCCLK Pixel Valid Generated From ADCCLK
Note: Green Channel Synchronized First Rising Edge ADCCLK After Falling Edge VSAMP
Rev. P1.10
XRD9814/9816
Application Notes
Avdd Dvdd c1=c3=0.1uF c2=c4=0.01uF
Data 14/16 Databus (ASIC)
Connect Connect
Red(+) Red(-) Grn(+) Grn(-)
Serial Load Control Signals
XRD9814/XRD9816
Connect Connect
Blu(+) Blu(-)
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure Single Channel DC-Coupled Mode
Avdd
2.2uF
Dvdd c1=c3=0.1uF c2=c4=0.01uF
100pF
Connect Connect
Red(+) Red(-) Grn(+) Grn(-)
Data 14/16- Databus (ASIC)
Serial Load Control Signals
XRD9814/XRD9816
100pF Connect Connect Blu(+) Blu(-)
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure Single Channel AC-Coupled Mode
Rev. P1.10
2.2uF
XRD9814/9816
Avdd
Dvdd c1=c3=0.1uF c2=c4=0.01uF
Red(+) Red(-) Grn(+) Grn(-)
Data 14/16-8 Databus (ASIC) Serial Load Control Signals
XRD9814/XRD9816
Blu(+) Blu(-)
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure Triple Channel DC-Coupled Mode
Avdd
2.2uF
Dvdd c1=c3=0.1uF c2=c4=0.01uF
100pF 100pF 100pF 100pF 100pF 100pF Red(+) Red(-) Grn(+) Grn(-)
Data 14/16-8 Databus (ASIC) Serial Load Control Signals
XRD9814/XRD9816
Blu(+) Blu(-)
0.1uF 2.2uF
0.1uF
2.2uF
0.1uF
2.2uF
0.1uF
Figure Triple Channel AC-Coupled Mode
Rev. P1.10
2.2uF
XRD9814/9816
INSEL/OUTSEL Data Output Format
There control signals setting output data format serial load control. INSEL used select mode programming serial port. external pins sdi, sclk load, INSEL must (Figure Figure 21). When INSEL high, DB13/sdi DB12/sclk become inputs through bi-directional output load internal control registers (Figure Figure 22). load still used latch data. This helps reduce count requirements ASIC that drives XRD9814/9816.
OUTSEL used select output data format XRD9814/9816. XRD9814/9816 supports 14/16bit parallel 8-bit nibble output modes. When OUTSEL low, output standard 14/16-bit parallel (Figure Figure 21). 8-bit nibble output mode, OUTSEL must high. either 14/16-bit 8-bit nibble applications, output tri-stated when using bi-directional serial load control option (Figure Figure 22).
DB13/DB15 DB12/DB14
14/16-Bit Parallel
Digital ASIC
XRD9814/ XRD9816
sclk load Insel Outsel External Serial Load
Insel=0, Outsel=0
Figure 14/16-Bit Output (OUTSEL=0), External Serial Load (INSEL=0)
14/16-Bit Parallel Bi-Directional Serial Load
DB13/DB15/sdi DB12/DB14/sclk
Digital ASIC
XRD9814 XRD9816
sclk load Insel Outsel Connect Connect Insel=1, Outsel=0
Figure 14/16-Bit Output (OUTSEL=0), Bi-Directional Serial Load (INSEL=1)
Rev. P1.10
XRD9814/9816
DB13/DB15 DB12/DB14
8-Bit Nibble Digital ASIC
XRD9814
XRD9816
sclk load Insel Outsel
External Serial Load
Insel=0, Outsel=1
Figure 8-Bit Nibble Output (OUTSEL=1), External Serial Load (INSEL=0)
DB13/DB15/sdi DB12/DB14/sclk
8-Bit Nibble Bi-Directional Serial Load
Digital ASIC
XRD9814
XRD9816
sclk load Insel Outsel Connect Connect Insel=1, Outsel=1
Figure 8-Bit Nibble Output (OUTSEL=1), Bi-Directional Serial Load (INSEL=1)
Rev. P1.10
XRD9814/9816
Rev. P1.10
Preliminary Notes
XRD9814/9816
Rev. P1.10
XRD9814/9816
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed accuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances.
Copyright 1999 EXAR Corporation
Datasheet 1999 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
Rev. P1.10

3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors 1999-

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