SM2603 2604 Enhanced SDRAM (ESDRAM) devices JEDEC superset standard SD

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SM2603 2604 Enhanced SDRAM (ESDRAM) devices JEDEC superset standard SD

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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM Description
SM2603 2604 Enhanced SDRAM (ESDRAM) devices JEDEC superset standard SDRAM. While pin, function, timing compatible with standard SDRAM, they combine improved speed innovative architecture optimize system price/performance high performance main memory, video graphics, embedded systems. four bank architecture combines 22.5 DRAM arrays with 10.5 SRAM caches. Three significant functional features include early auto-precharge, hidden delay (tRCD), optional Write Transfer mode. ESDRAM capable maintaining four open read pages four open write pages simultaneously Write Transfer mode.
High Performance Superset SDRAM 100% Compatible with SDRAM 100% Function Timing Compatible with JEDEC Standard SDRAM Integrated Kbit SRAM Cache latency Operation Synchronous Operation 2:2:2 1:1:1 Programmable Output Impedance (EMRS) Programmable Burst Length full page) Programmable Latency Hidden Auto-Refresh Without Closing Read Pages Power Suspend, Self Refresh, Power Down Modes Supported Programmable Write Policy Programmable Read Latency (EMRS) Refresh Single 3.3V Power Supply Flexible VDDQ Supports LVTTL 2.5V 54-pin TSOP-II (0.8mm pitch)
Block Diagram (4Mx16 shown)
ADDRESS BUFFERS
DECODER
BANK rows bits
BANK rows bits
BANK rows bits
BANK rows bits
A(11:0)
DATA LATCHES
DATA LATCHES
DATA LATCHES
SRAM CACHE COLUMN DECODER
SRAM CACHE COLUMN DECODER
SRAM CACHE COLUMN DECODER
SRAM CACHE COLUMN DECODER
RAS# CAS# UDQM LDQM
Data Buffers COMMAND DECODER TIMING GENERATOR
DQ(15:0)
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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DATA LATCHES
SENSE AMPLIFIERS
SENSE AMPLIFIERS
SENSE AMPLIFIERS
SENSE AMPLIFIERS
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Assignments (Top View)
8Mx8 4Mx16
VDDQ VSSQ VDDQ VSSQ CAS# RAS# A10/AP
VDDQ VSSQ VDDQ VSSQ LDQM CAS# RAS# A10/AP
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ UDQM
VSSQ VDDQ VSSQ VDDQ
54-pin TSOP-II mils pitch
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Preliminary Datasheet Descriptions Symbol Type Input Input Function
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Clocks: ESDRAM input signals sampled rising edge CLK. Clock Enable: activates (high) deactivates (low) internally. Deactivating clock provides means entering Power-Down Self-Refresh modes (all banks idle), Clock Suspend mode. synchronous until device enters Power-Down Self-Refresh modes where asynchronous until mode exited. Chip Select: enables (low) disables (high) command decoder. When command decoder disabled, commands ignored previous operations continue. Command Inputs: Sampled rising edge CLK, these inputs define command execute. Bank Addresses: These inputs define which banks given command applied. They also used define EMRS commands. Address Inputs: A0-A11 define address during Bank Activate command. 8Mx8 device, A0-A8 define column address during Read Write commands. 4Mx16 device, A0-A7 defines column address during Read Write commands. A10/AP invokes Auto-Precharge operation. During manual Precharge commands, A10/AP specifies single bank precharge while A10/AP high precharges banks. address inputs also used program Mode registers. Data I/O: Data inputs outputs. Write cycles, input data applied these pins must held relative rising edge clock. Read cycles, device drives output data these pins after latency satisfied. Data Mask Input: inputs mask write data (zero latency) synchronous output enable (2-cycle latency) read data. optional mode provided through settings Extended Mode register, output enable latency when latency one. Power (+3.3 ground input buffers core logic. Isolated power ground output buffers. VDDQ connected either 3.3V 2.5V power. connect open pin.
Input
RAS#, CAS#, BA1, A0-A11
Input Input Input
DQ0-DQ15
Input/ Output
LDQM, UDQM
Input
VDD, VDDQ, VSSQ
Supply Supply
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
General Description
64Mbit ESDRAM high-speed SDRAM configured four banks DRAM with SRAM cache bank synchronous interface. inputs registered outputs driven rising edge clock. Within each bank, devices organized 4096 rows 4096 bits each. Within each row, 8Mx8 device column address locations 4Mx16 device column locations. Read write accesses accomplished opening selecting column address location transaction. Bank Activate command instructs device open four banks, though four banks active simultaneously. subsequent Read Write command instructs device read data from write data specified column address location. device programmed burst data out. Burst accesses start with given column address location continue until burst length satisfied. Throughout burst, device internally generates column addresses according burst type burst length programmed into Mode register. early auto-precharge feature allows device self-time precharge clock cycle after Read command issued, clock cycle following last data word write burst. precharge operation must occur before another opened within same bank.
Cache Operation
ESDRAM architecture combines four banks fast 22.5 DRAM with 10.5 SRAM cache bank improve memory latency. Sustained high-speed bandwidth achieved pipelining operations internally. random read access, DRAM bank activated data latched into sense amplifiers sense amplifiers hold data considered open. Read command causes entire latch into SRAM cache, data specified column address location driven 10.5 Since data latched into SRAM cache, DRAM sense amplifiers decoupled from data. DRAM precharge time hidden behind burst read from cache. This minimizes subsequent page miss latency. Since both precharge delays hidden, device supports industry leading latency clock frequencies MHz, latency MHz. MHz, cycle next random access location same bank hidden. This dramatically increases sustained bandwidth times over standard SDRAM. interleaved burst read accesses, entire precharge time hidden output data driven without wait states.
Write Transfer Mode
ESDRAM architecture offers system designer different cache loading policies during write cycles. cache loading policy programmed Mode Register command. Write Transfer (normal) mode SRAM cache always loaded with write data. This ensures coherency between cache DRAM array, allows read-modify-write cycles simplified memory control logic. Write Transfer mode, cache loaded during writes DRAM array. This allows continued access previously cached read data without incurring page miss penalty (closing write re-opening read row). ESDRAM maintain four open read pages four open write pages simultaneously Write Transfer mode. This subject also covered section Mode Register command. Note: write occurs (the write page already cache) ESDRAM automatically updates cache when data written DRAM array, regardless Write Transfer mode setting. This maintains coherency.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice. Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Performance Advantages
ESDRAM delivers improved system performance reducing latency allowing concurrent operations same bank DRAM array.
Reduced Latency
ESDRAM core consists high-speed (tRAC 22.5ns) DRAM arrays. These fast arrays reduce precharge time (tRP) bank cycle time (tRC). Since reads always access SRAM cache, this allows ESDRAM perform random column accesses SRAM speeds.
Concurrent Operations Pipelining
Using SRAM cache, ESDRAM also perform concurrent operations same bank. This ability provides significant increase performance, some cases effectively doubling memory bandwidth. following discussion which concurrent operations allowed system performance maximized. When Bank Activate command given, selected sense amplifiers latch data. Then Read command transfers entire into SRAM cache. Since reads take data from cache, longer necessary hold DRAM bank open. using Read with Auto-Precharge command DRAM array precharged next clock cycle. Once DRAM bank precharged system issue Auto-Refresh command another Bank Activate command during read accesses from cache. ability perform bank activate during read gives system option pipelined memory accesses same bank. Using pipelining, precharge time (tRP) delay (tRCD) page miss hidden during burst read. case random reads, pipelining double memory bandwidth. Note that write bursts cannot pipelined because DRAM bank must held open, therefore cannot precharged, during Write command execution.
Compatibility
making ESDRAM exactly compatible with JEDEC standard SDRAM, possible memory controller support both types memory with simple mode selection. Both SDRAM ESDRAM identical memory footprints planar, identical DIMM module wiring. Systems designed support both memory types provide distinct price/performance points simple field upgrade with ESDRAM.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Commands
Command Summary Table
Function
Previous Cycle Current Cycle RAS# CAS# BA1, A10/ A11, A8-A0*
Mode Register Extended Mode Register Operation (NOP) Bank Activate Write with Auto-Precharge Write Read with Auto-Precharge Read Burst Termination Single Bank Precharge Precharge Banks Auto-Refresh (CBR) Self Refresh Entry Self Refresh Exit Device Deselect (DESEL) Clock Suspend Mode Entry Clock Suspend Mode Exit Power Down Mode Entry Power Down Mode Exit Data Write/Output Enable Data Mask/ Output Disable
Code (BA1=0, BA0=0) Code (BA1=1, BA0=0) Column Column Column Column Address
DESEL
DESEL DESEL
4Mx16 does column addresses.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Mode Register Command
Power Initialization
default power state Mode register undefined. following power initialization sequence guarantees device preconditioned each users specific need. During power VDDQ pins must achieve working voltage later than input signal voltages. power voltage must exceed 0.3V input pins power supplies. After power initial pause 100µs least Deselect command required followed Precharge Banks command. avoid data contention bus, recommended that pin(s) held high during initial pause period. Once four banks precharged, minimum Auto Refresh (CBR) commands must occur before Mode register programmed. Following Mode Register command, minimum delay clock cycles required before first Bank Activate command. Failure follow these steps lead unpredictable startups.
Programming Mode Register
application flexibility, latency, burst length, burst type, write transfer policy user defined variables that must programmed into Mode register. This done with single Mode Register command. Re-executing this command allows changes these variables, four variables must specified each time. Before Mode Register command issued, four banks must precharged must high least clock cycle. After initial power this command must issued before Read Write commands. Mode Register command activated when RAS#, CAS#, CS#, rising edge clock. address input data during this cycle defines parameters shown following Mode Register diagram. After this command, delay clock cycles required before issuing command. Note: Issuing Mode Register command always sets Extended Mode register default settings.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Mode Register (Address Input Mode Set)
Write Policy
Latency
Burst Length
Mode
Write Transfer Write Transfer
Burst type Sequential Interleaved
Burst Length Latency Reserved Reserved Reserved Reserved Reserved Sequential Reserved Reserved Reserved Full Page Interleaved Reserved Reserved Reserved Reserved
Latency
latency refers delay from when Read command registered rising clock edge when data becomes available outputs. latency expressed clock cycles, have values one, two, three cycles. table showing these relationships appears Electrical Characteristics section.
Write Policy
There modes that define ESDRAM cache used during write cycles. Write Transfer mode, cache always loaded with write data during write cycles. This assures coherency between cache DRAM array, allowing read-modify-write cycles simplified memory control logic. Write Transfer mode, cache loaded with write data during Write command execution. Data written DRAM array, prior cache contents maintained. Every time memory controller issues Bank Activate command, ESDRAM loads internal address register later comparison against address during next Bank Activate command. on-chip page hit/miss comparator determines that write same cache, write updates cache along with DRAM array maintain coherency. Write Transfer mode allows immediate return prior cached read page without incurring page miss penalty. cache read follows write cycle, write precharge time hidden.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice. Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Burst Length Burst Type
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Bursting provides constant flow data memory locations (writes), from memory locations (reads). Burst length burst type programmable through address bits A0-A3 during Mode Register command. Burst length defines number bits transferred after Read Write command. This value programmable one, two, four, eight, full page (actual page length dependent device organization: x16). Full page bursting only available with sequential type bursts. burst does automatically terminate full page mode, continues even after page length satisfied. Burst type defines order which data transferred. Both sequential interleaved bursting supported. details table below.
Burst Length Type
Burst Length Starting Address Full Page (Note) Sequential Addressing (decimal) Cn+1, Cn+2, Interleaved Addressing (decimal) Supported
Note: Page length function organization column addressing. organization (CA0-CA8); Page Length column addresses organization (CA0-CA7); Page Length column addresses
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM Extended Mode Register Command
This command extension Mode Register command. Please refer preceding Mode Register command description basic understanding. Extended Mode Register command used program latency choose between output driver impedances. Extended Mode Register command activated issuing Mode Register command with high. address inputs during this cycle define parameters shown following Extended Mode Register diagram. After Extended Mode Register command, clocks required before command issued. Mode Register command issued, Extended Mode Register settings revert their default values.
Extended Mode Register (Address Input Extended Mode Set)
Operation Mode
Reserved
Rsvd
Mode latency latency CL=1
Driver Impedance ohms (nom.) ohms (nom.)
Note: This device does require EMRS command. default setting latency two, driver impedance Ohms. Latency
latency parameter used coordinate data mask function with latency setting. This allows simultaneous data mask with Read command when latency one. latency defaults unless one. When latency three, this feature disabled, latency always regardless bits this register. This feature effect write latency, which always remains zero cycles.
Bank Activate Command
Bank Activate command issued holding CAS# high with RAS# rising edge clock. specify four banks, A11-A0 defines address load into sense amplifiers. When accessing data that already stored cache, Bank Activate command must issued before read write executed. When Bank Activate command given, address decoded sense amplifiers hold selected data. However, loaded into cache, contents cache remain unchanged. delay between Bank Activate command first read write must meet exceed delay time (tRCD). Once bank activated, must precharged before another Bank Activate command applied same bank. ESDRAM allows system issue Bank Activate command during burst read cycle. This because reads occur from cache, from DRAM array. Writes, however, require open page DRAM array. possible issue Bank Activate command during burst write.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice. Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
minimum time interval between interleaved Bank Activate commands bank-to-bank delay time (tRRD).
Read Command
Read command initiated holding CAS# RAS# high rising edge clock. address inputs determine starting address read. Mode register settings determine burst type (sequential interleaved), burst length full page), latency (the delay from command start data output). first Read command issued after Bank Activate command automatically loads cache. data mask activated (DQM high) during read cycle, corresponding data outputs disabled become high impedance after clock delay determined programmed latency. Please refer Extended Mode Register Command section setting latency.
Read Interrupted Read
read burst interrupted before completion burst another Read command. data from first Read command continues appear outputs until latency command satisfied. read different row, DRAM array must precharged reactivated between first interrupting Read command, loaded into cache.
Read Interrupted Write
read burst interrupted before completion burst Write command. must used avoid data contention placing output drivers (DQ15-DQ0) high impedance state least clock cycle before initiating Write command. must high least clock cycles before Write command, must same clock cycle Write command. ESDRAM allows user close page being read, open different page write, still read data from cache. write same page, Bank Activate command must issued before interrupting Write command reopen closed page.
Read Interrupted Precharge
read burst terminated Precharge command. data from Read command continues appear outputs until delay equal latency satisfied. Precharge command bank does terminate read burst from another bank.
Write Command
Write command initiated holding CS#, CAS#, RAS# high rising edge clock. address inputs determine starting address. There latency required write cycles. Data first write must supplied same clock cycle Write command. bursting, remaining data inputs must supplied each subsequent rising clock edge.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Unlike Read commands, which allow reads continue from cache while DRAM closed, Write commands require that DRAM remain open, even cache (page) hit. When write currently cache, both cache DRAM array updated maintain cache coherency. When write another row, must activated. This also transferred cache Write Transfer mode Mode register, when Write Transfer mode set. data mask activated (DQM high) during write cycle, write operation prohibited immediately with zero clock latency.
Write Interrupted Write
write burst interrupted before completion burst another Write command. When previous burst interrupted, remaining addresses ignored, data written addresses until programmed burst length satisfied.
Write Interrupted Read
Read command interrupts Write command same clock cycle that Read command registered. Only data present pins before Read command registered written memory. data must high impedance state least cycle before interrupting read data appears outputs avoid data contention.
Write Interrupted Precharge
write burst terminated Precharge command same bank. Write data written device during Precharge command masked. write burst bank terminated Precharge command another bank.
Burst Stop Command
There several ways terminate burst read burst write prematurely. These methods include using another Read Write command interrupt existing burst, using Precharge command interrupt burst close active bank, using Burst Stop command terminate existing burst leave bank open future reads writes same page active bank. When interrupting burst with another Read Write command care must taken avoid contention. Burst Stop command, however, fewer restrictions making easiest method use. Burst Stop command issued holding RAS# CAS# high, rising edge clock. When using this command stop read cycle, pins high impedance state after delay equal latency Mode register. When Burst Stop command terminates write cycle, data pins before command registered gets written memory.
Auto-Precharge Operation
Before opening active bank, bank must precharged using either Precharge command Auto-Precharge function. While decoding column address ESDRAM uses A10/AP allow active bank automatically begin precharge earliest possible moment. when Read Write command issued, normal read write operation executed, bank remains active. high when Read Write command issued, Auto-Precharge function engaged. When read with auto-precharge issued, active bank begins precharge next clock cycle. Therefore, precharge hidden during burst read cycles. ESDRAM cache allows Read commands execute even after precharged DRAM array. Once precharge starts, bank cannot reactivated until precharge time (tRP) satisfied.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice. Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
write with auto-precharge different than issuing Precharge command directly device. ESDRAM enters precharge clock cycle this case referred tDPL) after last write burst. bank being auto-precharged cannot reactivated until data-in active delay (tDAL tDPL tRP) satisfied. write with auto-precharge operation, including full page bursts, device auto-precharges when four commands issued: Precharge, Burst Stop, Read another bank, Write another Bank.
Precharge Command
Precharge command issued holding CS#, RAS#, CAS# high rising edge clock. This command precharges (closes) specified bank, banks once. Single banks specified using while A10/AP low. banks precharged A10/AP high. Precharge command terminates read after delay equal latency write current cycle. During reads when latency equals Precharge command applied last clock burst. During reads when latency equals Precharge command applied second last clock burst. During reads when latency equals three Precharge command applied third last clock burst. Precharge command issued sooner, terminates burst explained Read Command section. During writes data-in precharge delay (tDPL) from last clock burst must satisfied before Precharge command issued. Precharge command issued sooner, terminates burst explained Write Command section. After Precharge command issued, precharged bank must reactivated before Write command executed. minimum delay between Precharge command Bank Activate command must satisfy precharge time (tRP).
Auto Refresh Command (CAS before Refresh)
Auto-Refresh command (CBR) issued holding CS#, RAS#, CAS# CKE, high rising edge clock. banks must precharged before this command issued. contents each cache maintained during auto-refresh, reads continue. Once Auto-Refresh command issued, next Bank Activate command issued after delay least cycle time (tRC).
Self Refresh Command
Self Refresh command issued holding CS#, RAS#, CAS#, high rising edge clock. Refresh cycles generated internal clock long clocked low. inputs disabled except CKE, device placed power standby mode. external clock stopped during this operation, must cycling upon exit. ESDRAM exits self refresh second rising edge clock after returned high. next Bank Activate command issued after delay least cycle time (tRC).
Operation Command
Operation command (NOP) issued holding RAS#, CAS#, high rising edge clock. purpose prevent ESDRAM from registering unwanted commands. does terminate pending operations.
Deselect Command
Deselect command issued when high rising edge clock. This command performs same function NOP. Deselect command does terminate pending operations.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice. Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM Power Down Modes
Power Down mode initiated holding after banks precharged required precharge delay (tRP) satisfied. this mode refresh cycles occur device must remain this state longer than refresh period (tREF). Power Down mode exited clock cycle after bringing high.
Clock Suspend Mode
When brought during normal operation, execution current command suspended until clocked high. There clock delay after registration before ESDRAM operation suspended. Clock Suspend mode exited clock cycle after returns high. During read burst, last data held valid until normal operation resumes. During write burst, input data masked ignored until normal operation resumes.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Electrical Characteristics
Absolute Maximum Ratings
Description Symbol Value
Power Supply Voltage Power Supply Voltage Voltage with Respect Ground Operating Temperature (ambient) Storage Temperature Power Dissipation
VDDQ VIN, VOUT Tstg
+4.6V +4.6V, where VDDQ VDD+1V -0.5V +4.6V +70°C -55°C +150°C
Output Current (I/O pins) IOUT 50mA Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these, other conditions above those listed operational section specification, implied. Exposure conditions absolute maximum ratings extended periods affect device reliability. Operating Conditions 70°C)
Symbol Parameter Typical Units Notes
VDDQ VIH1 VIL1 VIH2 VIL2 II(L) IO(L) VOH1 VOL1 VOH2 VOL2
Notes:
Supply Voltage Supply Voltage Input High Voltage Input Voltage Input High Voltage pins) Input Voltage pins) Input Leakage Current (VSS VDD) Output Leakage Current (VSSQ VDDQ) Output High Voltage (IOUT -4mA) Output Voltage (IOUT +4mA) Output High Voltage (IOUT -2mA) Output Voltage (IOUT +2mA)
3.135 -0.3 -0.3
3.63 3.63 VDDQ
VDDQ must more than 0.3V higher than VDD. Applies input-only pins regardless VDDQ voltage. Applies pins when VDDQ 3.3V. Applies pins when VDDQ 2.5V.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Output Load Circuit
Output
VDDQ 3.3V (DC) 2.4V, -4mA (DC) 0.4V, 1.4V, VDDQ 2.5V (DC) 2.0V, -2mA (DC) 0.4V, 1.2V, =400
Capacitance 25°C, 1MHz, 3.3V +10%, -5%)
Symbol Parameter Typical Units Notes
CIn1 CIn2
Input Capacitance (BA1, BA0, A0-11) Input Capacitance (all control inputs) Output Capacitance (DQ0-15)
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Preliminary Datasheet Operating Currents 70°C, 3.3V +10%, -5%)
Parameter Symbol Test Condition
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Value
Units
Notes
ICC1A Operating Current (One Bank Active) ICCB ICC2P ICC2PS ICC2N ICC2NS ICC3N Device Deselected (DRAM Active) ICC3P ICC4A Burst Operating Current (All Banks Active) Auto (CBR) Refresh Current Self Refresh Current
Notes:
-7.5
1,2,3 1,2,3 3,4,5 3,4,5
Read Write, VIH(min), min., min. 2,3, Read Write, VIH(min), min., min. VIL, min., Input Change Every Cycles VIL, Infinity, Input Change VIH, min. VIH, Infinity VIH, min., Input Change Every Cycles VIL, min., Input Change Every Cycles Full Page, Read Write, Infinity, min. Full Page, 2,3, Read Write, Infinity, min. min., tRC(min). min., 15.625 0.2V, Input Change
Standby Current Power Down Mode (DRAM Precharged) Standby Current NonPower Down Mode (DRAM Precharged)
ICC4B ICC5F ICC5D ICC6
specified value obtained with outputs open. specified value obtained when programmed burst length executed completion without interruption subsequent burst read burst write cycle. specified value valid when addresses changed more than once during tCK(min). specified value valid when Operation commands registered every rising clock edge during tRC(min). specified value valid when data inputs (DQs) stable during tRC(min).
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM Characteristics 70°C, 3.3V +10%, -5%)
After power applied VDDQ (simultaneously) clock stable, initial pause 100µs required. After 100µs delay satisfied least DESEL applied, Precharge Banks command must given followed minimum Auto (CBR) Refresh cycles before Mode Register operation begin. VDDQ 3.3V, timing tests have 2.8V with timing referenced 1.4V crossover point.
tSETUP tHOLD Input Output 1.4V
Clock
Output
CLOAD 50pF
Output Load Curcuit
measurements assume address transition clock cycle. addition meeting transition rate specification, clock must transition between VIL) monotonic manner. CLOAD value speed grade 30pF.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Clock Clock Enable Parameters
Symbol tCK2 tCK1 tAC3 tAC2 tAC1 tCKH2, tCKL2 tCKH1, tCKL2 tCKES tCKEH tCKSP Notes: Access time measured 1.4V (LVTTL) VDDQ 3.3V +10%, -5%. Test Load. Access time based clock rise time 1ns. clock rise time longer than 1ns, then (trise/2 0.5) must added access time. Assumes clock rise fall times equal 1ns. rise fall time exceeds 1ns, other timing parameters must compensated additional [(trise+tfall)/2 Parameter Clock Cycle Time, Clock Cycle Time, Clock Access Time, Clock Access Time, Clock Access Time, Clock High Times, Clock High Times, Clock Enable Set-Up Time Clock Enable Hold Time Set-Up Time (Power down mode) Transition Time (Rise Fall) 166MHz 83MHz 10.5 -7.5 133MHz 66MHz 100MHz 66MHz 11.5 Units Notes
Common Parameters
Symbol tRCD tRAS tRRD tCCD tMRD Parameter Command Address Set-Up Time Command Address Hold Time Delay Time Bank Cycle Time Bank Active Time Precharge Time Bank Bank Delay Time (Alt. Bank) Delay Time (Same Bank) Mode Register Active Delay 120K 37.5 22.5 -7.5 120K 120K Units Notes
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Read Write Parameters
Symbol tOH3 tOH2 tOH1 tHZ3 tHZ2 tHZ1 tDPL tDAL Notes: Parameter Data Output Hold Time Data Output Hold Time Data Output Hold Time Data Output Low-Z Time Data Output High-Z Time Data Output High-Z Time Data Output High-Z Time Data Input Setup Time Data Input Hold Time Data Input Precharge Data Input ACTV/Refresh 22.5 -7.5
Units
Notes
Output timings measured 1.4V (LVTTL) VDDQ 3.3V +10%, clock rate latency specified. Test Load. tDAL equal tDPL tRP.
Refresh Parameters
Symbol tREF tSREX Notes: 4096 cycles. Anytime refresh period exceeded, minimum Auto-Refresh (CBR) commands must given "wake device. Self Refresh Exit synchronous operation begins second positive clock edge after returns high. Self Refresh Exit completed until satisfied once Self Refresh Exit command registered. Parameter Refresh Period Self Refresh Exit Time 2CLK +tRC 2CLK +tRC -7.5 2CLK +tRC Units Notes
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Timing Diagrams Bank Address, Address, Column Address)
Power Initialization Sequence
tMRD
tMRD
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) Internal Status Banks
Precharge Hi-Z
Code
Code
Code
Code
Refresh
Refresh
EMRS
Bank Active
After Power applied VDDQ, clock stable, initial pause 100µs required. Once this delay satisfied, controller must issue DESEL commands prior signaling shown this diagram. EMRS command optional.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Burst Reads
tRCD tRAS tRCD tRAS
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) Internal Status Bank Cache
Active Idle Active Idle
mode ESDRAM perform burst reads without wait states. timing shown worst-case situation which read from followed read from both bank cache loaded Read command DRAM bank auto-precharged clock cycle following Read command. Once precharge time satisfied, DRAM bank idle re-activated refreshed.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Preliminary Datasheet Burst Reads
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
tRCD tRAS tRCD tRAS
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) Internal Status Banks Cache
Active Precharge Active Precharge Idle
mode ESDRAM delivers worst-case burst read data with only wait state clock rates MHz. This high performance achieved through combination fast DRAM core timings SRAM cache.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Burst Writes
tRCD tRAS
tDPL
tRCD
tDPL
tRAS
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) Internal Status Bank Cache
Active Precharge Active Precharge Idle
Cache modified column addresses.
This diagram shows burst writes followed burst write Once DRAM bank activated, Write command caches row. Data used update both SRAM cache DRAM bank column addresses specified. frequencies below MHz, tRCD times reduced clock cycle.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Preliminary Datasheet Read/Write/Read
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
tRCD tDPL tRCD tRAS
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) Internal Status Bank Cache
Active Active Idle
Cache modified column addresses.
This pattern shows SRAM cache being loaded Read command while DRAM remains active. write follows, data used update both DRAM bank SRAM cache column addresses SRAM cache otherwise undisturbed. read from shown illustrate earliest time bank re-activated.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Write Transfer Mode
tRCD tRAS tRCD
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) Internal Status Bank Cache
Active Idle Active
ESDRAM device provides unique capability. Within same bank, cached subsequent write different performed while keeping read cache intact. burst reads from burst writes shown.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Preliminary Datasheet Hidden Refresh
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
tRCD tRAS
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) Internal Status Bank Cache
Refresh Active Precharge Refresh Active Idle
Previously Loaded
This diagram shows three burst reads while device performs refresh cycles. four SRAM caches read while DRAM refreshing, precharging, idle. four banks must idle before issuing AutoRefresh (CBR) command.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Burst Termination
RAS# CAS# BA(1:0) A11, A10/AP A(8:0) (CL1) (CL2) Internal Status Bank Bank
Active Precharge Idle
Active
Precharge
Idle
burst reads, Precharge Burst Termination commands hi-Z clock cycles. single bank PreCharge command bank that bursting pre-charges that bank, does terminate other bank's burst. burst writes, Precharge Burst Termination commands terminate burst same clock cycle which command registered ESDRAM.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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Preliminary Datasheet Operation (Default Settings)
64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
(CL1)
(CL2)
(CL3)
Read
Write
Operation (EMR bit-9
(CL1)
(CL2)
(CL3)
Read
Write
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Operation
Commands ignored clock following low.
(CL1) (CL2) (CL3)
Read
Write
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Mechanical Drawing (400mil, 54-pin TSOP)
22.22 0.13
10.16 0.13
VIEW
Lead Seating Plane
11.76 0.20
0.10 0.80 Basic 0.35 0.10 0.05 0.805
1.20
0.25 Basic
Gage Plane
0.05
dimensions shown unless specified otherwise
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM Revision
Revision Date 11/20/00 01/29/02 Summary Changes
First release. Changed power supply limits 3.3V +10%, -5%. Updated supply current values. Changed input/output leakage current limits 5uA. Corrected BA1,BA0 settings Extended Mode Register command.
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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64Mbit Enhanced SDRAM 8Mx8, 4Mx16 ESDRAM
Ordering Information
Maximum Operating Frequency (MHz)
Part Number
Latencies
Width
Type
Package
Power Supply 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
SM2603T-6 SM2604T-6 SM2603T-7.5 SM2604T-7.5 SM2603T-10 SM2604T-10
LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V LVTTL, 2.5V
54-pin TSOP 54-pin TSOP 54-pin TSOP 54-pin TSOP 54-pin TSOP 54-pin TSOP
This product sampling pre-production phase development. Characteristic data other specifications subject change without notice.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, 80921 PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
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SM2603 2604 Enhanced SDRAM (ESDRAM) devices JEDEC superset standard SD

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