HCPL-3120 HCPL-J312 HCNW3120 Minimum Peak Output Current kV/µs Mi
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Output Current IGBT Gate Drive Optocoupler Technical Data
HCPL-3120 HCPL-J312 HCNW3120
Minimum Peak Output Current kV/µs Minimum Common Mode Rejection (CMR) 1500 Maximum Level Output Voltage (VOL) Eliminates Need Negative Gate Drive Maximum Supply Current Under Voltage Lock-Out Protection (UVLO) with Hysteresis Wide Operating Range: Volts Maximum Switching Speeds Industrial Temperature Range: -40°C 100°C Safety Approval Recognized 2500 Vrms min. HCPL-3120 3750 Vrms min. HCPL-J312 5000 Vrms min. HCNW3120
Approval 0884 Approved VIORM Vpeak HCPL-3120 (Option 060) VIORM Vpeak HCPL-J312 VIORM 1414 Vpeak HCNW3120 Certified (HCNW3120 only) (Pending)
Applications
IGBT/MOSFET Gate Drive AC/Brushless Motor Drives Industrial Inverters Switch Mode Power Supplies
Functional Diagram
HCPL-3120/J312 HCNW3120
ANODE CATHODE
ANODE CATHODE
SHIELD
SHIELD
TRUTH TABLE "POSITIVE GOING" "NEGATIVE GOING" (i.e., TURN-ON) (i.e., TURN-OFF) 13.5 13.5
TRANSITION HIGH
bypass capacitor must connected between pins
CAUTION: advised that normal static precautions taken handling assembly this component prevent damage and/or degradation which induced ESD.
Description
HCPL-3120 contains GaAsP while HCPL-J312 HCNW3120 contain AlGaAs LED. optically coupled integrated circuit with power output stage. These optocouplers ideally suited driving power IGBTs MOSFETs used motor control inverter applications. high
operating voltage range output stage provides drive voltages required gate controlled devices. voltage current supplied these optocouplers make them ideally suited directly driving IGBTs with ratings 1200 V/100 IGBTs with higher ratings, HCPL-3120 series used drive discrete power
stage which drives IGBT gate. HCNW3120 highest insulation voltage VIORM 1414 Vpeak VDE0884. HCPL-J312 insulation voltage VIORM Vpeak VIORM Vpeak also available with HCPL-3120 (Option 060).
Selection Guide
Part Number Output Peak Current VDE0884 Approval HCPL-3120 HCPL-J312 VIORM Vpeak VIORM Vpeak (Option 060) HCNW3120 VIORM 1414 Vpeak HCPL-3150* VIORM Vpeak (Option 060)
*The HCPL-3150 Data sheet available. Contact Hewlett-Packard sales representative authorized distributor.
Ordering Information
Specify Part Number followed Option Number desired) Example: HCPL-3120#XXX VDE0884, VIORM Vpeak (HCPL-3120 only) Gull Wing Surface Mount Option Tape Reel Packaging Option Option contains 1000 units (HCPL-3120/J312), units (HCNW3120) reel. Other options contain units (HCPL-3120/J312), units (HCNW312) tube. Option data sheets available. Contact Hewlett-Packard sales representative authorized distributor.
Package Outline Drawings
HCPL-3120 HCPL-J312 Outline Drawing (Standard Package)
9.65 0.25 (0.380 0.010) TYPE NUMBER 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010)
OPTION CODE* DATE CODE
XXXXZ YYWW 1.19 (0.047) MAX.
1.78 (0.070) MAX. 0.076 0.254 0.051 0.003) (0.010 0.002)
TYP. 4.70 (0.185) MAX.
0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS MILLIMETERS (INCHES). 1.080 0.320 (0.043 0.013) 0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010) MARKING CODE LETTER OPTION NUMBERS. (HCPL-3120 ONLY) OPTION OPTION NUMBERS MARKED.
HCPL-3120 HCPL-J312 Gull Wing Surface Mount Option Outline Drawing
LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
1.016 (0.040) 1.194 (0.047)
4.826 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.398 (0.370) 9.906 (0.390)
1.194 (0.047) 1.778 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.381 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
0.076 0.254 0.051 0.003) (0.010 0.002)
1.080 0.320 (0.043 0.013) 0.635 0.130 2.54 (0.025 0.005) (0.100) DIMENSIONS MILLIMETERS (INCHES). LEAD COPLANARITY 0.10 (0.004 INCHES).
0.635 0.25 (0.025 0.010)
NOM.
HCNW3120 Outline Drawing (8-Pin Wide Body Package)
11.15 0.15 (0.442 0.006)
11.00 MAX. (0.433) 9.00 0.15 (0.354 0.006) TYPE NUMBER
HCNWXXXX YYWW
DATE CODE
1.55 (0.061) MAX.
10.16 (0.400) TYP. TYP. 0.076 0.254 0.0051 0.003) (0.010 0.002)
5.10 MAX. (0.201)
3.10 (0.122) 3.90 (0.154) 2.54 (0.100) TYP. 1.78 0.15 (0.070 0.006) 0.40 (0.016) 0.56 (0.022)
0.51 (0.021) MIN.
DIMENSIONS MILLIMETERS (INCHES).
HCNW3120 Gull Wing Surface Mount Option Outline Drawing
11.15 0.15 (0.442 0.006)
LOCATION (FOR REFERENCE ONLY)
6.15 (0.242)TYP. 9.00 0.15 (0.354 0.006) 12.30 0.30 (0.484 0.012)
(0.051) 1.55 (0.061) MAX. 12.30 0.30 (0.484 0.012) 11.00 MAX. (0.433)
(0.035)
4.00 MAX. (0.158)
1.78 0.15 (0.070 0.006) 2.54 (0.100) 0.75 0.25 (0.030 0.010)
1.00 0.15 (0.039 0.006)
0.076 0.254 0.0051 0.003) (0.010 0.002) NOM.
DIMENSIONS MILLIMETERS (INCHES). LEAD COPLANARITY 0.10 (0.004 INCHES).
Reflow Temperature Profile
145°C, 1°C/SEC 115°C, 0.3°C/SEC
TEMPERATURE
100°C, 1.5°C/SEC
TIME MINUTES MAXIMUM SOLDER REFLOW THERMAL PROFILE (NOTE: NON-CHLORINE ACTIVATED FLUXES RECOMMENDED.)
Regulatory Information
Agency/Standard
Underwriters Laboratory (UL)
HCPL-3120
HCPL-J312
HCNW3120
Recognized under 1577, Component Recognition
Program, Category, File E55361
Canadian Standards Association (CSA) File CA88324, Component Acceptance Notice Verband Deutscher Electrotechniker (VDE) 0884 (June 1992) British Standards Institute (BSI) Certification According EN60065: 1994 (BS415:1994), EN60950: 1992 (BS7002:1992) Option Pending
Insulation Safety Related Specifications
Value HCPL- HCPLSymbol 3120 J312 L(101) HCNW 3120
Parameter Minimum External (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group
Units
L(102)
10.0
0.08
>175
>175
>200
Volts
Conditions Measured from input terminals output terminals, shortest distance through air. Measured from input terminals output terminals, shortest distance path along body. Insulation thickness between emitter detector; also known distance through insulation. 112/VDE 0303 Part
IIIa
IIIa
IIIa
Material Group (DIN 0110, 1/89, Table
Hewlett-Packard data sheets report creepage clearance inherent optocoupler component itself. These dimensions needed starting point equipment designer when determining circuit insulation requirements. However, once mounted printed circuit
board, minimum creepage clearance requirements must specified individual equipment standards. creepage, shortest distance path along surface printed circuit board between solder fillets input output leads must considered. There
recommended techniques such grooves ribs which used printed circuit board achieve desired creepage clearances. Creepage clearance distances will also change depending factors such pollution degree insulation level.
VDE0884 Insulation Related Characteristics
Description Installation classification 0110/1.89, Table rated mains voltage rated mains voltage rated mains voltage rated mains voltage rated mains voltage 1000 Climatic Classification Pollution Degree (DIN 0110/1.89) Maximum Working Insulation Voltage Input Output Test Voltage, Method VIORM 1.875 VPR, 100% Production Test, sec, Partial Discharge Input Output Test Voltage, Method VIORM VPR, Type Sample Test, sec, Partial Discharge Highest Allowable Overvoltage* (Transient Overvoltage, tini sec) Safety Limiting Values maximum values allowed event failure, also Figure Case Temperature Input Current Output Power Insulation Resistance Symbol HCPL-3120 Option HCPL-J312 HCNW3120 Unit
I-IV I-IV I-III
I-IV I-IV I-III I-III 55/100/21 1670
VIORM
55/100/21 1181
I-IV I-IV I-IV I-IV I-III 55/100/21 1414 2652
Vpeak Vpeak
1336
2121
Vpeak
VIO
6000
6000
8000
Vpeak
INPUT OUTPUT
*Refer VDE0884 section (page 1-6/8) Isolation Control Component Designer's Catalog detailed description Method partial discharge test profiles. Note: These optocouplers suitable "safe electrical isolation" only within safety limit data. Maintenance safety data shall ensured means protective circuits. Surface mount classification Class accordance with CECC 00802.
Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current pulse width, pps) Reverse Input Voltage HCPL-3120 HCPL-J312 HCNW3120 "High" Peak Output Current "Low" Peak Output Current Supply Voltage Input Current (Rise/Fall Time) Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder HCPL-3120 Temperature HCPL-J312 HCNW3120 Solder Reflow Temperature Profile Symbol IF(AVG) IF(TRAN) Min. Max. Units Volts Note
IOH(PEAK) IOL(PEAK) (VCC VEE) tr(IN) tf(IN) VO(PEAK)
Volts Volts 260°C sec., below seating plane 260°C sec., seating plane Package Outline Drawings section
Recommended Operating Conditions
Parameter Power Supply Voltage Input Current (ON) HCPL-3120 HCPL-J312 HCNW3120 Input Voltage (OFF) Operating Temperature Symbol (VCC VEE) IF(ON) VF(OFF) Min. -3.0 Max. Units Volts
Electrical Specifications (DC)
Over recommended operating conditions 100°C, F(ON) VF(OFF) -3.0 Ground) unless otherwise specified.
Parameter High Level Symbol IFLH HCPL-3120 HCPL-J312 HCNW3120 Device Min. Typ.* (VCC (VCC Max. Units Test Conditions (VCC (VCC (VEE (VEE -100 Fig. Note
Output Current
Level
Output Current
High Level Output Voltage Level Output Voltage High Level Supply Current Level Supply Current Threshold Input Current High Threshold Input Voltage High Input Forward Voltage Temperature Coefficient Forward Voltage Input Reverse Breakdown Voltage Input Capacitance UVLO Threshold
Output Open, Output Open, -3.0 +0.8
VFHL
HCPL-3120 HCPL-J312 HCNW3120 HCPL-3120 HCPL-J312 HCNW3120 HCPL-3120 HCPL-J312 HCNW3120 HCPL-3120 HCPL-J312 HCNW3120
-1.6 -1.3
1.95
mV/°C
11.0 12.3 10.7 13.5 12.0
MHz,
VUVLO+
VUVLO- UVLO Hysteresis UVLOHYS
*All typical values 25°C unless otherwise noted.
Switching Specifications (AC)
Over recommended operating conditions 100°C, IF(ON) VF(OFF) -3.0 Ground) unless otherwise specified. Parameter Symbol Min. Propagation Delay tPLH 0.10 Time High Output Level Propagation Delay tPHL 0.10 Time Output Level Pulse Width Distortion Propagation Delay -0.35 Difference Between (tPHL tPLH) Parts Rise Time Fall Time UVLO Turn tUVLO Delay UVLO Turn tUVLO Delay Output High Level |CMH| Common Mode Transient Immunity Output Level |CML| Common Mode Transient Immunity Typ.* 0.30 Max. 0.50 Units Test Conditions kHz, Duty Cycle Fig. Note
0.30
0.50
0.35
kV/µs
kV/µs
25°C, 1500 25°C, 1500
*All typical values 25°C unless otherwise noted.
Package Characteristics
Over recommended temperature 100°C) unless otherwise specified. Parameter Symbol Device Min. Typ. Max. Units Test Conditions Input-Output VISO HCPL-3120 2500 VRMS 50%, Momentary HCPL-J312 3750 min., Withstand Voltage** HCNW3120 5000 25°C Resistance RI-O HCPL-3120 1012 VI-O (Input-Output) HCPL-J312 HCNW3120 1012 1013 25°C 1011 100°C Capacitance CI-O HCPL-3120 (Input-Output) HCPL-J312 HCNW3120 LED-to-Case °C/W Thermocouple Thermal Resistance located center LED-to-Detector °C/W underside package Thermal Resistance Detector-to-Case °C/W Thermal Resistance Fig. Note
*All typicals 25°C. **The Input-Output Momentary Withstand Voltage dielectric voltage rating that should interpreted input-output continuous voltage rating. continuous voltage rating refer your equipment level safety specification Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." Notes: Derate linearly above 70°C free-air temperature rate mA/°C. Maximum pulse width maximum duty cycle 0.2%. This value intended allow component tolerances designs with peak minimum Applications section additional details limiting peak. Derate linearly above 70°C free-air temperature rate mW/°C. Derate linearly above 70°C free-air temperature rate mW/°C. maximum junction temperature should exceed 125°C. Maximum pulse width maximum duty cycle 0.5%. this test measured with load current. When driving capacitive loads will approach approaches zero amps. Maximum pulse width maximum duty cycle 20%. accordance with UL1577, each optocoupler proof tested applying insulation test voltage 3000 Vrms second (leakage detection current limit, II-O µA). accordance with UL1577, each optocoupler proof tested applying insulation test voltage 4500 Vrms second (leakage detection current limit, II-O µA). accordance with UL1577, each optocoupler proof tested applying insulation test voltage 6000 Vrms second (leakage detection current limit, II-O µA). Device considered two-terminal device: pins shorted together pins shorted together. difference between tPHL tPLH between HCPL-3120 parts under same test condition. Pins need connected common. Common mode transient immunity high state maximum tolerable dVCM common mode pulse, VCM, assure that output will remain high state (i.e., 15.0 Common mode transient immunity state maximum tolerable dVCM/dt common mode pulse, VCM, assure that output will remain state (i.e., This load condition approximates gate load 1200 V/75A IGBT. Pulse Width Distortion (PWD) defined |tPHL-t PLH| given device.
(VOH HIGH OUTPUT VOLTAGE DROP
OUTPUT HIGH CURRENT
(VOH OUTPUT HIGH VOLTAGE DROP
IOUT -100
VOUT (VCC
TEMPERATURE
TEMPERATURE
OUTPUT HIGH CURRENT
Figure Temperature.
Figure Temperature.
Figure
0.25
OUTPUT VOLTAGE
(OFF) -3.0 IOUT
(OFF) -3.0 VOUT
OUTPUT VOLTAGE
0.20
OUTPUT CURRENT
VF(OFF) -3.0
0.15
0.10
0.05
OUTPUT CURRENT
TEMPERATURE
TEMPERATURE
Figure Temperature.
Figure Temperature.
Figure IOL.
SUPPLY CURRENT
SUPPLY CURRENT
ICCH ICCL
ICCH ICCL
ICCH ICCL
ICCH ICCL
TEMPERATURE
SUPPLY VOLTAGE
Figure Temperature.
Figure VCC.
IFLH HIGH CURRENT THRESHOLD
IFLH HIGH CURRENT THRESHOLD
HCPL-3120 OUTPUT OPEN
HCPL-J312 OUTPUT OPEN
IFLH HIGH CURRENT THRESHOLD
HCNW3120 OUTPUT OPEN
TEMPERATURE
TEMPERATURE
TEMPERATURE
Figure IFLH Temperature.
PROPAGATION DELAY
PROPAGATION DELAY
DUTY CYCLE
PROPAGATION DELAY
DUTY CYCLE
TPLH TPHL
DUTY CYCLE
TPLH TPHL
TPLH TPHL
SUPPLY VOLTAGE
FORWARD CURRENT
TEMPERATURE
Figure Propagation Delay VCC.
Figure Propagation Delay
Figure Propagation Delay Temperature.
PROPAGATION DELAY
PROPAGATION DELAY
DUTY CYCLE
DUTY CYCLE
TPLH TPHL
TPLH TPHL
SERIES LOAD RESISTANCE
LOAD CAPACITANCE
Figure Propagation Delay
Figure Propagation Delay
HCPL-3120 HCNW3120
HCPL-J312
OUTPUT VOLTAGE
OUTPUT VOLTAGE
FORWARD CURRENT
FORWARD CURRENT
Figure Transfer Characteristics.
1000
FORWARD CURRENT
HCPL-3120
HCPL-J312/HCNW3120 1000
FORWARD CURRENT
25°C
25°C 0.01
0.01
0.001 1.10
1.20
1.30
1.40
1.50
1.60
0.001
FORWARD VOLTAGE VOLTS
FORWARD VOLTAGE VOLTS
Figure Input Current Forward Voltage.
Figure Test Circuit.
Figure Test Circuit.
Figure Test Circuit.
Figure Test Circuit.
Figure Test Circuit.
Figure UVLO Test Circuit.
DUTY CYCLE
VOUT tPLH tPHL
Figure tPLH, PHL, Test Circuit Waveforms.
SWITCH SWITCH 1500
Figure Test Circuit Waveforms.
Applications Information
Eliminating Negative IGBT Gate Drive (Discussion applies
HCPL-3120, HCPL-J312, HCNW3120)
keep IGBT firmly off, HCPL-3120 very maximum specification HCPL-3120 realizes this very using DMOS transistor with (typical) resistance pull down circuit. When HCPL-
3120 state, IGBT gate shorted emitter Minimizing lead inductance from HCPL3120 IGBT gate emitter (possibly mounting HCPL-3120 small board directly above IGBT) eliminate need negative IGBT gate drive many applications shown Figure Care should taken with such board design avoid routing
IGBT collector emitter traces close HCPL-3120 input this result unwanted coupling transient signals into HCPL-3120 degrade performance. IGBT drain must routed near HCPL3120 input, then should reverse-biased when state, prevent transient signals coupled from IGBT drain from turning HCPL-3120.)
HCPL-3120
HVDC
CONTROL INPUT 74XXX OPEN COLLECTOR
3-PHASE
HVDC
Figure Recommended Drive Application Circuit.
Selecting Gate Resistor (Rg) Minimize IGBT Switching Losses. (Discussion applies HCPL-3120, HCPLJ312 HCNW3120) Step Calculate Minimum from Peak Specification. IGBT Figure analyzed simple circuit with voltage supplied HCPL-3120.
(VCC VOL) --------------- OLPEAK (VCC --------------- OLPEAK ------------------
value previous equation conservative value peak current 2.5A (see Figure lower values voltage supplied HCPL-3120 ideal voltage step. This results lower peak currents (more margin) than predicted this analysis. When negative gate drive used previous equation equal zero volts.
HCPL-3120
HVDC
CONTROL INPUT 74XXX OPEN COLLECTOR
3-PHASE
HVDC
Figure HCPL-3120 Typical Application Circuit with Negative IGBT Gate Drive.
Step Check HCPL-3120 Power Dissipation Increase Necessary. HCPL-3120 total power dissipation (PT) equal emitter power output power (PO): Duty Cycle PO(BIAS) (SWITCHING) (VCC VEE) ESW(R circuit Figure with (worst case) Duty Cycle 80%, 85C: 4.25 (PO(MAX) mW-15C*4.8 mW/C)
value 4.25 previous equation obtained derating (which occurs -40°C) (see Figure Since this case greater than PO(MAX), must increased reduce HCPL-3120 power dissipation. PO(SWITCHING MAX) PO(MAX) PO(BIAS) PO(SWITCHINGMAX) ESW(MAX) --------------- ------- 4.65 from Figure value 4.65 gives 10.3
Parameter Duty Cycle
Description Current Voltage Maximum Duty Cycle
Parameter ESW(Rg,Qg)
Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated HCPL-3120 each IGBT Switching Cycle (See Figure Switching Frequency
ENERGY SWITCHING CYCLE
1000
GATE RESISTANCE
Figure Energy Dissipated HCPL-3120 Each IGBT Switching Cycle.
Thermal Model (Discussion applies HCPL-3120, HCPL-J312 HCNW3120)
steady state thermal model HCPL-3120 shown Figure thermal resistance values given this model used calculate temperatures each node given operating condition. shown model, heat generated flows through which raises case temperature accordingly. value depends conditions board design therefore, determined designer. value 83°C/W obtained from thermal measurements using inch
board, with small traces ground plane), single HCPL3120 soldered into center board still air. absolute maximum power dissipation derating specifications assume CAvalue 83°C/W. From thermal mode Figure detector junction temperatures expressed (LC||(LD ----------------
Inserting values shown Figure gives: (256°C/W (57°C/W (57°C/W (111°C/W example, given 70°C 83°C/W:
339°C/W 140°C/W 339°C/W 140°C/W 70°C 120°C 140°C/W 194°C/W 140C/W 194°C/W 70°C 125°C
---------------
(DC||(LD
should limited 125°C based board layout part placement (CA) specific application.
°C/W °C/W °C/W* °C/W
junction temperature detector junction temperature case temperature measured center package bottom LED-to-case thermal resistance LED-to-detector thermal resistance detector-to-case thermal resistance case-to-ambient thermal resistance will depend board design placement part.
Figure Thermal Model.
Drive Circuit Considerations Ultra High Performance.
(Discussion applies HCPL3120, HCPL-J312, HCNW3120)
Without detector shield, dominant cause optocoupler failure capacitive coupling from input side optocoupler, through package, detector shown Figure HCPL3120 improves performance
using detector with optically transparent Faraday shield, which diverts capacitively coupled current away from sensitive circuitry. However, this shield does eliminate capacitive coupling between optocoupler pins shown Figure This capacitive coupling causes perturbations current during common mode transients becomes major source failures
shielded optocoupler. main design objective high drive circuit becomes keeping proper state off) during common mode transients. example, recommended application circuit (Figure 25), achieve kV/µs while minimizing component complexity. Techniques keep proper state discussed next sections.
CLEDP
CLEDO1 CLEDP
CLEDO2
CLEDN
CLEDN
SHIELD
Figure Optocoupler Input Output Capacitance Model Unshielded Optocouplers.
Figure Optocoupler Input Output Capacitance Model Shielded Optocouplers.
with (CMRH).
high drive circuit must keep during common mode transients. This achieved overdriving current beyond input threshold that pulled below threshold during transient. minimum current provides adequate margin over maximum IFLH achieve kV/µs CMR.
with (CMRL).
high drive circuit must keep VF(OFF)) during common mode transients. example, during -dVcm/dt transient Figure current flowing through LEDP also flows through RSAT VSAT logic gate. long state voltage developed across logic gate less than VF(OFF), will remain common mode failure will occur.
open collector drive circuit, shown Figure cannot keep during +dVcm/dt transient, since current flowing through CLEDN must supplied LED, recommended applications requiring ultra high CMRL performance. Figure alternative drive circuit which, like recommended application circuit (Figure 25), does achieve ultra high performance shunting state.
CLEDP
ILEDP
VSAT
CLEDP
CLEDN
SHIELD
CLEDN ILEDN
ARROWS INDICATE DIRECTION CURRENT FLOW DURING -dVCM/dt.
SHIELD
Figure Equivalent Circuit Figure During Common Mode Transient.
Figure Recommended Open Collector Drive Circuit.
CLEDP
CLEDN
SHIELD
Figure Recommended Drive Circuit Ultra-High CMR.
Under Voltage Lockout Feature. (Discussion applies
HCPL-3120, HCPL-J312, HCNW3120)
HCPL-3120 contains under voltage lockout (UVLO) feature that designed protect IGBT under fault conditions which cause HCPL-3120 supply voltage (equivalent
fully-charged IGBT gate voltage) drop below level necessary keep IGBT resistance state. When HCPL-3120 output high state supply voltage drops below HCPL-3120 VUVLO- threshold (9.5 VUVLO- 12.0) optocoupler output will into state with typical delay, UVLO Turn Delay,
When HCPL-3120 output state supply voltage rises above HCPL3120 VUVLO+ threshold (11.0 VUVLO+ 13.5) optocoupler output will into high state (assumes "ON") with typical delay, UVLO Turn Delay
OUTPUT VOLTAGE
(10.7, 0.1) (12.3, 0.1) (12.3, 10.8) (10.7, 9.2)
(VCC SUPPLY VOLTAGE
Figure Under Voltage Lock Out.
Dead Time Propagation Delay Specifications. (Discussion
applies HCPL-3120, HCPLJ312, HCNW3120)
HCPL-3120 includes Propagation Delay Difference (PDD) specification intended help designers minimize "dead time" their power inverter
designs. Dead time time period during which both high side power transistors Figure off. overlap conduction will result large currents flowing through power devices between high voltage motor rails.
ILED1
ILED1
VOUT1
VOUT1
VOUT2 ILED2
VOUT2
ILED2
tPHL tPLH PDD* (tPHL- tPLH)MAX tPHL tPLH
tPHL tPHL tPLH
*PDD PROPAGATION DELAY DIFFERENCE NOTE: CALCULATIONS PROPAGATION DELAYS TAKEN SAME TEMPERATURE TEST CONDITIONS.
tPLH (tPHL-tPLH) PDD*
Figure Minimum Skew Zero Dead Time.
MAXIMUM DEAD TIME (DUE OPTOCOUPLER) (tPHL tPHL MIN) (tPLH tPLH MIN) (tPHL tPLH MIN) (tPHL tPLH MAX) PDD* PDD* *PDD PROPAGATION DELAY DIFFERENCE NOTE: DEAD TIME CALCULATIONS PROPAGATION DELAYS TAKEN SAME TEMPERATURE TEST CONDITIONS.
Figure Waveforms Dead Time.
OUTPUT POWER INPUT CURRENT
OUTPUT POWER INPUT CURRENT
HCPL-3120 OPTION 060/HCPL-J312 (mW) (mA) HCPL-3120 OPTION (mA) HCPL-J312
1000
HCNW3120 (mW) (mA)
CASE TEMPERATURE
CASE TEMPERATURE
Figure Thermal Derating Curve, Dependence Safety Limiting Value with Case Temperature 0884.
minimize dead time given design, turn LED2 should delayed (relative turn LED1) that under worst-case conditions, transistor just turned when transistor turns shown Figure amount delay necessary achieve this conditions equal maximum value propagation delay difference specification, PDDMAX, which specified over operating temperature range -40°C 100°C.
Delaying signal maximum propagation delay difference ensures that minimum dead time zero, does tell designer what maximum dead time will maximum dead time equivalent difference between maximum minimum propagation delay difference specifications shown Figure maximum dead time HCPL-3120 (-350 ns)) over operating temperature range -40°C 100°C.
Note that propagation delays used calculate dead time taken equal temperatures test conditions since optocouplers under consideration typically mounted close proximity each other switching identical IGBTs.
technical assistance location your nearest Hewlett-Packard sales office, distributor representative call: Americas/Canada: 1-800-235-0312 408-654-8675 East/Australasia: Call your local sales office. Japan: 3335-8152 Europe: Call your local sales office. Data subject change. Copyright 1997 Hewlett-Packard Obsoletes 5965-4779E Printed U.S.A. 5965-7875E (7/97)
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