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Document No.: AX88655-1.0 V1.0 Mar, 12,2002 5-Port Gigabit Ethern


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AX88655 5-Port 10/100/1000BASE-T Ethernet Switch 5-Port Gigabit Ethernet Switch with Embedded Memory
Document No.: AX88655-1.0 V1.0 Mar, 12,2002
5-Port Gigabit Ethernet switch integrating MACs, packet buffer memory switching engine with GMII/MII interface Full Duplex 1000 Mbit/s. Full Half Duplex 10/100 Mbit/s Supports auto-sensing manual selection speed duplex capability with embedded Store-and-forward operation support Performs full wire-speed switching with blocking Broadcast storm control Quality-of-Service provisioning 802.1P port-pairs with priority queues Embedded 128K Byte SRAM packet buffer
Integrated two-way Address-Lookup engine table addresses Programmable aging mechanism two-way addresses table Full-duplex IEEE 802.3x flow control Half-duplex back pressure flow control Port trunking high-bandwidth links Provides GPIO ports Provides EEPROM interface auto-configuration System clock input 27MHz Crystal 125MHz Oscillator 3.3V operations I/Os packaged 256-pin PQFP
Product Description
AX88655 5-Port 10/100/1000 Mbps Ethernet switch with GMII Interface. switch controller provides network system manufacturers ideal platform building smart cost-effective backbone switches small medium sized businesses. AX88655 5-Port 10/100/100 BASE-T single chip switch controllers combine benefits network simplicity, flexibility high integration. highly integrated feature enables network system manufacturers build smart switches fast-growing small medium business market segment. Benefits AX88655 Switches below. Simplicity Provides smart, simple maintenance plug-and-play network interconnect system small medium size businesses Flexibility Highly scalable configuration allows system manufacturers enable disable range features best meet their target price point Integration Highly integrated design drives down overall switch manufacturing costs.
Target Applications
5-Port Gigabit Layer Switches workgroup High-port count Layer switches with trunking High performance solution Ethernet backbone
Always contact ASIX possible updates before starting design.
This data sheet contains products information. ASIX ELECTRONICS reserves rights modify product specification without notice. liability assumed result this product. rights under patent accompany sale product.
ASIX ELECTRONICS CORPORATION
NO.8, Hsin Rd., Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-563-9799
First Released Date: 01/31/2002
http://www.asix.com.tw
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
System Block Diagram
AX88655P
Switch Controller EEPROM
10/100/1000 Mbps PHYs
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
CONTENTS AX88655 OVERVIEW
GENERAL DESCRIPTION
AX88655 BLOCK DIAGRAM
CONNECTION DIAGRAM
DEFINITION
GMII/MII INTERFACE
2.1.1 GMII Interface Port 2.1.2 GMII Interface Port 2.1.3 GMII Interface Port 2.1.4 GMII Interface Port 2.1.5 GMII Interface Port
MISCELLANEOUS
FUNCTIONAL DESCRIPTION
INTRODUCTION PACKET FILTERING FORWARDING PROCESS ADDRESS ROUTING, LEARNING AGING PROCESS FULL DUPLEX 802.3X FLOW CONTROL HALF DUPLEX BACK PRESSURE CONTROL POLLING PORT-BASED QOS: PORT-PAIR
REGISTER DESCRIPTIONS
REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER 4.10 REGISTER 4.11 REGISTER 4.12 REGISTER 4.13 REGISTER 4.14 REGISTER 4.15 REGISTER 4.16 REGISTER 4.17 REGISTER 4.18 REGISTER 4.19 REGISTER 4.20 REGISTER 4.21 REGISTER ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
ELECTRICAL SPECIFICATION TIMING
ABSOLUTE MAXIMUM RATINGS GENERAL OPERATION CONDITIONS CHARACTERISTICS SPECIFICATIONS
5.4.1 X_IN Signal Timing. 5.4.2 Reset Signal Timing 5.4.3 GMII Transmit/Receive Signals Timing. 5.4.4 Mbps Transmit/Receive Signals Timing 5.4.5 Mbps Transmit/Receive Signals Timing
PACKAGE INFORMATION APPENDIX SYSTEM APPLICATIONS
AX88655 5-PORT SOHO HIGH TRAFFIC POWER USER SWITCH AX88655 5-PORT SMART SWITCH (DIP SWITCH CONFIGURABLE) AX88655 10/100MBPS ETHERNET BACKBONE AX88655 SUPER SERVER TRUNKING APPLICATION
APPENDIX DESIGN NOTE
USING CONNECTS MAC.
APPENDIX WEIGHT SETTING QOS. DEMONSTRATION CIRCUIT AX88658 SMART SWITCH
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
FIGURES
FIG-1 AX88655 BLOCK DIAGRAM FIG-2 AX88655 DIAGRAM.
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
AX88655 Overview
General Description
AX88655 Gigabit switch controller supports five 10/100/1000 Mbps ports wire-speed operation. AX88655 Gigabit switch controller provides five 10/100/1000 Ethernet ports with GMII/MII interface. each ports, AX88655 supports GMII (802.3ab) interface with full-duplex operation Gigabit speed, full- half-duplex operation 10/100 Mbps speed polls status PHYs with embedded MPU. Embedded 128K bytes SRAM packet buffer operates with internal 90MHz clock. efficient utilization packet buffer, there 1024 128-byte page-links totally buffer. device supports internal addresses which shared ports with embedded byte SSRAM. learning/routing engine implemented with two-way hash/linear algorithm reduce possibility routing collision. Basically AX88655 supports non-blocking wire speed forwarding rate Head-of-Line (HOL) blocking issue. AX88655 provides flow-control mechanisms avoid loss data: optional jamming based backpressure flow control half-duplex operation IEEE 802.3x full-duplex mode. support Quality Service (QoS), each output port priority queues their assignment based 802.1p priority field Port-Pair setting. Each output port retrieves frames from shared buffer based queuing sends them transmitting (Tx) FIFO.
AX88655 Block Diagram
GMII 10/100/1000 Routing /Learning Engine
GMII
10/100/1000 Address Look-up Table
GMII
10/100/1000 High Speed Switch Fabric Buffer Manager
GMII GMII
10/100/1000 10/100/1000
Packet Buffer General Purpose Interface (GPIO)
GPIO
Configuration Logic
EEPROM Interface
Fig-1 AX88655 Block Diagram
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Connection Diagram
VDD25 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 VDD33 /RST SYSCLK MDIO SDIO VDD25 GCLK /SYSCLK_EN /GCLK_EN SID4 SID3 SID2 SID1 SID0 VDD25 TX_EN4 TXD4[7] TXD4[6] TXD4[5] TXD4[4] TXD4[3] TXD4[2] TXD4[1] TXD4[0] TX_CLK4 VDD25 GTX_CLK4 RX_DV4 RX_CLK4 RXD4[7] RXD4[6] RXD4[5] RXD4[4] RXD4[3] RXD4[2] VDD25 VDD25 VDD25 VSS25 VDD25 CRS0 COL0 RXD0[0] RXD0[1] RXD0[2] RXD0[3] RXD0[4] RXD0[5] RXD0[6] RXD0[7] RX_CLK0 RX_DV0 GTX_CLK0 VDD25 TX_CLK0 TXD0[0] TXD0[1] TXD0[2] TXD0[3]
TXD0[4] TXD0[5] TXD0[6] TXD0[7] TX_EN0 VDD25 VDD25 VDD33 X_IN X_OUT AVBB25 AVDD25A AVSS25A FILTER AVSS25D AVDD25D CRS1 COL1 RXD1[0] RXD1[1] RXD1[2] RXD1[3] RXD1[4] RXD1[5] RXD1[6] RXD1[7] RX_CLK1 RX_DV1 GTX_CLK1 VDD25 TX_CLK1 TXD1[1] TXD1[1] TXD1[2] TXD1[3] TXD1[4]
Fig-2 AX88655 Diagram
ASIX ELECTRONICS CORPORATION
AX88655P 10/100/1000Mbps Ethernet Switch Controller
RXD4[1] RXD4[0] COL4 CRS4 VDD25 TX_EN3 TXD3[7] TXD3[6] TXD3[5] TXD3[4] TXD3[3] TXD3[2] TXD3[1] TXD3[0] TX_CLK3 VDD25 GTX_CLK3 RX_DV3 RX_CLK3 RXD3[7] RXD3[6] RXD3[5] RXD3[4] RXD3[3] RXD3[2] RXD3[1] RXD3[0] COL3 CRS3 VDD25 VSS25 TX_EN2 TXD2[7] TXD2[6] TXD2[5] TXD2[4] TXD2[3] TXD2[2] TXD2[1] TXD2[0] TX_CLK2 VDD25 GTX_CLK2 RX_DV2 RX_CLK2 RXD2[7] RXD2[6] RXD2[5] RXD2[4] RXD2[3] RXD2[2] RXD2[1] RXD2[0] COL2 CRS2 VDD25 VSS25 TX_EN1 TXD1[7] TXD1[6] TXD1[5]
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Descriptions
Definition
following terms describe AX88655 pin-out: names with suffix asserted low. following abbreviations used following Tables.
Input Output Input/Output Open Drain
Pull Pull Down Power
GMII/MII Interface
2.1.1 GMII Interface Port Signal Name
GTX_CLK0
Description
125MHz Clock Output: continuous clock output giga-PHY operating 1000BASE-T. That timing reference TX_EN0 TXD0[7:0] Transmit Enable: When TX_EN0 asserted, data TXD0[7:0] transmitted onto PHY. TX_EN0 synchronous GTX_CLK0 1000BASE-T mode synchronous TX_CLK0 10/100BASE-T mode. Transmit Data: Synchronous rising GTX_CLK0 1000BASE-T mode. synchronous rising edge TX_CLK0 10/100BASE-T mode. Transmit Clock Input: TX_EN0 TXD0[3:0] synchronous rising edge this clock 10/100BASE-T mode. Collision Detect: Active high indicate that there collision occurred half duplex mode. full duplex mode COL0 always low. Carrier Sense: Active high there carrier medium. half duplex mode CRS0 also asserted during transmission asynchronous clock. Receive Data Valid: Active high indicate that data presented RXD0[7:0] valid synchronous RX_CLK0. Receive Clock Input: 125, running 1000/100/10 BASE-T mode respectively. RX_DV0 RXD0[7:0] synchronous rising edge this clock. Receive Data: Data received presented RXD0 synchronous RX_CLK0. RXD0[3:0] valid 10/100/1000BASE-T RXD[7:4] valid only 1000BASE-T modes.
TX_EN0
TXD0[7:0]
TX_CLK0 COL0 CRS0
I/PD I/PD I/PD
RX_DV0 RX_CLK0
RXD0[7:0]
I/PD
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
2.1.2 GMII Interface Port Signal Name
GTX_CLK1 TX_EN1 TXD1[7:0] TX_CLK1 COL1 CRS1 RX_DV1 RX_CLK1 RXD1[7:0] I/PD I/PD I/PD I/PD
Description
125MHz Clock Output: Please references section 2.1.1. Transmit Enable: Please references section 2.1.1. Transmit Data: Please references section 2.1.1. Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1.
2.1.3 GMII Interface Port Signal Name
GTX_CLK2 TX_EN2 TXD2[7:0] TX_CLK2 COL2 CRS2 RX_DV2 RX_CLK2 RXD2[7:0] I/PD I/PD I/PD I/PD
Description
125MHz Clock Output: Please references section 2.1.1. Transmit Enable: Please references section 2.1.1. Transmit Data: Please references section 2.1.1. Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1.
2.1.4 GMII Interface Port Signal Name
GTX_CLK3 TX_EN3 TXD3[7:0] TX_CLK3 COL3 CRS3 RX_DV3 RX_CLK3 RXD3[7:0] I/PD I/PD I/PD I/PD
Description
125MHz Clock Output: Please references section 2.1.1. Transmit Enable: Please references section 2.1.1. Transmit Data: Please references section 2.1.1. Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1.
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
2.1.5 GMII Interface Port Signal Name
GTX_CLK4 TX_EN4 TXD4[7:0] TX_CLK4 COL4 CRS4 RX_DV4 RX_CLK4 RXD4[7:0] I/PD I/PD I/PD I/PD
Description
125MHz Clock Output: Please references section 2.1.1. Transmit Enable: Please references section 2.1.1. Transmit Data: Please references section 2.1.1. Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1.
Miscellaneous
Signal Name
X_IN X_OUT GCLK SYSCLK /GCLK /SYSCLK_EN FILTER /RST MDIO SDIO SID[4:0]
I/PU I/PU I/O/PU I/O/PU I/O/PU I/PD I/PD I/PD I/UP I/UP I/O/PU
156, 155, 154, 153,
Description
Crystal 27MHz Input: This clock source PLL. will generate 90MHz internal clock. Crystal 27MHz Output: This should floating with single-ended external clock. 125MHz Input: 125MHz Clock GMII System Clock Input: 90MHz Clock switch kernel GCLK Enable: GCLK; Reserved System Clock Enable: SYSCLK; 90MHz generated internal circuit from X_IN clock source. FILTER: internal circuit use. Reset: Active Station Management Data In/Out: Management Data Input Output. Station Management Data Clock Out: Management Clock. EEPROM Data In/Out: EEPROM Serial Data Input Output. EEPROM Data Clock In/Out: EEPROM Serial Clock. (Note: output embedded active; otherwise input pin) Switch identify switch PHYs with this Default "00011b".
GPIO[4:0]
General Purpose I/O: GPIOs programmed special application. (Note: function released user normally. Please contact with ASIX directly requirement)
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Connect. 167, 172, 173, 174, 175, 183, 184, 189, 190, 191, 192, 196, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 210, 211, 216, 217, 218, 219, 223, 225, 226, 227, 228, 229, 230, 231, 232, 233, 171, 3.3V +/-5% Supply Voltage. 2.5V +/-5% Supply Voltage. 112, 124, 139, 151, 162, 182, 197, 209, 224, 236, Ground 83,96, 110, 123, 137, 150, 157, 159, 160, 167, 169, 181, 185, 186, 187, 188, 193, 194, 195, 208, 212, 213, 214, 215, 220, 221, 222, 235, Ground 2.5V +/-5% Supply Voltage PLL. Ground 2.5V +/-5% Supply Voltage PLL. Ground
VDD33 VDD25
AVBB25 AVDD25A AVSS25A AVDD25D AVSS25D
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Functional Description
Introduction
general, AX88655 device highly integrated Layer switch. supports five 10/100/1000 ports with on-chip MACs. also supports integrated switching logic, packet queuing memory packet storage memory. AX88655 capable routing-and-forwarding packets wire speed ports regardless packet size. cost solution five ports Gigabit Ethernet backbone switch design. interface required; After power reset, AX88655 provide auto load configuration setting function through wire serial EEPROM interface access external EEPROM device, AX88655 easily configured support trunking, QoS, IEEE 802.3x flow control threshold setting, broadcast storm control .etc functions. overview AX88658's major functional blocks shown Fig-1.
Packet Filtering Forwarding Process
switch simple store-and-forward algorithm packet switching method. After receives incoming packets, packets will stored embedded memory first. AX88655 searches Address-Lookup Table with packet. packet will forward destination port, this packet's hits; otherwise this packet will broadcasted. course, only good packets will forward. Conditions good packets below: correct. Bytes PacketLength 1518/1522 Bytes local packets, That local packets SourcePort DestinationPort. PAUSE other control packets. same trunking group.
Address Routing, Learning Aging Process
switch supports entries switching. Two-way dynamic address learning performed each good unicast packet completely received. linear/XOR hash algorithm static address learning achieved EEPROM configuration. other hand, routing process performed whenever packet's captured. result, packet going broadcast. Only learned address entries scheduled aging machine. station does transmit packet period time, belonging address will kicked from address table. aging time program automatically through EEPROM configuration. (Default value seconds)
Full Duplex 802.3x Flow Control
full duplex mode, AX88655 supports standard flow control mechanism defined IEEE 802.3x standard. enables stopping remote node transmissions PAUSE frame information interaction. When space packet buffer less than initialization setting threshold value, AX88655 will send PAUSE-ON packet with pause time equal "xFFF" stop remote node transmission. then AX88655 will send PAUSE-OFF packet with pause time equal zero inform remote node retransmit packet enough space receive packets.
Half Duplex Back Pressure Control
half duplex mode, AX88655 provide backpressure control mechanism avoid dropping packets during network conjection situation. When space packet buffer less than initialization setting threshold value, AX88655 will send pattern input port when senses incoming packet, thus force collision make remote node transmission back will effectively avoid dropping packets. then AX88655 will send packet more enough space receive packet.
Polling
AX88655 supports management through serial MDIO/MDC interface. That AX88655 access related ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
register PHYs MDIO/MDC interface after power reset. AX88655 will periodically continuously poll update link status link partner's ability which include speed, duplex mode, 802.3x flow control capable status connected devices through MDIO/MDC serial interface.
Port-Based QoS: Port-Pair
AX88655 provides Port-Pairs bandwidth management. Users assign ports Port-Pair with internal registers basically. packets will high priority queue Port-Pair when send packets each other. That ports each Port-Pair will obtain more bandwidth than other ports when congestion. addition, port highest priority port All_Bit Port-Pair active. That user assign format Port-Pair OnePort-to-All every packets OnePort will high priority transmit queue other ports.
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Register Descriptions
Registers Table Summary: Address Default Reserved 0000 Reserved 0000 Reserved RxFlowCtrl[4:0] Reserved TxFlowCtrl[4:0] 0000 Reserved 0000 Reserved 0000 Reserved 0000 Reserved 0000 Reserved 1215 Reserved 7777 Reserved 7777 PortPair1[7:0] PortPair0[7:0] 0000 PortPair3[7:0] PortPair2[7:0] 0000 LowQueueWeight[3:0] Reserved lw_LowQueueDiscardLimit [9:0] 1060 HighQueueWeight[3:0] MaxStorm lw_HighQueueDiscardLimit [9:0] 1060 Res. Reserved Reserved QoS[1:0] Res. 8880 Reserved MaxAge[8:0] 1865 Reserved Trunk30[2:0] Reserved 00C0 Reserved LowQueueFlowCtrlMark[9:0] 0010 MaxJam[5:0] HighQueueFlowCtrlMark[9:0] 2810 Reserved hw_LowQueueDiscardLimit[9:0] 0070 Reserved hw_HighQueueDiscardLimit[9:0] 0070 Notes: word "Reserved" "Res." above table. Notes: Care must taken that "Reserved" registers should keep default value always. Change reserved value resulting unpredictable conditions. Notes: registers accessed internal only. will read configuration table, located EEPROM somewhere address, programs above registers when every time power after system reset.
Register
15:0 DESCRIPTION Reserved
Register
15:0 DESCRIPTION Reserved
Register
15:13 DESCRIPTION Reserved ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
12:8 FlowCtrlEnable MAC's receive part Port[4:0] configured internal 8051 identify PAUSE frames receive part identify PAUSE frames. That PauseTimer will active. Reserved FlowCtrlEnable MAC's transmit part Port[4:0] configured internal 8051 send PAUSE frames send PAUSE frames full-duplex when packet buffer empty. send frames half-duplex when packet buffer empty.
Register
15:0 DESCRIPTION Reserved
Register
15:0 DESCRIPTION Reserved
Register
15:0 DESCRIPTION Reserved
Register
15:0 DESCRIPTION Reserved
Register
15:0 DESCRIPTION Reserved
Register
15:0 DESCRIPTION Reserved
4.10 Register
15:0 DESCRIPTION Reserved
4.11 Register
14:12 DESCRIPTION All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
10:8 All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high
4.12 Register
14:12 10:8 DESCRIPTION All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high All_Bit PortPair when QoS[0] high Port_ID PortPair when QoS[0] high
4.13 Register
15:12 11:10 DESCRIPTION WeightForLowQue: Weight priority queues when active (see Appendix Reserved LowWaterMark priority queues when drop packets
4.14 Register
15:12 11:10 DESCRIPTION WeightForHighQue: Weight high priority queues when active (see Appendix Maximum number broadcast frames that accumulated each input frame buffer. disable broadcast storm control frames frames frames LowWaterMark high priority queues when drop packets
4.15 Register
DESCRIPTION Reserved 802.3x Flow control frame recognition control check control frame address addition control type field check only control type field Setting maximum length packet that received 1518 byte 1522 byte Reserved Software Reset (Only reset switch kernel) active disable ASIX ELECTRONICS CORPORATION
12:11
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Back-off algorithm selection disable. Device will perform IEEE standard exponential back algorithm when collision occurs. enable. When collisions occur, MACs will back slots. stop generate patterns after some collision that defined MaxJam[5:0] Never stop back-pressure Reserved selection disable function Port-Pair Priority algorithm 802.1p AgingEnable Switch Table Entry Aging Control. Only dynamically learned addresses will aged. explicit entries will age. aging time programmed register disable. table aging process disabled. enable. table aging process enabled hardware process ages every dynamically learned table entry. Hash algorithm selection mapping Linear mapping Reserved
4.16 Register
15:9 DESCRIPTION Reserved MaxAge. This seven-bit register containing unsigned integer determining address-aging timer. resolution normal address aging MaxAge[8:0]) FreqencyOfSystemClock. Default value seconds.
4.17 Register
15:13 12:10 DESCRIPTION Reserved Trunking selection Port[3:0] 000: disable trunking 001: disable trunking 010: 2-Port Trunking Port[1:0] 011: 2-Port Trunking Port[1:0] 100: 2-Port Trunking Port[3:2] 101: 4-Port Trunking 110: 2-Port Trunkings Port[3:2] Port[1:0] 111: 4-Port Trunking Reserved
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
4.18 Register
15:10 DESCRIPTION Reserved LowWaterMarkForFlowCtrl. This ten-bit register containing unsigned integer transmit queues whether generate PAUSE-ON not.
4.19 Register
15:10 DESCRIPTION MaxJam. This six-bit register containing unsigned integer determining counter whether generate not. HighWaterMarkForFlowCtrl. This ten-bit register containing unsigned integer transmit queues whether generate PAUSE-OFF not.
4.20 Register
15:10 DESCRIPTION Reserved HighWaterMark priority queues when drop packets
4.21 Register
15:10 DESCRIPTION Reserved HighWaterMark high priority queues when drop packets
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
ELECTRICAL SPECIFICATION TIMING
Absolute Maximum Ratings
Description Units Operating Temperature Storage Temperature +150 Supply Voltage -0.3 +4.0 Input Voltage -0.3 Vdd+0.5 Output Voltage Vout -0.3 Vdd+0.5 Lead Temperature (soldering seconds maximum) +220 Note: Stress above those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Ratings conditions extended period, adversely affect device life reliability
General Operation Conditions
Description Operating Temperature Supply Voltage +3.0 +3.6 Units
Characteristics
(Vdd=3.0V 3.6V, Vss=0V, Ta=0°C 70°C) Description Input Voltage High Input Voltage Output Voltage High Output Voltage Input Leakage Current (Note Input Leakage Current (Note Output Leakage Current Description Power Consumption Iil1 Iil1 Vss-0.3 Vdd+0.5 Units Units
Note: input pins without pull pull high. Those pins been pull pull high.
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
specifications
5.4.1 X_IN Signal Timing
Thigh
X_IN
Tcyc Tlow
Symbol
Tcyc Thigh Tlow Tr/Tf CYCLE TIME HIGH TIME TIME SLEW RATE
Description
Typ.
Units
5.4.2 Reset Signal Timing SYSCLK /RST
Symbol
Trst Reset pulse width
Description
Typ.
Units SYSCLK
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
5.4.3 GMII Transmit/Receive Signals Timing GTX_CLK TX_EN
TXD[7:0]
Symbol
Description GTX_CLK Clock Cycle Time GTX_CLK Clock High Time TX_EN data setup GTX_CLK rising edge TX_EN data hold from GTX_CLK rising edge
7.998
Typ.
8.002
Units
RX_CLK
RX_DV
RXD[7:0]
Symbol
Description RX_CLK Clock Cycle Time RX_CLK Clock High Time RX_DV data setup RX_CLK rising edge RX_DV data hold from RX_CLK rising edge
7.998
Typ.
8.002
Units
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
5.4.4 Mbps Transmit/Receive Signals Timing TX_CLK TX_EN
TXD[3:0]
Symbol
Description TX_CLK Cycle Time TX_CLK High Time TX_CLK rising edge TX_EN Delay TX_CLK rising edge Delay
39.996 7.440 3.410
Typ.
40.004 21.760 13.320
Units
RX_CLK
RX_CRS RX_DV
RXD[3:0]
Symbol
Description RX_CLK Clock Cycle Time RX_CLK Clock High Time RX_CLK rising edge RX_DV RX_CRS Delay RX_CLK rising edge Delay
39.996
Typ.
40.004 13.0 13.0
Units
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
5.4.5 Mbps Transmit/Receive Signals Timing TX_CLK TX_EN
TXD[3:0]
Symbol
Description TX_CLK Cycle Time TX_CLK High Time TX_CLK rising edge TX_EN Delay TX_CLK rising edge Delay
399.96 7.440 3.410
Typ.
400.04 21.760 13.320
Units
RX_CLK
RX_CRS RX_DV
RXD[3:0]
Symbol
Description RX_CLK Clock Cycle Time RX_CLK Clock High Time RX_CLK rising edge RX_DV RX_CRS Delay RX_CLK rising edge Delay
399.
Typ.
400. 13.0 13.0
Units
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
PACKAGE INFORMATION
SYMBOL MIN.
0.45 0.25
MILIMETER
0.16 28.00 28.00 30.6 30.6 0.75
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Appendix System Applications
AX88655 5-Port SOHO high traffic power user switch
Port Configuration From
AX88655P
Switch Controller
SEEPROM save Configuration
GMII
Quad GMII GMII PHYs
AX88655 5-Port Smart switch (DIP switch configurable)
LEDs General Serial Output GPIO Configuration Serial GPIO
AX88655P
Switch Controller EEPROM
10/100/1000Mbps PHYs
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
AX88655 10/100Mbps Ethernet Backbone
5-port Gigabit switch
AX88655P
Switch Controller
16*10/100Mbps +2*1000Mbps Ethernet Switch Router
16*10/100Mbps +2*1000Mbps Ethernet Switch
Using Gigabit Ports Up-link Trunking form 12.8G Non-blocking backbone
AX88655 Super Server Trunking Application
5-port Gigabit switch
AX88655
Switch Controller
Super Server with Gigabit Ethernet Cards Trunking
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Appendix Design Note
Using connects Using interface connect type device application AX88655 illustrated bellow.
25MHz Clock
COL0 TX_EN0 TX_CLK0 TXD0[3:0]
RX_DV RX_CLK RXD[3:0] RX_ER TX_EN TX_CLK TXD[3:0] TX_ER
CRS0 RX_DV0 RX_CLK0 RXD0[3:0]
AX88655 Switch
AX88195
Note: needs full-duplex mode. Care must taken that receive side enough setup and/or hold time Some kind with embedded also refer this example
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
Appendix Weight Setting
Service Ratio (High Low) WeightForHighQue[3:0] 4'b0100 4'b0100 4'b0110 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 4'b1001 4'b1010 4'b1011 4'b1100 4'b1101 4'b1110 4'b1111 WeightForLowQue[3:0] 4'b0100 4'b0010 4'b0010 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001 4'b0001
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch Demonstration Circuit AX88658 Smart Switch
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch Application.
VDD18_2 VDD18_1 VDD25_2 VDD25_2 VDD33 VDD25 VDD33 VDD33 MDIO RST#_P34 25M_P4 MDIO RST#_P34 25M_P3 MDIO RST#_P12 25M_P2 MDIO RST#_P12 25M_P1 VDD33 VDD33 OSC_CKT 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4 ROM_CKT ROM_CKT VDD18_2 VDD18_1 VDD33 RST_CTL# RST_CTL# RST#_SW RST#_P0 RST#_P12 RST#_P34 RST_CTL# RST#_SW RST#_P0 RST#_P12 RST#_P34 VDD25 25MHZ MDIO PHY_RST# 25MHZ POWER_CKT POWER_CKT
GCLK
SDIO
RST#_SW
SYSCLK
VDD25_2
GCLK
VDD33
SYSCLK
RESET#
VDD33
GSW_CKT GCLK
VDD25_2
MDIO
MDIO
SDIO
OSC_CKT
SYSCLK
SDIO
VDD18_2 VDD25 VDD18 VDD25 PORT4 GPHY4 TX_EN4 TXD4[0.7] TX_CLK4 GTX_CLK4 RX_RV4 RX_CLK4 RXD4[0.7] COL4 CRS4 TX_EN4 TXD4[0.7] TX_CLK4 GTX_CLK4 RX_DV4 RX_CLK4 RXD4[0.7] COL4 CRS4
TX_EN TXD[0.7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0.7]
MDIO PHY_RST#
VDD18_2 VDD25 VDD18 VDD25 PORT3 GPHY3 TX_EN3 TXD3[0.7] TX_CLK3 GTX_CLK3 RX_RV3 RX_CLK3 RXD3[0.7] COL3 CRS3 VDD18_1 VDD25 VDD18 VDD25 VDD18 VDD25 PORT0 GPHY0 MDIO RST#_P0 25M_P0 MDIO PORT2 GPHY2 RXD[0.7] RX_CLK RX_DV GTX_CLK TX_CLK TXD[0.7] TX_EN CRS0 COL0 RXD0[0.7] RX_CLK0 RX_DV0 GTX_CLK0 TX_CLK0 TXD0[0.7] TX_EN0 CRS0 COL0 RXD0[0.7] RX_CLK0 RX_DV0 GTX_CLK0 TX_CLK0 TXD0[0.7] TX_EN0 TX_EN2 TXD2[0.7] TX_CLK2 GTX_CLK2 RX_RV2 RX_CLK2 RXD2[0.7] COL2 CRS2 TX_EN2 TXD2[0.7] TX_CLK2 GTX_CLK2 RX_DV2 RX_CLK2 RXD2[0.7] COL2 CRS2 TX_EN3 TXD3[0.7] TX_CLK3 GTX_CLK3 RX_DV3 RX_CLK3 RXD3[0.7] COL3 CRS3
TX_EN TXD[0.7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0.7]
MDIO PHY_RST# 25MHZ
VDD18_2 VDD25
GTX_CLK1
RXD1[0.7]
PHY_RST# 25MHZ
TXD1[0.7]
RX_CLK1
TX_CLK1
RX_DV1
TX_EN1
CRS1
COL1
TX_EN TXD[0.7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0.7]
MDIO PHY_RST#
25MHZ
VDD18_2 VDD25 VDD18 VDD25 PORT1 GPHY1 TX_EN1 TXD1[0.7] TX_CLK1 GTX_CLK1 RX_DV1 RX_CLK1 RXD1[0.7] COL1 CRS1
GSW_CKT
TX_EN TXD[0.7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0.7]
ASIX ELECTRONICS CORPORATION Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch ROOT CKT. Size Date: Document Number GSW_ROOT.SCH Thursday, March 2002 Sheet
ASIX ELECTRONICS
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
RXD[0.7] RX_CLK RX_DV TX_CLK RXD[0.7] RX_CLK RX_DV TX_CLK
GTX_CLK TXD[0.7] TX_EN MDIO PHY_RST# 25MHZ VDD25 VDD18
GTX_CLK TXD[0.7] TX_EN MDIO RESET# 25M_IN VDD25 VDD18
00110
PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k VDD_O
VDD_O 4.7K
PHYADD0 AN_EN
VDD_O
RESET# OPTION VDD_O DUPLEX SPEED1 SPEED VDD_O VDD_C PHYADD3 PHYADD2 VDD_O PHYADD1 PHYADD0 VDD_C AN_EN DUPLEX SPEED1 SPEED
DUPLEX Link 1000 Link Link
Activity
VDD_O VDD_C
VDD_O
VDD_O
VDD_C
IO_VDD CORE_VDD VDD_SEL_STRAP /RESET /TRST IO_VDD CORE_VDD RESERVED IO_VDD CORE_VDD PHYADDR3_STRAP PHYADDR2_STRAP IO_VDD PHYADDR1_STRAP PHYADDR0_STRAP /DUPLEX_LED CORE_VDD AN_EN_STRAP /LINK1000_LED LINK100_LED /DUPLEX_STRAP LINK10_LED /SPEED1_STRAP ACTIVITY_LED /SPEED_STRAP TX_TCLK IO_VDD /INTERRUPT RESERVED NON_IEEE_STRAP
DP83865AVH RX_VDD25 0.1uF MDID_N MDID_P RX_VDD MDIC_N MDIC_P RX_VDD MDIB_N MDIB_P RX_VDD MDIA_N MDIA_P RX_VDD RX_VDD MDID_N MDID_P VDD_C MDIC_N MDIC_P VDD_C MDIB_N MDIB_P VDD_C MDIA_N MDIA_P VDD_C VDD_C MDID_N MDID_P RX_VDD25 0.1uF MDIC_N MDIC_P RX_VDD25 0.1uF MDIB_N MDIB_P RX_VDD25 0.1uF MDIA_N MDIA_P 1000pF 0.1uF 49.9 49.9 0.1uF 0.1uF 0.1uF 49.9 49.9 0.1uF 0.1uF 49.9 49.9 0.1uF TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD424HST1041 0.01uF/2KV MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX424 MDI_DMDI_D+ MDI_CMDI_C+ MDI_BMDI_B+ MDI_AMDI_A+ MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ JACK1 0.1uF 49.9 49.9 0.1uF
RXD[0.7] RX_DV RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0
4.7K VDD_O
VDD_C VDD_O
RX_CLK TX_CLK
TXD7 TXD6 TXD5 TXD4 IO_VDD TXD3 TXD2 CORD_VDD TXD1 TXD0 IO_VDD GTX_CLK MDIO IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD CORD_VDD MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD PGM_VDD CORD_VDD BG_VDD BG_REF
VDD_O 4.7K TX_EN VDD_C
RX_ER IO_VDD RX_DV RXD7 RXD6 RXD5 CORD_VDD RXD4 RXD3 RXD2 IO_VDD RXD1 RXD0 RX_CLK IO_VDD TX_CLK TX_ER TX_EN CORD_VDD
RJ45_A
VDD_O VDD_O VDD_C PHYADD4 RX_VDD25 VDD_C RX_VDD25
TXD7 TXD6 TXD5 TXD4 VDD_O TXD3 TXD2 VDD_C TXD1 TXD0 VDD_O
TXD[0.7] 4.7K MDIO VDD_O VDD_O 1.5K 0.1uF 22uF
9.76K
GTX_CLK VDD_O
1.5K
F.B.
VDD_C
Option
25M_IN 4.7K
VDD_O VDD25 VDD18 F.B. VDD_C F.B. VDD_O 1000pF 0.1uF 0.1uF
RX_VDD25 1000pF 0.1uF 0.1uF
100uF/16V 0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
100uF/16V 0.1uF
1000pF
100uF/16V 0.1uF
ASIX ELECTRONICS CORPORATION 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Size Date: Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch Port G'PHY CKT. Document Number GPHY0.SCH Thursday, March 2002 Sheet
100uF/16V 0.1uF
1000pF
100uF/16V 0.1uF
ASIX ELECTRONICS CORPORATION
SHIELD
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
RXD[0.7] RX_CLK RX_DV TX_CLK RXD[0.7] RX_CLK RX_DV TX_CLK
GTX_CLK TXD[0.7] TX_EN MDIO PHY_RST# 25MHZ VDD25 VDD18
GTX_CLK TXD[0.7] TX_EN MDIO RESET# 25M_IN
01000
PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
VDD25 VDD18 VDD_O
VDD_O
4.7K PHYADD0 AN_EN RESET# OPTION VDD_O DUPLEX SPEED1 SPEED VDD_O VDD_C PHYADD3 PHYADD2 VDD_O PHYADD1 PHYADD0 VDD_C AN_EN DUPLEX SPEED1 SPEED VDD_O
DUPLEX Link 1000 Link Link
Activity
VDD_O VDD_C
VDD_O
VDD_O
VDD_C
IO_VDD CORE_VDD VDD_SEL_STRAP /RESET /TRST IO_VDD CORE_VDD RESERVED IO_VDD CORE_VDD PHYADDR3_STRAP PHYADDR2_STRAP IO_VDD PHYADDR1_STRAP PHYADDR0_STRAP /DUPLEX_LED CORE_VDD AN_EN_STRAP /LINK1000_LED LINK100_LED /DUPLEX_STRAP LINK10_LED /SPEED1_STRAP ACTIVITY_LED /SPEED_STRAP TX_TCLK IO_VDD /INTERRUPT RESERVED NON_IEEE_STRAP
DP83865AVH RX_VDD25 0.1uF MDID_N MDID_P RX_VDD MDIC_N MDIC_P RX_VDD MDIB_N MDIB_P RX_VDD MDIA_N MDIA_P RX_VDD RX_VDD MDID_N MDID_P VDD_C MDIC_N MDIC_P VDD_C MDIB_N MDIB_P VDD_C MDIA_N MDIA_P VDD_C VDD_C MDID_N MDID_P RX_VDD25 0.1uF MDIC_N MDIC_P RX_VDD25 0.1uF MDIB_N MDIB_P RX_VDD25 0.1uF MDIA_N MDIA_P 1000pF 0.1uF 49.9 49.9 0.1uF 0.1uF 0.1uF 49.9 49.9 0.1uF 0.1uF 49.9 49.9 0.1uF TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD424HST1041 0.01uF/2KV MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX424 MDI_DMDI_D+ MDI_CMDI_C+ MDI_BMDI_B+ MDI_AMDI_A+ MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ JACK2 0.1uF 49.9 49.9 0.1uF
RXD[0.7] RX_DV RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0
4.7K VDD_O
VDD_C VDD_O
RX_CLK TX_CLK
TXD7 TXD6 TXD5 TXD4 IO_VDD TXD3 TXD2 CORD_VDD TXD1 TXD0 IO_VDD GTX_CLK MDIO IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD CORD_VDD MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD PGM_VDD CORD_VDD BG_VDD BG_REF
VDD_O 4.7K TX_EN VDD_C
RX_ER IO_VDD RX_DV RXD7 RXD6 RXD5 CORD_VDD RXD4 RXD3 RXD2 IO_VDD RXD1 RXD0 RX_CLK IO_VDD TX_CLK TX_ER TX_EN CORD_VDD
RJ45_A
VDD_O VDD_O VDD_C PHYADD4 RX_VDD25 VDD_C RX_VDD25
TXD7 TXD6 TXD5 TXD4 VDD_O TXD3 TXD2 VDD_C TXD1 TXD0 VDD_O
TXD[0.7] 4.7K
9.76K
GTX_CLK VDD_O MDIO
1.5K
22uF
F.B.
VDD_C
VDD_O VDD_O 1.5K 0.1uF
OPTION
25M_IN 4.7K
VDD_O VDD25 VDD18 C103 C105 C106 F.B. 1000pF C104 C107 VDD_C C108 1000pF C109 0.1uF C110 0.1uF F.B. VDD_O 1000pF 0.1uF 0.1uF
RX_VDD25 1000pF 0.1uF 0.1uF
100uF/16V 0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C100 0.1uF
C101 0.1uF
C102 0.1uF
100uF/16V 0.1uF
1000pF
100uF/16V 0.1uF
C111 0.1uF
C112 0.1uF
C113 0.1uF
C114 0.1uF
C115 0.1uF
C116 0.1uF
C117 0.1uF
C118 0.1uF
C119 0.1uF
C120 0.1uF
C121 0.1uF
C122 Title 0.1uF Size Date:
ASIX ELECTRONICS CORPORATION AX88655 5-Port 10/100/1000BASE-T EtherNet Switch Port G'PHY CKT. Document Number GPHY1.SCH Thursday, March 2002 Sheet
100uF/16V 0.1uF
100uF/16V 0.1uF
ASIX ELECTRONICS CORPORATION
SHIELD
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
RXD[0.7] RX_CLK RX_DV TX_CLK RXD[0.7] RX_CLK RX_DV TX_CLK
GTX_CLK TXD[0.7] TX_EN MDIO PHY_RST# 25MHZ VDD25 VDD18
GTX_CLK TXD[0.7] TX_EN MDIO RESET# 25M_IN VDD25 VDD18 VDD_O
01001
PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k VDD_O
4.7K PHYADD0 AN_EN RESET# OPTION VDD_O DUPLEX SPEED1 SPEED R100 VDD_O
DUPLEX Link 1000 Link Link
Activity
VDD_O VDD_C PHYADD3 PHYADD2 VDD_O PHYADD1 PHYADD0 VDD_C AN_EN DUPLEX SPEED1 SPEED
VDD_O VDD_C
VDD_O
VDD_O
VDD_C
DP83865AVH RX_VDD25 C123 0.1uF MDID_N MDID_P RX_VDD MDIC_N MDIC_P RX_VDD MDIB_N MDIB_P RX_VDD MDIA_N MDIA_P RX_VDD RX_VDD MDID_N MDID_P VDD_C MDIC_N MDIC_P VDD_C MDIB_N MDIB_P VDD_C MDIA_N MDIA_P VDD_C VDD_C MDID_N MDID_P RX_VDD25 C126 0.1uF MDIC_N MDIC_P RX_VDD25 C129 0.1uF MDIB_N MDIB_P RX_VDD25 C133 0.1uF MDIA_N MDIA_P C137 1000pF C134 0.1uF R118 49.9 C135 R119 49.9 0.1uF C136 0.1uF C130 0.1uF R113 49.9 C131 R114 49.9 0.1uF C127 0.1uF R106 49.9 C128 R107 49.9 0.1uF TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD424HST1041 C132 0.01uF/2KV MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX424 R108 MDI_DMDI_D+ R110 MDI_CMDI_C+ R111 MDI_BMDI_B+ R115 MDI_AMDI_A+ MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ JACK3 C124 0.1uF R101 49.9 C125 R102 49.9 0.1uF
RXD[0.7] RX_DV RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 R105
R103 R104
4.7K VDD_O
VDD_C R109 VDD_O
RX_CLK TX_CLK
R112 R116 R117
VDD_O 4.7K TX_EN VDD_C
TXD7 TXD6 TXD5 TXD4 IO_VDD TXD3 TXD2 CORD_VDD TXD1 TXD0 IO_VDD GTX_CLK MDIO IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD CORD_VDD MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD PGM_VDD CORD_VDD BG_VDD BG_REF
RX_ER IO_VDD RX_DV RXD7 RXD6 RXD5 CORD_VDD RXD4 RXD3 RXD2 IO_VDD RXD1 RXD0 RX_CLK IO_VDD TX_CLK TX_ER TX_EN CORD_VDD
IO_VDD CORE_VDD VDD_SEL_STRAP /RESET /TRST IO_VDD CORE_VDD RESERVED IO_VDD CORE_VDD PHYADDR3_STRAP PHYADDR2_STRAP IO_VDD PHYADDR1_STRAP PHYADDR0_STRAP /DUPLEX_LED CORE_VDD AN_EN_STRAP /LINK1000_LED LINK100_LED /DUPLEX_STRAP LINK10_LED /SPEED1_STRAP ACTIVITY_LED /SPEED_STRAP TX_TCLK IO_VDD /INTERRUPT RESERVED NON_IEEE_STRAP
RJ45_A
PHYADD4 RX_VDD25
VDD_C RX_VDD25
TXD7 TXD6 TXD5 TXD4 VDD_O TXD3 TXD2 VDD_C TXD1 TXD0 VDD_O
VDD_O
VDD_O VDD_C
TXD[0.7] R121 4.7K
R120
9.76K
GTX_CLK VDD_O MDIO
R122 R124
1.5K
R123 C139 C138 22uF
F.B.
VDD_C
VDD_O VDD_O R125 1.5K 0.1uF
Option
25M_IN R126 4.7K
VDD_O C140 100uF/16V VDD25 C145 100uF/16V VDD18 C164 100uF/16V C166 0.1uF C167 1000pF F.B. C165 100uF/16V C168 0.1uF VDD_C C147 0.1uF C148 1000pF F.B. C146 100uF/16V C149 0.1uF VDD_O C150 1000pF C151 0.1uF C152 0.1uF C153 0.1uF C154 0.1uF C155 0.1uF C156 0.1uF C157 0.1uF C158 0.1uF C159 C141 0.1uF
RX_VDD25 C142 1000pF C143 0.1uF C144 0.1uF
C160 0.1uF
C161 0.1uF
C162 0.1uF
C163 0.1uF
0.1uF
ASIX ELECTRONICS CORPORATION C169 1000pF C170 0.1uF C171 0.1uF C172 0.1uF C173 0.1uF C174 0.1uF C175 0.1uF C176 0.1uF C177 0.1uF C178 0.1uF C179 0.1uF C180 0.1uF C181 0.1uF C182 0.1uF C183 0.1uF Size Date: Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch Port G'PHY CKT. Document Number GPHY2.SCH Thursday, March 2002 Sheet
ASIX ELECTRONICS CORPORATION
SHIELD
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
RXD[0.7] RX_CLK RX_DV TX_CLK RXD[0.7] RX_CLK RX_DV TX_CLK
GTX_CLK TXD[0.7] TX_EN MDIO PHY_RST# 25MHZ
GTX_CLK TXD[0.7] TX_EN MDIO RESET# 25M_IN VDD25 VDD18 VDD_O
01010
PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED R127 R128 R129 R130 R131 R132 R133 R134 R135 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k VDD_O
VDD25 VDD18
R136 4.7K PHYADD0 AN_EN RESET# R139 OPTION VDD_O DUPLEX SPEED1 SPEED VDD_O VDD_C PHYADD3 PHYADD2 VDD_O PHYADD1 PHYADD0 VDD_C AN_EN DUPLEX SPEED1 SPEED R140 R141 R142 R137 R138 VDD_O
DUPLEX Link 1000 Link Link
Activity
VDD_O VDD_C
VDD_O
VDD_O
VDD_C
IO_VDD CORE_VDD VDD_SEL_STRAP /RESET /TRST IO_VDD CORE_VDD RESERVED IO_VDD CORE_VDD PHYADDR3_STRAP PHYADDR2_STRAP IO_VDD PHYADDR1_STRAP PHYADDR0_STRAP /DUPLEX_LED CORE_VDD AN_EN_STRAP /LINK1000_LED LINK100_LED /DUPLEX_STRAP LINK10_LED /SPEED1_STRAP ACTIVITY_LED /SPEED_STRAP TX_TCLK IO_VDD /INTERRUPT RESERVED NON_IEEE_STRAP
DP83865AVH RX_VDD25 C184 0.1uF MDID_N MDID_P RX_VDD MDIC_N MDIC_P RX_VDD MDIB_N MDIB_P RX_VDD MDIA_N MDIA_P RX_VDD RX_VDD MDID_N MDID_P VDD_C MDIC_N MDIC_P VDD_C MDIB_N MDIB_P VDD_C MDIA_N MDIA_P VDD_C VDD_C MDID_N MDID_P RX_VDD25 C187 0.1uF MDIC_N MDIC_P RX_VDD25 C190 0.1uF MDIB_N MDIB_P RX_VDD25 C194 0.1uF MDIA_N MDIA_P C198 1000pF C195 0.1uF R160 49.9 C196 R161 49.9 0.1uF C197 0.1uF C191 0.1uF R155 49.9 C192 R156 49.9 0.1uF C188 0.1uF R148 49.9 C189 R149 49.9 0.1uF TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD424HST1041 C193 0.01uF/2KV MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX424 R150 MDI_DMDI_D+ R152 MDI_CMDI_C+ R153 MDI_BMDI_B+ R157 MDI_AMDI_A+ MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ JACK4 C185 0.1uF R143 49.9 C186 R144 49.9 0.1uF
RXD[0.7] RX_DV RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 R147
R145 R146
4.7K VDD_O
VDD_C R151 VDD_O
RX_CLK TX_CLK
R154 R158 R159
TXD7 TXD6 TXD5 TXD4 IO_VDD TXD3 TXD2 CORD_VDD TXD1 TXD0 IO_VDD GTX_CLK MDIO IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD CORD_VDD MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD PGM_VDD CORD_VDD BG_VDD BG_REF
VDD_O 4.7K TX_EN VDD_C
RX_ER IO_VDD RX_DV RXD7 RXD6 RXD5 CORD_VDD RXD4 RXD3 RXD2 IO_VDD RXD1 RXD0 RX_CLK IO_VDD TX_CLK TX_ER TX_EN CORD_VDD
RJ45_A
VDD_O VDD_O VDD_C PHYADD4 RX_VDD25 VDD_C RX_VDD25
TXD7 TXD6 TXD5 TXD4 VDD_O TXD3 TXD2 VDD_C TXD1 TXD0 VDD_O
TXD[0.7] R163 4.7K
R162
9.76K
GTX_CLK VDD_O MDIO
R164 R166
1.5K
R165 C200 C199 22uF
F.B.
VDD_C
VDD_O VDD_O R167 1.5K 0.1uF
OPTION
25M_IN R168 4.7K
VDD_O C201 VDD25 C206 VDD18 C225 C227 C228 F.B. 1000pF C226 C229 VDD_C C208 C209 F.B. 1000pF C207 C210 VDD_O C211 1000pF C212 0.1uF C213 0.1uF C202
RX_VDD25 C203 1000pF C204 0.1uF C205 0.1uF
100uF/16V 0.1uF
C214 0.1uF
C215 0.1uF
C216 0.1uF
C217 0.1uF
C218 0.1uF
C219 0.1uF
C220 0.1uF
C221 0.1uF
C222 0.1uF
C223 0.1uF
C224 0.1uF
100uF/16V 0.1uF
100uF/16V 0.1uF
ASIX ELECTRONICS CORPORATION C230 1000pF C231 0.1uF C232 0.1uF C233 0.1uF C234 0.1uF C235 0.1uF C236 0.1uF C237 0.1uF C238 0.1uF C239 0.1uF C240 0.1uF C241 0.1uF C242 0.1uF C243 0.1uF C244 0.1uF Size Date: Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch Port G'PHY CKT. Document Number GPHY3.SCH Thursday, March 2002 Sheet
100uF/16V 0.1uF
100uF/16V 0.1uF
ASIX ELECTRONICS CORPORATION
SHIELD
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
RXD[0.7] RX_CLK RX_DV TX_CLK RXD[0.7] RX_CLK RX_DV TX_CLK
GTX_CLK TXD[0.7] TX_EN MDIO PHY_RST# 25MHZ
GTX_CLK TXD[0.7] TX_EN MDIO RESET# 25M_IN
01011
PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED R169 R170 R171 R172 R173 R174 R175 R176 R177 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k VDD_O
VDD25 VDD18
VDD25 VDD18 VDD_O R178 4.7K
PHYADD0 AN_EN RESET# R181 OPTION VDD_O DUPLEX SPEED1 SPEED VDD_O VDD_C PHYADD3 PHYADD2 VDD_O PHYADD1 PHYADD0 VDD_C AN_EN DUPLEX SPEED1 SPEED
R179 R180 R182 R183 R184
VDD_O
DUPLEX Link 1000 Link Link
Activity
VDD_O VDD_C
VDD_O
VDD_O
VDD_C
IO_VDD CORE_VDD VDD_SEL_STRAP /RESET /TRST IO_VDD CORE_VDD RESERVED IO_VDD CORE_VDD PHYADDR3_STRAP PHYADDR2_STRAP IO_VDD PHYADDR1_STRAP PHYADDR0_STRAP /DUPLEX_LED CORE_VDD AN_EN_STRAP /LINK1000_LED LINK100_LED /DUPLEX_STRAP LINK10_LED /SPEED1_STRAP ACTIVITY_LED /SPEED_STRAP TX_TCLK IO_VDD /INTERRUPT RESERVED NON_IEEE_STRAP
DP83865AVH RX_VDD25 C245 0.1uF MDID_N MDID_P RX_VDD MDIC_N MDIC_P RX_VDD MDIB_N MDIB_P RX_VDD MDIA_N MDIA_P RX_VDD RX_VDD MDID_N MDID_P VDD_C MDIC_N MDIC_P VDD_C MDIB_N MDIB_P VDD_C MDIA_N MDIA_P VDD_C VDD_C MDID_N MDID_P C246 0.1uF R185 49.9 C247 R186 49.9 0.1uF
RXD[0.7] RX_DV RXD7 RXD6 RXD5 RXD4 R189
R187
4.7K VDD_O
R188
VDD_C R193 VDD_O
RXD3 RXD2 RXD1 RXD0
RX_CLK TX_CLK
R196 R200 R201
VDD_O 4.7K TX_EN VDD_C
TXD7 TXD6 TXD5 TXD4 IO_VDD TXD3 TXD2 CORD_VDD TXD1 TXD0 IO_VDD GTX_CLK MDIO IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD CORD_VDD MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD PGM_VDD CORD_VDD BG_VDD BG_REF
RX_ER IO_VDD RX_DV RXD7 RXD6 RXD5 CORD_VDD RXD4 RXD3 RXD2 IO_VDD RXD1 RXD0 RX_CLK IO_VDD TX_CLK TX_ER TX_EN CORD_VDD
RX_VDD25 C248 0.1uF MDIC_N MDIC_P C249 0.1uF R190 49.9 C250 R191 49.9 0.1uF TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD424HST1041 C254 RX_VDD25 C255 0.1uF MDIA_N MDIA_P C259 1000pF C256 0.1uF R202 49.9 C257 R203 49.9 0.1uF C258 0.1uF 0.01uF/2KV MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX424 R192 MDI_DMDI_D+ R194 MDI_CMDI_C+ R195 MDI_BMDI_B+ R199 MDI_AMDI_A+ MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ JACK5
RX_VDD25 C251 0.1uF MDIB_N MDIB_P C252 0.1uF R197 49.9 C253 R198 49.9 0.1uF
RJ45_A
PHYADD4 RX_VDD25
VDD_C RX_VDD25
TXD7 TXD6 TXD5 TXD4 VDD_O TXD3 TXD2 VDD_C TXD1 TXD0 VDD_O
VDD_O
VDD_O VDD_C
TXD[0.7] R205 4.7K
R204
9.76K
GTX_CLK VDD_O MDIO
R206 R208
1.5K
R207
VDD_C
C261 VDD_O VDD_O R209 1.5K 0.1uF 22uF C260
F.B.
OPTION
25M_IN R210 4.7K
VDD_O C262 VDD25 C267 VDD18 C286 C288 C289 F.B. 1000pF C287 C290 VDD_C C269 C270 F.B. 1000pF C268 C271 VDD_O C272 1000pF C273 0.1uF C274 0.1uF C263
RX_VDD25 C264 1000pF C265 0.1uF C266 0.1uF
100uF/16V 0.1uF
C275 0.1uF
C276 0.1uF
C277 0.1uF
C278 0.1uF
C279 0.1uF
C280 0.1uF
C281 0.1uF
C282 0.1uF
C283 0.1uF
C284 0.1uF
C285 0.1uF
100uF/16V 0.1uF
100uF/16V 0.1uF
ASIX ELECTRONICS CORPORATION C291 1000pF C292 0.1uF C293 0.1uF C294 0.1uF C295 0.1uF C296 0.1uF C297 0.1uF C298 0.1uF C299 0.1uF C300 0.1uF C301 0.1uF C302 0.1uF C303 0.1uF C304 0.1uF C305 0.1uF Size Date: Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch Port G'PHY CKT. Document Number GPHY4.SCH Thursday, March 2002 Sheet
100uF/16V 0.1uF
100uF/16V 0.1uF
ASIX ELECTRONICS CORPORATION
SHIELD
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
CRS0 COL0 RXD0[0.7] RX_CLK0 RX_DV0 TX_CLK0 CRS1 COL1 RXD1[0.7] RX_CLK1 RX_DV1 TX_CLK1 CRS2 COL2 RXD2[0.7] RX_CLK2 RX_RV2 TX_CLK2 CRS3 COL3 RXD3[0.7] RX_CLK3 RX_RV3 TX_CLK3 CRS4 COL4 RXD4[0.7] RX_CLK4 RX_RV4 TX_CLK4 CRS0 COL0 RXD0[0.7] RX_CLK0 RX_DV0 TX_CLK0 CRS1 COL1 RXD1[0.7] RX_CLK1 RX_DV1 TX_CLK1 CRS2 COL2 RXD2[0.7] RX_CLK2 RX_DV2 TX_CLK2 CRS3 COL3 RXD3[0.7] RX_CLK3 RX_DV3 TX_CLK3 CRS4 COL4 RXD4[0.7] RX_CLK4 RX_DV4 TX_CLK4
RXD0[0.7]
GTX_CLK0 TXD0[0.7] TX_EN0 GTX_CLK1 TXD1[0.7] TX_EN1 GTX_CLK2 TXD2[0.7] TX_EN2 GTX_CLK3 TXD3[0.7] TX_EN3 GTX_CLK4 TXD4[0.7] TX_EN4
GTX_CLK0 TXD0[0.7] TX_EN0 GTX_CLK1 TXD1[0.7] TX_EN1 GTX_CLK2 TXD2[0.7] TX_EN2 GTX_CLK3 TXD3[0.7] TX_EN3 GTX_CLK4 TXD4[0.7] TX_EN4
2.5V
RX_DV0 RX_CLK0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 COL0 CRS0 2.5V
TXD00 TXD01 TXD02 TXD03 TXD04 TXD05 TXD06 TXD07 TX_EN0 R214 R212 R213
TXD0[0.7]
2.5V
2.5V
GCLK SYSCLK RESET# MDIO SDIO VDD33 VDD25_2
GCLK SYSCLK RESET# MDIO SDIO VDD33 VDD25
3.3V X_IN X_OUT 2.5VA FILTER 2.5VA CRS1 COL1 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 RXD16 RXD17 RX_CLK1 RX_DV1 GTX_CLK1 R224 2.5V TX_CLK1 R225 R226
FILTER R222 RXD1[0.7]
C306 39pF
C307 680pF
TXD1[0.7]
TXD1[5] TXD1[6] TXD1[7] TX_EN1 VDD25 CRS2 COL2 RXD2[0] RXD2[1] RXD2[2] RXD2[3] RXD2[4] RXD2[5] RXD2[6] RXD2[7] RX_CLK2 RX_DV2 GTX_CLK2 VDD25 TX_CLK2 TXD2[0] TXD2[1] TXD2[2] TXD2[3] TXD2[4] TXD2[5] TXD2[6] TXD2[7] TX_EN2 VDD25 CRS3 COL3 RXD3[0] RXD3[1] RXD3[2] RXD3[3] RXD3[4] RXD3[5] RXD3[6] RXD3[7] RX_CLK3 RX_DV3 GTX_CLK3 VDD25 TX_CLK3 TXD3[0] TXD3[1] TXD3[2] TXD3[3] TXD3[4] TXD3[5] TXD3[6] TXD3[7] TX_EN3 VDD25 CRS4 COL4 RXD4[0] RXD4[1]
TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TXD16 TXD17
TXD0[3] TXD0[2] TXD0[1] TXD0[0] TX_CLK0 VDD25 GTX_CLK0 RX_DV0 RX_CLK0 RXD0[7] RXD0[6] RXD0[5] RXD0[4] RXD0[3] RXD0[2] RXD0[1] RXD0[0] COL0 CRS0 VDD25 VDD25 VDD25 VDD25
GTX_CLK0 R211
TX_CLK0 2.5V
2.5V
2.5V
TXD0[4] TXD0[5] TXD0[6] TXD0[7] TX_EN0 VDD25 VDD25 VDD33 X_IN X_OUT AVBB25 AVDD25A AVSS25A FILTER AVSS25D AVDD25D CRS1 COL1 RXD1[0] RXD1[1] RXD1[2] RXD1[3] RXD1[4] RXD1[5] RXD1[6] RXD1[7] RX_CLK1 RX_DV1 GTX_CLK1 VDD25 TX_CLK1 TXD1[0] TXD1[1] TXD1[2] TXD1[3] TXD1[4]
AX88655
VDD25 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 VDD33 /RST SYSCLK MDIO SDIO VDD25 GCLK /SYSCLK_EN /GCLK_EN SID4 SID3 SID2 SID1 SID0 VDD25 TX_EN4 TXD4[7] TXD4[6] TXD4[5] TXD4[4] TXD4[3] TXD4[2] TXD4[1] TXD4[0] TX_CLK4 VDD25 G_TXCLK4 RX_DV4 RX_CLK4 RXD4[7] RXD4[6] RXD4[5] RXD4[4] RXD4[3] RXD4[2]
2.5V
2.5V
3.3V RESET# SYSCLK MDIO SDIO 2.5V GCLK SYSCLK_EN# GCLK_EN#
R215 1.5K
2.5V R216 1.5K
SYSCLK_EN pull down, SYSCLK input 90MHZ, else X_IN X_OUT input 27MHz.
SYSCLK_EN# R217 GCLK_EN#
R218
2.5V R219 R220 TX_EN4 TXD47 TXD46 TXD45 TXD44 TXD43 TXD42 TXD41 TXD40
R221 TX_CLK4 2.5V R223 RX_DV4 RX_CLK4 RXD47 RXD46 RXD45 RXD44 RXD43 RXD42
TXD4[0.7]
GTX_CLK4
2.5V CRS2 COL2 RXD20 RXD21 RXD22 RXD23 RXD24 RXD25 RXD26 RXD2[0.7] RXD27 RX_CLK2 RX_DV2 R229 GTX_CLK2 2.5V TX_CLK2 R230 TXD20 TXD21 TXD22 TXD23 R231 TXD24 TXD25 TXD26 TXD2[0.7] TXD27 R232 TX_EN2 2.5V CRS3 COL3 RXD30 RXD31 RXD32 RXD33 RXD34 RXD35 RXD36 RXD3[0.7] RXD37 RX_CLK3 RX_DV3 R233 GTX_CLK3 2.5V TX_CLK3 R234 TXD30 TXD31
RXD41 RXD40 R235 2.5V CRS4 COL4
RXD4[0.7]
TX_EN1 R228
R227
X_IN 27MHZ C308 20pF C309 20pF F.B. X_OUT
F.B. VDD25 C310 C312 C313 F.B. 1000pF C311 C314 2.5V C315 1000pF C316 0.1uF C317 0.1uF C318 0.1uF C319 0.1uF C320 0.1uF C321 0.1uF C322 0.1uF C323 0.1uF C324 0.1uF C325 0.1uF C326 0.1uF C327 0.1uF C328 0.1uF C329 0.1uF C330 0.1uF C331 0.1uF C332 0.1uF
220uF/16V0.1uF
220uF/16V0.1uF
VDD25 C333 C337 C338 F.B. 1000pF C334 C339 2.5VA C340 1000pF C341 0.1uF C342 0.1uF VDD33 C335 C343
3.3V C344 F.B. 1000pF C336 C345 C346 1000pF C347 0.1uF C348 Title 100uF/16V0.1uF 0.1uF Size Date: AX88655 5-Port 10/100/1000BASE-T EtherNet Switch AX88655 CKT. Document Number GSW_CKT.SCH Thursday, March 2002 Sheet ASIX ELECTRONICS CORPORATION
100uF/16V0.1uF
100uF/16V0.1uF
100uF/16V0.1uF
TXD32 TXD33 TXD34 TXD35 TXD36 TXD3[0.7] TXD37 R236 TX_EN3
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
VDD33 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4
VDD33
GCLK SYSCLK
GCLK SYSCLK
VDD33 C349 F.B. 0.1uF C350 0.1uF 125MHz R237 GCLK 25MHz 25M_P0 25M_P1 R238 R240 R242
CLK2 CLK1 PLL102_05 CLKOUT CLK4 CLK3 R239 R241 CLK_VDD1 R243 25M_P4 25M_P3 25M_P2
VDD33 C351 F.B. 0.1uF C352 0.1uF 90MHz C353 F.B. 0.1uF 0.1uF C354 R244 SYSCLK VDD33 CLK_VDD1
VDD33 C355 F.B. 0.1uF C356 0.1uF 25MHZ R245 25MHz
ASIX ELECTRONICS CORPORATION Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch CKT. Size Date: Document Number OSC_CKT.SCH Thursday, March 2002 Sheet
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
VDD33 VDD25 VDD25_2 VDD18_2 VDD18_1 RST_CTL# VDD33 VDD25 VDD25_2 VDD18_2 VDD18_1 RST_CTL#
RST#_P34 RST#_P12 RST#_P0 RST#_SW
RST#_P34 RST#_P12 RST#_P0 RST#_SW
5VSB 3.3V R247 4.7K R249 3.3V PS_ON SPST 3.3V 3.3V -12V 3.3V PS-ON PW_OK 5VSB POWER 220uF/16V R253 100/2W 3.3V 3.3V 5VSB C371 C372 1000pF C373 0.1uF C374 1000pF C375 0.1uF 220uF/16V 3.3V R250 C376 C378 0.1uF C379 1000pF LT1085 C366 1N5402 1000pF C367 0.1uF C368 1000pF C369 0.1uF C365 220uF/16V INPUT 220uF/16V TEST POINT C357 C359 0.1uF C360 1000pF LT1085 TEST POINT TAB/OUT VOUT ADJ/GND VDD18_1 VDD18_1 R246 R248 C358 220uF/16V C361 0.1uF C362 1000pF C363 0.1uF C364 1000pF
1.8V Output
TEST POINT TEST POINT
C370 0.1uF
Power
TAB/OUT VOUT ADJ/GND VDD18_2 VDD18_2 R251 R252 C377 220uF/16V C380 0.1uF C381 1000pF C382 0.1uF C383 1000pF
1.8V Output
TEST POINT TEST POINT
C397 CON2 0.1uF 1N5402 1000pF 0.1uF 1000pF 0.1uF 3.3V C393 C394 C395 C396 C392 220uF/16V 3.3V INPUT TEST POINT TP10 TEST POINT VDD25 C398 C399 1000pF C400 0.1uF C401 1000pF C402 0.1uF 220uF/16V R257 220uF/16V C403 C405 0.1uF C406 1000pF C407 1000pF LT1085 TAB/OUT VOUT ADJ/GND TP11 VDD25 R256 R258 C404 220uF/16V C408 0.1uF C409 1000pF C410 0.1uF C411 1000pF 2.5V TEST POINT TP12 TEST POINT C384 220uF/16V C386 0.1uF C387 1000pF LT1085 TAB/OUT VOUT ADJ/GND VDD25_2 R254 R255 C385 220uF/16V C388 0.1uF C389 1000pF C390 0.1uF C391 1000pF
2.5V Output
TEST POINT TEST POINT
3.3V Power Output
VDD33 TP13 TEST POINT VDD25 C412 C414 220uF/16V0.1uF VDD33 C413 C415 C416 1000pF TP14 TEST POINT
220uF/16V0.1uF
R259 VDD33 100K 1N4148 VDD33 VDD33 R264 C417 0.1uF
U16A CEXT R261 4.7K VDD33 R265 RST_CTL# R263 74HC04 VDD33 74HC00 U17C 74HC04 C420 0.1uF C421 0.1uF U17D 74HC04 VDD33 U17E 74HC04 R268 VOUT XC61F R269 U18A U17A 74HC04 U17B R260
VDD33
VDD33 RST#_SW
VDD33 C418 0.1uF RST#_P0
REXT/CEXT 74HC123
RST#_P12
Option
C419 0.1uF
PUSHBUTTON
VDD33
RST#_P34
VDD33
C422 0.1uF
C423 4.7uF/16V
VDD33 C424 0.1uF
Option external reset
ASIX ELECTRONICS CORPORATION Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch Power Input CKT. Size Date: Document Number POWER_CKT.SCH Thursday, March 2002 Sheet
ASIX ELECTRONICS CORPORATION
AX88655 5-Port 10/100/1000BASE-T Ethernet Switch
RST_CTL# VDD33 SDIO
RST_CTL#
VDD33 SDIO
VDD33 R270 4.7K VDD33 VDD33 VDD33 VDD33 RST_CTL# SDIO RST_CTL# RST_CTL# VDD33 74HC00 74HC00 C425 0.1uF 74HC125 SDIO BUSY R272 4.7K INIT# U18C STROB# R271 4.7K U18B VDD33 VDD33 C426 0.1uF R279 R281 R282 AT24C16B (SEEPROM) BUSY(O) BUSY R283 VDD33 RST_CTL# SDIO R274 4.7K R275 4.7K R276 4.7K STROB#(I) PD0(I) PD2(I) STROB# R273 R277 R280 R278 INIT# INIT#(I) PRINT_PORT ASIX ELECTRONICS CORPORATION Title AX88655 5-Port 10/100/1000BASE-T EtherNet Switch -Serial EEPROM CKT. Size Date: Document Number ROM_CKT.SCH Thursday, March 2002 Sheet
ASIX ELECTRONICS CORPORATION
ASIX Electronic
Revision history
Revision Date 3/14/02 Comment Initial release.
NO.8, HSIN RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C.
TEL: 886-3-5799500 FAX: 886-3-5799558
Email: support@asix.com.tw Web: http://www.asix.com.tw
http://www.asix.com.tw

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