Megabit High Speed CMOS SRAM DPS1MK32MKV3 DPS1MK32MKV3 `'VER

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Megabit High Speed CMOS SRAM DPS1MK32MKV3 DPS1MK32MKV3 `'VER

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4Mx8/2Mx16/1Mx32, 45ns, 30A128-14
Megabit High Speed CMOS SRAM
DPS1MK32MKV3
DPS1MK32MKV3 `'VERSA-STACK'' module revolutionary high speed memory subsystem using Dense-Pac Microsystems' ceramic Stackable Leadless Chip Carriers (SLCC) mounted co-fired ceramic substrate. offers Megabits SRAM package envelope 1.190 1.190 0.360 inches. DPS1MK32MKV3 contains eight individual 512K SRAMs, packaged their hermetically sealed SLCCs making module suitable commercial, industrial military applications. using SLCCs, `'Versa-Stack'' family modules offers higher board density memory than available with conventional through-hole, surface mount, module, hybrid techniques.
FEATURES:
Organizations Available: READ: 1Meg WRITE: 1Meg Access Times: 45ns Fully Static Operation clock refresh required Power Dissipation Single Power Supply, ±10% Tolerance Compatible Common Data Inputs Outputs Data Retention Current 66-Pin Special `'VERSA-STACK'' Package with Compatable Footprint
FUNCTIONAL BLOCK DIAGRAM
PIN-OUT DIAGRAM NAMES
I/O0 I/O31 CE0, N.C. Address Inputs Data Input/Output Chip Enables Write Enables Output Enable Power (+5V) Ground Connect
30A128-14 REV.
This document contains information product that currently released production Dense-Pac Microsystems, Inc. Dense-Pac reserves right change products specifications herein without prior notice.
DPS1MK32MKV3
TRUTH TABLE Mode Selected DOUT Disable Read Write HIGH Supply Current High-Z Standby High-Z Active DOUT Active Active Don't Care Symbol
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE Characteristic Min. Typ. Max. Unit Supply Voltage Input HIGH Voltage VDD+0.3 Input Voltage -0.52 +125 Operating Temperature
OUTPUT CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit HIGH Voltage IOH= -4.0mA Voltage IOL=8.0mA CAPACITANCE 25°C, 1.0MHz Symbol Parameter Max. Unit Condition CADR Address Input Chip Enable VIN2 Write Enable Output Enable CI/O Data Input/Output
Symbol TSTC TBIAS VI/O
ABSOLUTE MAXIMUM RATINGS Parameter Value
Unit
Storage Temperature +150 Temperature Under Bias +125 Supply Voltage -0.5 +7.0 Input/Output Voltage -0.5 DD+0.5
Symbol IOUT ISB1 ISB2 IDR3 IDR2
Characteristics
OPERATING CHARACTERISTICS: Over operating ranges Typ. Test Conditions Min. Max. Min. Max. VI/O VDD, VIH, Cycle=min., Duty=100% IOUT -0.2V +0.2V -0.2V, -0.2V +0.2V -0.2V, -0.2V +0.2V IOUT 8.0mA IOUT -4.0mA
Min. Max.
Unit
Input Leakage Current Output Leakage Current Operating Supply Current Full Standby Supply Current Standby Current (TTL) Data Retention Supply Current (3V) Data Retention Supply Current (2V) Output Voltage Output High Voltage
16.0 14.4
Typical measurements made +25oC, Cycle min., 5.0V.
Symbol VCDR
Parameter Data Retention Chip Disable Data Retention Time Operation Recovery Time
Data Retention Characteristics Test Conditions -0.2V Data Retention Waveform Data Retention Waveform
Min.
Typ.
Max.
Unit
30A128-14 REV.
Dense-Pac Microsystems, Inc.
DPS1MK32MKV3
OUTPUT LOAD Parameters Measured except tHZ, tOHZ, tOLZ, tLZ, tHZ, tOHZ, tOLZ, tWHZ
TEST CONDITIONS Input Pulse Levels 3.0V Input Pulse Rise Fall Times Input Output 1.5V Timing Reference Levels
Load
30pF
Figure Output Load
Including Probe Capacitance.
DATA RETENTION WAVEFORM:
4.5V 2.3V VDR1
-0.2V
Controlled.
DOUT
OPERATING CONDITIONS CHARACTERISTICS READ CYCLE: Over operating ranges 20ns 25ns 30ns 35ns 45ns Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min.
Max.
Unit
tOLZ tOHZ
Read Cycle Time Address Access Time Output Valid Output Enable Output Valid Output LOW-Z Output Enable Output LOW-Z Output HIGH-Z Output Enable Output HIGH-Z Output Hold from Address Change
OPERATING CONDITIONS CHARACTERISTICS WRITE CYCLE Over operating ranges 20ns 25ns 30ns 35ns 45ns Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min.
Max.
Unit
tWHZ
Write Cycle Time Address Valid Write Chip Enable Write Address Set-Up Time Write Pulse Width Write Recovery Time Write Enable Output HIGH-Z Data Write Time Overlap Data Hold from Write Time Output Active from Write
Valid both Read Write Cycles. 30A128-14 REV.
DPS1MK32MKV3
Dense-Pac Microsystems, Inc.
READ CYCLE
ADDRESS
DATA
WRITE CYCLE Controlled.
ADDRESS
DATA
DATA
WAVEFORM
Data Valid
Transition from HIGH
Transition from HIGH
Data Undefined Don't Care
30A128-14 REV.
Dense-Pac Microsystems, Inc.
WRITE CYCLE Controlled. HIGH.
DPS1MK32MKV3
ADDRESS
DATA
DATA WRITE CYCLE Controlled. LOW.
ADDRESS
DATA
DATA
NOTES: voltages with respect -2.0V min. pulse width less than 20ns (VIL min. -0.5V level). Stresses greater than those under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
30A128-14 REV.
This parameter guaranteed 100% tested. Transition measured point ±500mV from steady state voltage. When HIGH, pins output state,and input signals opposite phase outputs must applied. outputs high impedance state when LOW. initiate terminate WRITE Cycle.
DPS1MK32MKV3
Dense-Pac Microsystems, Inc.
ORDERING INFORMATION
MECHANICAL DRAWING
7321 Lincoln Garden Grove California 92841-1431 (714) 898-0007 (800) 642-4477 (Outside FAX: (714) 897-1772 http://www.dense-pac.com
Dense-Pac Microsystems, Inc.
30A128-14 REV.

Megabit High Speed CMOS SRAM DPS1MK32MKV3 DPS1MK32MKV3 `'VER

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