CY230 Twenty Output Zero Delay Buffer Features Total ti

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CY230 Twenty Output Zero Delay Buffer Features Total ti

Datasheet Thumbnail

Top Searches for this datasheet

CY230
Twenty Output Zero Delay Buffer
Features
Total timing budget impact (TTBI) Spread Aware-designed work with SSFTG reference signals Outputs selected equal input frequency x1,or LVTTL/LVCMOS inputs/outputs 3.3V core power supply 2.5V 3.3V output signals Available 48-pin TSSOP packages (contact factory package availability)
Overview
CY23020-1 PLL-based clock driver designed provide high performance. clock driver provides output frequencies MHz. most prominent feature skew, jitter, total timing budget impact performance that exceeds most previous Zero Delay Buffer (ZDB) products.
Block Diagram
2->1
LOCKED FBOUT
Configurations
LOCKED VDDC GNDC REF- REF+ GNDC VDDC FBIN- FBIN+ FBOUT RANGE
FBIN
2->1
CY230
S1:2 RANGE
C1C1
Output Control Logic
Cypress Semiconductor Corporation Document 38-07120 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised October 2001
CY230
Definitions
Name REF+ REFFBIN+ FBINPin Type Description Reference Inputs: Output signals synchronized crossing point REF+ REF- signals. Therefore REF- must tied VREF defined characteristics table. optimal performance, impedances seen these inputs must equal. Feedback Inputs: Input FBIN+ must outputs ensure proper functionality. trace between FBIN+ FBOUT equal length traces between outputs signal destinations, then signals received destinations will synchronized clock signal REF+ input. FBIN- must tied VREF defined characteristics table. best performance, impedances seen these inputs must equal. Feedback Output: order complete phase locked loop, output must connected back FBIN+ pin. outputs actually used feedback source. Outputs: Refer Tables characteristics these outputs.
FBOUT
Q1:19
RANGE LOCKED
Frequency Range Selection Input: determine correct connection this pin, refer Table This should static input Locked Output: When this output HIGH, CY23020-1 steady state operation mode (Locked). When this signal LOW, process locking onto reference signal. Output/PLL Enable Selection bits: determine appropriate settings, refer Table Analog Power Connection: Connect 3.3V. Analog Ground Connection: Connect common system ground plane. Output Buffer Power Connections: Connect 3.3V, whichever reference output signals. Ground Connections: Connect common system ground plane.
S1:2 VDDC GNDC
Multiplication factor select: When HIGH, outputs will twice speed reference signal. This should static input Output Configuration bit: Establishes either 2.5V 3.3V Full Swing Operation. determine appropriate setting, refer Table This should static input Connect: This must left floating. This used factory testing purposes.
Notes: Note Inputs Range,Mul,and static inputs. Note B:Default pull down resistors (~100kohm) present Range, Mul, inputs.
Document 38-07120 Rev.
Page
Table Output Configuration source Three-state Reserved Reference Input Output Shutdown Active Shutdown
CY230Inserting Other Devices Feedback Path
fact that device external feedback path user wide range control over output input skewing effect. these able synchronize outputs external clock that resultant from output clocks. This implementation applied device (ASIC, multiple output clock buffer/driver, etc.) that into feedback path. Referring Figure traces between ASIC/buffer destination clock signal(s) equal length trace between buffer FBIN (B), signals destination(s) device will driven high same time Reference clock provided goes high. Synchronizing other outputs outputs from ASIC/Buffer more complex however, propagation delay ASIC/Buffer must accounted for. There constraints when inserting other devices. devices contain Phase Locked Loops (PLL's) excessively long delay times they easily cause overall clocking system become unstable components interact. these designs advisable contact Cypress applications support.
Reference Signal Feedback Input Zero Delay Buffer
Table Frequency Range Setting RANGE Output Frequency Range 50-100 100-200
Table Output Configuration Setting Output Type Full swing Full swing
Table Frequency Multiplication table Output Frequency FOUT FREF FOUT FREF
ASIC/ Buffer
Spread Aware
Many systems designed utilize Spread Spectrum Modulation clock technology. This technology used dramatically reduce Electro Magnetic Interference (EMI) digital systems. Cypress pioneered SSFTG development, this product designed pass SSFTG modulation that present REF+ output clock signals. This capability also enhances part produce clocks with significantly smaller jitter tracking skew output clocks. This especially beneficial systems that have downstream PLLs present. more details Spread Spectrum timing technology, please Cypress application note titled, "EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs."
Figure Output Buffer Feedback Path
Component Characterization Set-Up
onchip output buffer
inch line
Figure Termination Networks
Cbyp FBINFBIN+ RefRef+ Vref Source Cbyp
Implement Zero Delay
Typically, ZDBs multiply (fan-out) single clock signals quantity while simultaneously reducing mitigating time delay associated with passing clock through buffering device. many cases output clock adjusted, phase, occur later more often before device's input clock compensate design's physical delay inadequacies. Most commonly this done using simple trace time delay element. longer trace earlier output clock edges occur with respect reference input clock edges. this such effects undesired transit time clock signal across compensated for.
FBOUT
Figure Establishing Reference Voltages
Document 38-07120 Rev.
Page
CY23020-1 uses differential input receiver increase it's rejection common mode input noise thus increase device performance. ensure that noise appears equally both Ref- Ref+ pins, necessary match external impedance circuitry seen these pins. Figure shows this accomplished. reference voltage, VREF generated resistor divider from power supply. This potential will adjust FBIN+ input's triggering threshold. reference voltage should well bypassed introduce single ended noise device. Note that impedance ohms) also matched FBIN+ line. resistor used create "like" load REF- input clock signal matches source imParameter TSTG Description Voltage with respect Voltage input with respect Storage Temperature Operation Temperature Junction Temperature Package Power Dissipation (TSSOP) Package Power Dissipation (QFN)
CY230pedance REF+ input signal. input impedance significantly different than ohms, reference resistor should adjusted accordingly.
Absolute Maximum Ratings
Stresses greater than those listed this table cause permanent damage device. These represent stress rating only. Operation device these other conditions above those specified operating sections this specification implied. Maximum conditions extended periods affect reliability.
Rating -0.5 +5.0 -0.5 VDD+0.5 +150 +150 max.
Unit
Full Swing Electrical Characteristics to70°C, VDDC ±5%, ±5%, Parameter TVDD Description REF+, FBIN+ Inputs only REF+, FBIN+ Inputs only Logic Inputs only Logic Inputs only Power Down current Supply Voltage Ramp Rate Input Capacitance disable mode, S0:S1=0 0.7xVDD 0.3xVDD Test Condition Min. Typ. Max. Unit V/ms
2.5V Full Swing Electrical Characteristics 70°C, VDDC ±5%, ±5%, 1.19V VREF 1.50V Parameter Description Supply Current Input Current HIGH state Input Current state Output current HIGH state Output current state Test Condition Unloaded, VIN= VIN= Measured pin, load network, VDD-0.35 Measured pin, load network, =0.35 Min. Typ. Max. Unit
2.5V Full Swing Electrical Characteristics to70°C, VDDC ±5%, ±5%, 1.19 VREF 1.50V, Load: (see Figure 5pF) Parameter FOUT Description Input Frequency Output Frequency Test Condition 2002 2002 Unit
Document 38-07120 Rev.
Page
2.5V Full Swing Electrical Characteristics to70°C, VDDC ±5%, ±5%, 1.19 VREF 1.50V, Load: (see Figure 5pF) Parameter TISR TIDC TPD2 TTBI TTBI2 TJC_RMS TJP_RMS TJLRMS TJC2 TJCRMS2 TJP2 TJPRMS2 TJL2 TJLRMS2 Tlock TPWD TTSK PSRR Description Input Slew Rate Output Rise Rate Output Fall Rate Input Duty Cycle Output Duty Cycle FBIN skew FBIN skew Output-Output Skew Total Timing Budget Impact Total Timing Budget Impact Peak Cycle Cycle Jitter (1000 cycles max) Cycle Cycle Jitter Period Jitter Period Jitter Long Term Jitter Long Term Jitter Peak Cycle Cycle Jitter (1000 cycles max) Cycle Cycle Jitter Period Jitter Period Jitter Long Term Jitter Long Term Jitter Power-Up Lock Time Power Down time Spread Spectrum Tracking Skew Power Supply Rejection Ratio Fsupply KHz-10 Test Condition Measured between input swing Measured between output swing Measured between output swing Tested swing Measured VDD/2 Fout Fref Fout Frefx2 Outputs equally loaded output1, Fout Fref output1, Fout Frefx2 outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 -175 -225
CY230
Unit V/ns V/ns V/ns ps/V
3.3V, Full Swing Electrical Characteristics to70°C, VDDC 3.3V ±5%, 3.3V ±5%, 0.42 VREF 0.50 Parameter Description Supply current Input Current high state Input Current state Vin=VDD Vin=0 Test Condition Unloaded, 200Mhz Unit
Document 38-07120 Rev.
Page
3.3V, Full Swing Electrical Characteristics to70°C, VDDC 3.3V ±5%, 3.3V ±5%, 0.42 VREF 0.50 Parameter Description Output current high state Output current state Test Condition measured pin, load network, Voh=2.4V measured pin, load network, Vol=0.4V
CY230
Unit
3.3V, Full Swing Electrical Characteristics: to70°C, VDDC 3.3V ±5%, 3.3V ±5%, 0.42 VREF 0.50 VDD, Load: (see Figure 5pF), Parameter FOUT TISR TIDC TPD2 TTBI TTBI2 TJC_RMS TJP_RMS TJLRMS TJC2 TJCRMS2 TJP2 TJPRMS2 TJL2 TJLRMS2 Tlock TPWD TTSK Description Input Frequency Output Frequency Input Slew Rate Output Rise Rate Output Fall Rate Input Duty Cycle Output Duty Cycle FBIN skew FBIN skew Output-Output Skew Total Timing Budget Impact Total Timing Budget Impact Peak Cycle Cycle Jitter (1000 cycles max) Cycle Cycle Jitter Period Jitter Period Jitter Long Term Jitter Long Term Jitter Peak Cycle Cycle Jitter (1000 cycles max) Cycle Cycle Jitter Period Jitter Period Jitter Long Term Jitter Long Term Jitter Power lock time Power Down time Spread Spectrum Tracking skew Refin output1,Fout Fref Refin output1,Fout Frefx2 outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Fref outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 outputs active, Fout Frefx2 Measured between input swing Measured between output swing Measured between output swing Tested swing Measured VDD/2 Fout Fref Fout Frefx2 Test Condition -175 -225
Unit v/ns V/ns V/ns
2002
Document 38-07120 Rev.
Page
CY230
3.3V, Full Swing Electrical Characteristics: to70°C, VDDC 3.3V ±5%, 3.3V ±5%, 0.42 VREF 0.50 VDD, Load: (see Figure 5pF), Parameter PSRR Notes:
MAX(TPD_MAX-TPD_MIN, TPD_MAX,(-1)*TPD_MIN) where _MAX longest delay refin output measured over least 1000cycles TPD_MIN minimum (may negative) delay observed over outputs over least 1000 cycles. Full statistics, mean, min., max, stdv each output will measured. Maximum Frequency TSSOP packaged version load This limitation result thermal performance package. Theta 95oC/W TSSOP package.
Description Power Supply Rejection Ratio
Test Condition Fsupply 1KHz-10Mhz
Unit ps/v
Ordering Information
Base Part Number CY23020ZC CY23020LFC Option code Package TSSOP[3] (contact factory availability) Temperature Range Commercial (0o-70o) Commercial (0o-70o)
Spread Aware trademark Cypress Semiconductor Corporation. product company names mentioned this document trademarks their respective holders.
Document 38-07120 Rev.
Page
Package Diagram
CY230
48-Lead Thin Shrunk Small Outline Package, Type
Document 38-07120 Rev.
Page
Cypress Semiconductor Corporation, 2001. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY230
Document Title: CY23020-1 Twenty Output Zero Delay Buffer Document Number: 38-07120 REV. 109287 Issue Date 10/30/01 Orig. Change Description Change Data Sheet
Document 38-07120 Rev.
Page

CY230 Twenty Output Zero Delay Buffer Features Total ti

Top Searches for this datasheet

Other recent searches