5V/3.3V 128K CMOS SRAM (Revolutionary pinout) Features AS7C1

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5V/3.3V 128K CMOS SRAM (Revolutionary pinout) Features AS7C1

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AS7C1025A AS7C31025A
5V/3.3V 128K CMOS SRAM (Revolutionary pinout)
Features
AS7C1025A version) AS7C31025A (3.3V version) Industrial commercial temperatures Organization: 131,072 bits High speed 10/12/15/20 address access time output enable access time power consumption: ACTIVE (AS7C1025A) (5V) (AS7C31025A) (3.3V) power consumption: STANDBY (AS7C1025A) CMOS (5V) (AS7C31025A) CMOS (3.3V) Latest 0.25u CMOS technology Easy memory expansion with inputs Center power ground TTL/LVTTL-compatible, three-state JEDEC-standard packages 32-pin, 32-pin, 32-pin, TSOP protection 2000 volts Latch-up current
arrangement
32-pin TSOP
I/O0 I/O1 I/O2 I/O3 I/O7 I/O6 I/O5 I/O4
Logic block diagram
Input buffer I/O7
decoder
Array (1,048,576)
Sense
32-pin (300 mil) 32-pin (400 mil) I/O0
I/O0 I/O1 I/O2 I/O3 I/O7 I/O6 I/O5 I/O4
Column decoder
Control circuit
Selection guide
Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C1025A AS7C31025A AS7C1025A AS7C31025A Unit
12/7/01; v.0.9.7
Alliance Semiconductor
AS7C1025A AS7C31025A
AS7C1025A AS7C31025A
Copyright Alliance Semiconductor. rights reserved.
AS7C1025A AS7C31025A
Functional description
AS7C1025A AS7C31025A high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized 131,072 bits. They designed memory applications where fast data access, power, simple interfacing desired. Equal address access cycle times (tAA, tRC, tWC) 10/12/15/20 with output enable access times (tOE) ideal high-performance applications. chip enable input permits easy memory expansion with multiple-bank memory systems. When high devices enter standby mode. standard AS7C1025A guaranteed exceed power consumption standby mode. write cycle accomplished asserting write enable (WE) chip enable (CE). Data input pins I/O0-I/O7 written rising edge (write cycle (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with RXWSXW HQDEOH ZULWH HQDEOH (WE). read cycle accomplished asserting output enable (OE) chip enable (CE), with write enable (WE) high. chips drive pins with data word referenced input address. When either chip enable output enable inactive, write enable active, output drivers stay high-impedance mode. chip inputs outputs TTL-compatible, operation from single supply (AS7C1025A) 3.3V supply (AS7C31025A). AS7C1025A AS7C31025A packaged common industry standard packages.
Absolute maximum ratings
Parameter Voltage relative Voltage relative Power dissipation Storage temperature (plastic) Ambient temperature with applied current into outputs (low) Device AS7C1025A AS7C31025A Symbol Tstg Tbias IOUT -0.50 -0.50 -0.50 +7.0 +5.0 +150 +125 Unit
NOTE: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Truth table
Data High High DOUT Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
Key: Don't Care, Low, High
12/7/01; v.0.9.7
Alliance Semiconductor
AS7C1025A AS7C31025A
Recommended operating conditions
Parameter Supply voltage Device AS7C1025A AS7C31025A AS7C1025A Input voltage AS7C31025A Both Ambient operating temperature
min. -3.0V pulse width less than tRC/2.
Symbol
-0.5
Nominal
Unit
commercial industrial
operating characteristics (over operating range)
Parameter
Input leakage current Output leakage current Operating power supply current Standby power supply current Output voltage
Test conditions
Max, Max, VIH, Vout
Device
Both
Unit
Both AS7C1025A
VIL, fMax, IOUT
AS7C31025A AS7C1025A AS7C31025A AS7C1025A AS7C31025A Both
ISB1
VIH, fMax, fOUT VCC-0.2V, 0.2V -0.2V, fOUT
Capacitance MHz, NOMINAL)
Parameter Input capacitance capacitance Symbol CI/O Signals Test conditions VOUT Unit
12/7/01; v.0.9.7
Alliance Semiconductor
AS7C1025A AS7C31025A
Read cycle (over operating range)
Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change output output high output High output high Power time Power down time Symbol tACE tCLZ tCHZ tOLZ tOHZ Unit Notes
switching waveforms
Rising input Falling input Undefined/don't care
Read waveform (address controlled)
Address DOUT Data valid
Read waveform controlled)
DOUT Supply current tACE tCLZ Data valid tOLZ tOHZ tCHZ tRC1
12/7/01; v.0.9.7
Alliance Semiconductor
AS7C1025A AS7C31025A
Write cycle (over operating range)
Parameter Write cycle time Chip enable (CE) write Address setup write Address setup time Write pulse width Write recovery time Address hold from write Data valid write Data hold time Write enable output high Output active from write Symbol Unit Notes
Write waveform controlled)
Address DOUT Data valid
12/7/01; v.0.9.7
Alliance Semiconductor
AS7C1025A AS7C31025A
Write waveform controlled)
Address DOUT Data valid
test conditions
Output load: Figure Figure Input pulse level: 3.0V. Figure Input rise fall times: Figure Input output timing reference levels: 1.5V.
Thevenin equivalent: 168W DOUT +1.728V 3.3V) 480W +3.0V DOUT 255W C(14) DOUT 255W +3.3V 320W C(14)
Figure Input pulse
Figure Output load
Figure 3.3V Output load
Notes
During power-up, pull-up resistor required meet specification. This parameter sampled, 100% tested. test conditions, Test Conditions, Figures tCLZ tCHZ specified with 5pF, Figure Transition measured ±500mV from steady-state voltage. This parameter guaranteed, 100% tested. High read cycle. read cycle. Address valid prior coincident with transition Low. read cycle timings referenced from last valid address first transitioning address. must High during address transitions. Either asserting high terminates write cycle. write cycle timings referenced from last valid address first transitioning address. C=30pF, except high parameters, where C=5pF.
12/7/01; v.0.9.7
Alliance Semiconductor
AS7C1025A AS7C31025A
Package dimensions
32-pin TSOP (mm)
32-pin TSOP
N/2+1
Symbol
0.05 0.12 20.82 10.03 11.56 1.27 0.40 0.95 REF.
0.15 0.52 0.21 21.08 10.29 11.96 0.60
Seating plane
32-pin Symbol 0.025 0.086 0.026 0.014 0.006 0.820 0.250 0.292 0.330 0.145 0.105 0.032 0.020 0.013 0.830 0.275 0.305 0.340
32-pin 0.025 0.086 0.026 0.015 0.007 0.820 0.360 0.395 0.435 0.145 0.115 0.032 0.020 0.013 0.830 0.380 0.405 0.445
32-pin mil/400
Seating Plane
0.050
0.050
12/7/01; v.0.9.7
Alliance Semiconductor
AS7C1025A AS7C31025A
Ordering codes
Package Access time Volt.
TSOP 3.3V 300-mil 3.3V 400-mil 3.3V
Temperature
Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
AS7C1025A-10HFC AS7C1025A-10TI AS7C31025A-10HFC AS7C31025A-10HFI AS7C1025A-10TJC AS7C1025A-10TJI AS7C31025A-10TJC AS7C31025A-10TJI AS7C1025A-10JC AS7C1025A-10JI AS7C31025A-10JC AS7C31025A-10JI
AS7C1025A-12HFC AS7C1025A-12HFI AS7C31025A-12HFC AS7C31025A-12HFI AS7C1025A-12TJC AS7C1025A-12TJI AS7C31025A-12TJC AS7C31025A-12TJI AS7C1025A-12JC AS7C1025A-12JI AS7C31025A-12JC AS7C31025A-12JI
AS7C1025A-15HFC AS7C1025A-15HFI AS7C31025A-15HFC AS7C31025A-15HFI AS7C1025A-15TJC AS7C1025A-15TJI AS7C31025A-15TJC AS7C31025A-15TJI AS7C1025A-15JC AS7C1025A-15JI AS7C31025A-15JC AS7C31025A-15JI
AS7C1025A-20HFC AS7C1025A-20HFI AS7C31025A-20HFC AS7C31025A-20HFI AS7C1025A-20TJC AS7C1025A-20TJI AS7C31025A-20TJC AS7C31025A-20TJI AS7C1025A-20JC AS7C1025A-20JI AS7C31025A-20JC AS7C31025A-20JI
Part numbering system
AS7C SRAM prefix Voltage: Blank=5V CMOS 3=3.3V CMOS 1025 Device number Access time Package: TSOP Temperature range Commercial, 70°C Industrial, -40°C 85°C
12/7/01; v.0.9.7
Alliance Semiconductor
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5V/3.3V 128K CMOS SRAM (Revolutionary pinout) Features AS7C1

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