CMOS DRAM (EDO) Features Organization: 1,048,576 words bits High
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AS4LC1M16E5
CMOS DRAM (EDO) Features
Organization: 1,048,576 words bits High speed
50/60 access time 20/25 hyper page cycle time 12/15 access time
Read-modify-write TTL-compatible, three-state JEDEC standard package pinout
mil, 42-pin mil, 44/50-pin TSOP
power consumption
Active: (-60) Standby: max, CMOS
Extended data 1024 refresh cycles, refresh interval
RAS-only CAS-before-RAS refresh self-refresh
power supply (AS4LC1M16E5) tolerant I/Os; 5.5V maximum Industrial commercial temperature available
arrangement
62Vcc DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 LCAS UCAS
7623
DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
designation
Pin(s) UCAS LCAS Description Address inputs address strobe Output enable Write enable Column address strobe, upper byte Column address strobe, lower byte Power Ground
DQ16 Input/output
LCAS UCAS
Selection guide
Symbol Maximum access time Maximum column address access time Maximum access time Maximum output enable (OE) access time Minimum read write cycle time Minimum hyper page mode cycle time Maximum operating current Maximum CMOS standby current
Unit
tRAC tCAC tOEA tHPC ICC1 ICC5
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Functional description
AS4LC1M16E5 high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized 1,048,576 words bits. device fabricated using advanced CMOS technology innovative design techniques resulting high speed, extremely power wide operating margins component system levels. Alliance 16Mb DRAM family optimized main memory personal portable PCs, workstations, multimedia router switch applications. AS4LC1M16E5 features hyper page mode operation where read write operations within single page) executed very high speed toggling column addresses within that row. column addresses alternately latched into input buffers using falling edge xCAS inputs, respectively. Also, used make column address latch transparent, enabling application column addresses prior xCAS assertion. AS4LC1M16E5 provides dual UCAS LCAS independent byte control read write access. Extended data (EDO), also known 'hyper-page mode,' enables high speed operation. contrast 'fast-page mode' devices, data remains active outputs after xCAS de-asserted high, giving system logic more time latch data. control output impedance prevent contention during read-modify-write shared applications. Outputs also high impedance last occurrance xCAS going high. Refresh 1024 address combinations must performed every using: RAS-only refresh: asserted while xCAS held high. Each 1024 rows must strobed. Outputs remain high impedence. Hidden refresh: xCAS held while toggled. Outputs remain impedence with previous valid data. CAS-before-RAS refresh (CBR): least xCAS asserted prior RAS. Refresh address generated internally. Outputs high-impedence don't care). Normal read write cycles refresh being accessed. Self-refresh cycles AS4LC1M16E5 available standard 42-pin plastic 44/50-pin TSOP packages, respectively. AS4LC1M16E5 device operates with single power supply 0.3V provides compatible inputs outputs.
Logic block diagram
Refresh controller clock generator Column decoder Sense Data buffers DQ16
UCAS LCAS
clock generator
clock generator
Address buffers
decoder 1024 1024 Array (16,777,216) Substrate bias generator
Recommended operating conditions1
Parameter Supply voltage Input voltage Ambient operating temperature Commercial Industrial Symbol -0.5
Nominal
Unit
Recommended operating conditions apply throughout this document unless otherwise specified. -3.0V pulse widths less than
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Absolute maximum ratings
Parameter Input voltage Power supply voltage Storage temperature (plastic) Soldering temperature time Power dissipation Short circuit output current Symbol TSTG TSOLDER Iout -1.0 -1.0 +5.5 +4.0 +150 Unit
Truth table
Addresses Operation Standby Word read Lower byte read Upper byte read Word (early) write Lower byte (early) write Upper byte(early) write Read write
cycle
cycle cycle
LCAS
UCAS
DQ15 High-Z Data Lower byte, Upper byte, Data Lower byte, Data out, Upper byte Data Lower byte, Data Upper byte, High-Z Lower byte, High-Z, Upper byte, Data Data out, Data Data Data Data Data Data Data out, Data Data out, Data High High High
Notes
read
write read write only refresh refresh Self refresh
cycle cycle cycle cycle
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electrical characteristics
Parameter Input leakage current Output leakage current Operating power supply current standby power supply current Average power supply current, refresh mode page mode average power supply current CMOS standby power supply current Output voltage before refresh current Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Test conditions (max) Pins under test DOUT disabled, Vout (max) RAS, UCAS, LCAS, Address cycling; tRC=min UCAS LCAS VIH, other inputs cycling, UCAS LCAS VIH, after XCAS low. VIL, UCAS LCAS, address cycling: tHPC UCAS LCAS 0.2V, IOUT -2.0 IOUT RAS, UCAS LCAS cycling, UCAS LCAS 0.2V, 0.2V, other inputs 0.2V 0.2V Unit
Notes
Self refresh current
ICC7
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parameters common waveforms
Symbol tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tREF tRAL tASC tCAH Parameter Random read write cycle time precharge time pulse width pulse width delay time column address delay time hold time hold time precharge time address setup time address hold time Transition time (rise fall) Refresh period precharge time Column address lead time Column address setup time Column address hold time Unit Notes
Read cycle
Symbol tRAC tCAC tRCS tRCH tRRH Parameter Access time from Access time from Access time from address Read command setup time Read command hold time Read command hold time Unit Notes 9,16 10,16
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Write cycle
Symbol tWCS tWCH tRWL tCWL Parameter Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Unit Notes
Read-modify-write cycle
Symbol tRWC tRWD tCWD tAWD Parameter Read-write cycle time delay time delay time Column address delay time Unit Notes
Refresh cycle
Symbol tCSR tCHR tRPC tCPT Parameter setup time (CAS-before-RAS) hold time (CAS-before-RAS) precharge hold time precharge time (CBR counter test) Unit Notes
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Hyper page mode cycle
Symbol tCPWD tCPA tRASP tDOH tREZ tWEZ tOEZ tHPC tHPRWC tRHCP Parameter precharge delay time Access time from precharge pulse width Previous data hold time from Output buffer turn delay from Output buffer turn delay from Output buffer turn delay from Hyper page mode cycle time Hyper page mode cycle hold time from 100K 100K Unit Notes
Output enable
Symbol tCLZ tROH tOEA tOED tOEZ tOEH tOLZ tOFF Parameter output hold time referenced access time data delay Output buffer turnoff delay from command hold time output Output buffer turn-off time Unit 11,13 Notes
Self refresh cycle
Symbol Parameter tRASS tRPS tCHS
Unit Notes
pulse width (CBR self refresh) precharge time (CBR self refresh) hold time
(CBR self refresh)
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test conditions
Access times measured with output reference levels 2.0V 0.8V, 2.0V 0.8V Input rise fall times: +3.3V Dout
Equivalent output load
*including scope capacitance
Notes
Write cycles byte write cycles (either LCAS UCAS active). Read cycles byte read cycles (either LCAS UCAS active). must active (either LCAS UCAS). ICC1, ICC3, ICC4, ICC6 dependent frequency. ICC1 ICC4 depend output loading. Specified values obtained with output open. initial pause required after power-up followed cycles before proper device operation achieved. case internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. initialization cycles required after extended periods bias without clocks (greater than ms). Characteristics assume parameters measured with load described test conditions below. (min) (max) reference levels measuring timing input signals. Transition times measured between VIL. Operation within tRCD (max) limit insures that tRAC (max) met. tRCD (max) specified reference point only. tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation within tRAD (max) limit insures that tRAC (max) met. tRAD (max) specified reference point only. tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. Assumes three state test load Thevenin equivalent). Either tRCH tRRH must satisfied read cycle. tOFF (max) defines time which output achieves open circuit condition; referenced output voltage levels. tOFF referenced from rising edge CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD tAWD restrictive operating parameters. They included datasheet electrical characteristics only. (min) (min), cycle early write cycle data pins will remain open circuit, high impedance, throughout cycle. tRWD tRWD (min), tCWD tCWD (min) tAWD tAWD (min), cycle read-write cycle data will contain data read from selected cell. neither above conditions satisfied, condition data access time indeterminate. These parameters referenced leading edge early write cycles leading edge read-write cycles. Access time determined longest tCAA tCAC tCPA tASC achieve (min) tCPA (max) values. These parameters sampled 100% tested.
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switching waveforms
Rising input Falling input Undefined output/don't care
Read waveform
tRAS tRCD tRSH
tCSH tCRP tASC tRCS tCAH tCAS
UCAS LCAS
tRAD tASR tRAH Column address tRRH tRCH tRAL
Address
address
tROH tROH
tWEZ
tRAC tOEA tCAC tCLZ tREZ Data tOLZ tOEZ tOFF (see note
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Upper byte read waveform
tRAS
tRCD tCSH tCRP tCAS tRPC tRSH tCRP
UCAS
tCRP
LCAS
tRAH tRAD tASR tASC tRCS Column tRCH tRRH tROH tRAL tCAH
Address
tWEZ
tRAC tCAC tCLZ tOFF Data tOLZ tOEA tOEZ tREZ
Upper Lower
Lower byte read waveform
tRAS
tRCD tCSH tCRP tCAS tRPC tASC tRAL tCAH tRCS Column tRCH tRRH tROH tWEZ tRSH tCRP
LCAS
tCRP
UCAS
tRAH tRAD tASR
Address Upper
tRAC
tOLZ
tOEA tOEZ tCAC
tREZ
tCLZ
tOFF Data
Lower
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Early write waveform
tRAS
tCSH tRSH tCRP tRCD tRAD tASC tASR tRAH tCAH Column address tCWL tRWL tWCS tWCH tCAS tRAL
UCAS, LCAS
Address
address
Data
Upper byte early write waveform
tRAS
tASR tRAH tRAD tRAL Column address tASC tRCD tCSH tCRP tCAS tRPC tCWL tWCS tWCH tRWL tCRP tCAH tRSH address
Address
UCAS
tCRP
LCAS
Data
Upper Lower
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Lower byte early write waveform
tRAS
tRAD tASR tRAH Column address tRPC tASC tRCD tCSH tCRP tRSH tRWL tCWL tWCS tWCH tCRP tCAH tCAS tRAL
Address UCAS
address tCRP
LCAS
Upper
Data
Lower
Write waveform
tRAS
controlled
tCSH tRSH tCRP tRCD tCAS tRAL tRAD tRAH tASC tCAH Column address tRWL tCWL
UCAS, LCAS
tASR
Address
address
tOEH
tOED
Data
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Upper byte write waveform
tRAS
controlled
tRAD tASR tRAH address Column address tCSH tRCD tCRP tASC tRSH tCAH tCAS tCRP tRAL
Address
UCAS
tCRP tRPC tCWL tRWL
LCAS
tOEH
Data tOED
Upper Lower
Lower byte write waveform
tRAS
controlled
tRAD tASR tRAH tRAL Column address tRCD tCSH tCRP tACS tCRP tRSH tRPC tCWL tRWL tCRP tCAH tCAS
Address
address
LCAS UCAS
tOEH
Upper
Data
Lower
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Read-modify-write waveform
tRWC tRAS tCAS tCRP tRCD tCSH tRSH
UCAS LCAS
tRAD tASR tRAH address
tRAL tASC tCAH Column address tRWD tAWD tRCS tCWD tOEA tOEZ tOED tCWL tRWL
Address
tRAC
tCAC tCLZ Data
tOLZ
Data
Upper byte read-modify-write waveform
tRWC tRAS
tCSH tRCD tCRP tCRP tCAS tRSH tCRP tRPC tACS tRAH
UCAS LCAS
tASR tRAD
tRAL tCAH tCWL tRWL tCWD tOEA
Address
Column address tRWD tAWD tRCS
Upper input
tCLZ tCAC tRAC tOLZ
tOED Data tOEZ
Upper output
Data tOED
Lower input Lower output
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Lower byte read-modify-write waveform
tRWC tRAS tRPC tCSH tRCD tCRP tCAS tRSH tRAL tACS tRAH tCAH tCRP
tCRP
UCAS
LCAS
tRAD tASR
Address
Column address tRWD tAWD tRCS tCWD tOEA tCWL tRWL
Upper input Upper output Lower input
tRAC tCAC tCLZ tOLZ tOED
tOED Data tOEZ Data
Lower output
Hyper page mode read waveform
tRASP
tCSH tCRP tRCD tCAS tRHCP tHPC tRSH
UCAS, LCAS
tRAD tASR tRAH
tRAL tASC address tRCS address tCAH address tRCH tOEA tOEA tCPA tCPA Data tOLZ tOEZ tOEZ tOFF tRRH
Address
tRAC tCLZ tCAC
Data tCLZ
Data tCLZ
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Hyper page mode byte write waveform
tRASP tRSH tCAS tHPC tHPC tCRP tCAS tRAH tRAD tASC Column tRCS tCAH tCAH Column tASC tRAL tCAH tASC Column tRCH tRPC tCRP
tCSH
UCAS
tCRP
tRCD
tCAS
LCAS
tASR
Address
tOEA tOEA tCAC tCLZ tCPA tOEA tRRH
tOLZ tOEZ Data tRAC tCAC tCLZ tOLZ tCAC tCLZ tCPA
Lower
tOEZ Data
tOFF tOEZ Data
Upper
tOLZ
Hyper page mode early write waveform
tRASP tRAH tRWL tCSH tCAS tASC tWCS tRAL address address address tCWL tWCH tOEH tCAH tRSH
tCRP tRCD
UCAS, LCAS
tASR tRAD address
Address
tHDR Data Data Data tOED
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Hyper page mode byte early write waveform
tRASP tRSH tCAS tCRP tCAS tRAD tRAH tASR tASC Column tRAL tCAH tASC Column tCAH tASC Column tRWL tWCH tWCS tCWL tWCH tWCS tCWL tWCS tCWL tWCH tRPC
tCSH tCRP tRCD tCAS tCRP
UCAS
LCAS
tCAH
Address
Data Data Data
Lower Upper
Hyper page mode read-modify-write waveform
tRASP
tHPRWC tCSH tRCD tCAS tRAD tASR tRCS tRAH tASC tCAH tRWD tCWD tAWD tASC tCWL tCWD tCAH tASC tCRP
UCAS, LCAS Address
tRAL tCAH tCPWD tCWD tAWD tRWL tCWL
address
tOEA tOEZ tCLZ tCAC Data Data Data Data tCPA tCLZ tCAC Data Data tCLZ tCAC tOED tOEA
tRAC
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before refresh waveform
tRAS
tRPC tCSR tCHR
UCAS, LCAS
OPEN
only refresh waveform
tRAS tRPC
UCAS, LCAS Address
tCRP
tASR address
tRAH
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Hyper page mode byte read-modify-write waveform
tRASP
tCSH tRCD tCRP tCAS tRSH tCAS
tCRP
UCAS
tCAS
LCAS
tRAL tRAD tRAH tASR tASC tAWD tCWD tRWD tCPWD tCWD tCWL tAWD tCPWD tCWL tOEA tOED tCPA tCAC tCLZ Data Data tOEZ tOEA tCAH tASC tCAH tAWD tASC tAWD tCWD tCWL tRWL tAWD tCAH
Address
tCAH
tOEA
tOED
Upper input
tRAC tCAC tCLZ Data tOEZ Data
Upper output
tOED
Lower input
tCPA tOEZ tCAC tCLZ Data
Lower output
Data
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Hidden refresh waveform (read)
tRAS tCHR tRCD tRSH tCRP tRAS
tCRP
tRAD tRAH tASR tASC tRCS address tRRH tOEA tCAH
Address
tRAC tCAC tCLZ tOEZ Data tOFF
Hidden refresh waveform (write)
tRAS tCHR
tCRP tRCD tRSH
UCAS, LCAS
tRAD tRAH tASR tASC address tWCR tWCS tWCH address tRWL tRAL tCAH
Address
tDHR Data
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before refresh counter test waveform
tRAS tRSH
tCSR tCPT tCHR
UCAS, LCAS
tCAS
tASC tCAH
tRAL
Address
address tCAC tCLZ tOFF tOEZ Data tRCS tRRH tRCH
Read cycle
tROH tOEA
tRWL tCWL tWCH tWCS
Write cycle
Data
tRCS tCWD tAWD
tCWL
tRWL
Read-Write cycle
tOEA tOED
tCLZ tCAC tOEZ Data Data
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CAS-before-RAS self refresh cycle
W5$66 W536
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Package dimensions
42-pin
0.148 0.115 0.032 0.020 0.013 1.080
0.128 0.025 0.105 0.026 0.015 0.007 1.070
Seating Plane
0.370 0.395 0.435 0.405 0.445
0.050
50-pin TSOP (mm) (mm) 0.05 0.95 0.30 0.12 20.85 10.03 11.56 1.05 0.45 0.21 21.05 10.29 11.96
TSOP
0.80 (typical) 0.40 0.60
0-5°
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Capacitance
Parameter Input capacitance capacitance Symbol CIN1 CIN2 Signals RAS, UCAS, LCAS, DQ15
MHz, Room temperature Test conditions Vout Unit
AS4LC1M16E5 ordering information
Package access time
Plastic SOJ, mil, 42-pin AS4LC1M16E5-50JC AS4LC1M16E5-50JI AS4LC1M16E5-60JC AS4LC1M16E5-60JI
TSOP mil, 44/50-pin
AS4LC1M16E5-50TC AS4LC1M16E5-50TI
AS4LC1M16E5-60TC AS4LC1M16E5-60TI
AS4LC1M16E5 part numbering system
DRAM prefix CMOS 3.3V CMOS 1M16E5 Device number access time Package: 42-pin 44/50-pin TSOP Temperature range C=Commercial, 70°C I=Industrial, -40°C 85°C
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