Megabit FLASH EEPROM DP5Z4MW16Pn3 PRELIMINARY DESCRIPTION:
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4Mx16, 200ns, STACK/PGA 30A161-24
Megabit FLASH EEPROM
DP5Z4MW16Pn3
PRELIMINARY DESCRIPTION:
DP5Z4MW16Pn3 `'SLCC'' devices revolutionary memory subsystem using Dense-Pac Microsystems' ceramic Stackable Leadless Chip Carriers (SLCC). Available unleaded, straight leaded, `'J'' leaded, gullwing leaded packages, mounted 50-pin co-fired ceramic substrate. Device packs 64-Megabits FLASH EEPROM area small 0.463 in2, while maintaining total height 0.349 inches. DP5Z4MW16Pn3 contains four individual FLASH EEPROM memory devices. Each SLCC hermetically sealed making module suitable commercial, industrial military applications. using SLCCs, `'Stack'' family modules offer higher board density memory than available with conventional through-hole, surface mount hybrid techniques.
DP5Z4MW16PY3
DP5Z4MW16PI3
FEATURES:
Organization: 4Meg Fast Access Times: 120, 150, 200ns (max.) Single Volt High-Density Symmetrically Blocked Architecture Sixteen Word Blocks Device Extended Cycling Capability 100K Write/Erase Cycles Automated Erase Program Cycles Command User Interface Status Register SRAM-Compatible Write Interface Hardware Data Protection Feature Erase Write Lockout during Power Transitions Packages Available: DP5Z4MW16PY3 SLCC DP5Z4MW16PI3 Straight Leaded SLCC DP5Z4MW16PH3 Gullwing Leaded SLCC DP5Z4MW16PJ3 `'J'' Leaded SLCC DP5Z4MW16PA3 Dense-SLCC
DP5Z4MW16PJ3
DP5Z4MW16PA3
DP5Z4MW16PH3
30A161-24 REV.
This document contains information product presently under development Dense-Pac Microsystems, Inc. Dense-Pac reserves right change products specifications herein without prior notice.
DP5Z4MW16Pn3
PRELIMINARY
Dense-Pac Microsystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
PIN-OUT DIAGRAM
LEADLESS SLCC STRAIGHT LEADED SLCC `'J'' LEADED SLCC GULLWING LEADED SLCC
DENSE-STACK
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NAMES
I/O0 I/O15
DP5Z4MW16Pn3
N.C.
ADDRESS INPUTS: memory address. Addresses internally latched during write cycle. DATA INPUT/OUTPUT: Input data command during Command Data Interface Register (CIR) write cycles. Outputs array, status identifier data appropriate read mode. Floated when chip de-selected outputs disabled. CHIP ENABLE INPUT: Activate device's control logic, Input buffers, decoders sense amplifiers. With high, device de-selected power consumption reduces Standby level upon completion current program erase operation. must select device. Device selection occurs with falling edge rising edge disables device. WRITE ENABLE: Controls writes Command Interface Register (CIR). active low. OUTPUT ENABLE: Gates device's data through output buffers during read cycle. active low. DEVICE POWER SUPPLY (+5.0 Volts ±10%) GROUND Connect
OPERATION
Flash memory reads, erases writes in-system local CPU. cycles from memory conform standard microprocessor cycles.
Table Operation
Mode Read
I/O0-I/O15 DOUT HIGH-Z HIGH-Z HIGH-Z 00C2H 00F1H
Output Disable Standby Deep Power-Down Device Identifier Write
Manufacturer Identifier
NOTES: address control pins. Command deferent Erase operations, Data program operations Selector Protect operations only successfully completed through proper command sequence. 11.5V 12.5V.
WRITE OPERATION
Commands written COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timing. serves interface between microprocessor internal chip operation. decipher Read Array, Read Silicon Erase Program command. event read command, simply points read path either array Silicon depending specific read command given. program erase cycle, informs write state machine that program erase been requested. During program cycle,
write state machine control program sequences will only respond status reads. During sector/chip erase cycle, will respond status reads erase suspend. After writhe state machine completed task, will allow respond full command set. stays read status register mode until microprocessor issues another valid command sequence. Device operations selected writing commands into CIR. Table below defines Megabit Flash family command.
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PRELIMINARY
Dense-Pac Microsystems, Inc.
DEVICE OPERATION
SILICON READ
Silicon Read mode allows reading binary code from device will identify manufacturer type. this intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate mode, programming equipment must force (11.5V 12.5V) address identifier bytes then sequenced from device outputs toggling address from addresses don't cares except manufacturer device codes also read command register, instance when device erased programmed system without access high voltage pin. command sequence illustrated Table
terminate operation, necessary write read/reset command sequence into CIR.
READ RESET COMMAND
read reset operation initiated writing read/reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. device remains enabled reads until contents altered valid command sequence. device will automatically power-up read/reset state. this case, command sequence required read data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
Table Command Definition
Command Sequence Cycles Req'd First Write Cycle Second Write Cycle Third Write Cycle Fourth Read/Write Cycle Address Data Fifth Write Cycle Sixth Write Cycle
Address Data Address Data Address Data
Address Data Address Data
Read/Reset Silicon Read Page/Byte Program Chip Erase Sector Erase Erase Suspend Erase Resume Read Status Register Clear Status Register Sleep Abort
5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H
2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H
5555H 5555H
2AAAH 2AAAH
5555H
00H/01H C2H/F1H
NOTES: Address Don't Care address commands except Programming Address (PA) Sector Address (SA). 5555H 2AAAH address command codes stand number starting from A14. operations defined Table Address memory location read. Address memory programmed. Addresses latched falling edge pulse. Address sector erased. combination will uniquely select sector. Data read from location during read operation. Data programmed location Data latched rising edge Data read from Status Register.
Table Silicon Code
Type
Manufacturer's Code Device Code
Code (HEX)
00C2H 00FIH
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
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PAGE PROGRAM
initiate Page Program mode, three-cycle command sequence required. There "unlock" write cycles. These followed writing page program command A0H. After three-cycle command sequence given, word load performed applying pulse input with (respectively) high. address latched falling edge whichever occurs last. data latched first rising edge Maximum words data loaded into each page same procedures outlined page program section below.
DP5Z4MW16Pn3
Table Sector Address*
Address Range [A0-A15] 00000H-0FFFFH 10000H-1FFFFH 20000H-2FFFFH 30000H-3FFFFH 40000H-4FFFFH F0000H-FFFFFH
WORD LOAD
Word loads used enter words page programmed. word load performed applying pulse input respectively) high. address latched falling edge whichever occurs last. data latched first rising edge SA15
device.
PROGRAM
page programmed should have page erase state first, i.e. performing sector erase suggested before page programming performed. device programmed page basis. word data within page changed, data entire page loaded into device. word that loaded during programming page will still erase state (i.e. FFH). Once words page loaded into device, they simultaneously programmed during internal programming period. After first data word been loaded into device, successive words entered same manner. Each word programmed must have high transition within 30µs high transition preceding word. specify page address, i.e. device page-aligned words boundary page address must valid during each high transition specify word address within page. word loaded order; sequential loading required. high transition detected within last high transition, load period will internal programming period will start. auto page program terminates when status I/O7 which time device stays read status register mode until contents altered valid command sequence. (Refer Table Figure
SECTOR ERASE
Sector erase six-bus cycle operation. There "unlock" write cycles. These followed writing set-up command 80H. more "unlock" write cycles then followed sector erase command 30H. sector address latched falling edge while command (data) latched rising edge Sector erase does require user program device prior erase. system required provide controls timings during these operations. automatic sector erase begins rising edge last pulse command sequence terminates when status I/O7 which time device stays read status register mode. device remains enabled read status register mode until contents altered valid command sequence. (Refer Tables Figures
ERASE SUSPEND
This command only meaning while executing SECTOR CHIP erase operations, therefore will only responded during SECTOR CHIP erase operation. After this command been executed, will initiate suspend erase operations, then return Read Status Register mode. will I/O6 "1". Once reached Suspend state, will I/O7 "1". this time, allows respond Read Array, Read Status Register, Abort Erase Resume commands only. this mode, will respond other commands. will continue run, idling SUSPEND state, regardless state input control pins.
CHIP ERASE
Chip erase six-bus cycle operation. There "unlock" write cycles. These followed writing "set-up" command 80H. more "unlock" write cycles then followed chip erase command 10H. Chip erase does require user program device prior erase. automatic erase begins rising edge last pulse command sequence terminates when status I/O7 which time device stays read status register mode until contents altered valid command sequence. (Refer Tables Figures
30A161-24 REV.
ERASE RESUME
This command will cause clear suspend state I/O6 "0", only Erase Suspend command previously used. Erase Resume will have effect other conditions.
READ STATUS REGISTER COMMAND
module contains Status Register which read determine when program erase operation complete, whether that operation completed successfully. status register read time writing Read Status command CIR. After writing this command, subsequent read operations output data from status register, until another valid command written CIR. Read Array command must written return Read Array mode.
DP5Z4MW16Pn3
PRELIMINARY
status register bits output I/O2 I/O7 (Table I/O0-I/O1 I/O8-I/O15 should noted that status register latched falling edge whichever occurs last read cycle. This prevents possible errors which might occur contents status register change while reading status register. must toggled with each subsequent status read, completion program erase operation will evident. Status Register interface between microprocessor Write State Machine (WSM). When active, this register will indicate status WSM, will also hold bits indicating whether successful performing desired operation. sets status bits four through seven clears bits seven, cannot clear status bits four five. Erase fail Program fail status detected, Status Register cleared until Clear Status Register command written. device automatically outputs Status Register data when read after Chip Erase, Sector Erase, Page Program Read Status Command write cycle. default state Status Register after power-up return from deep power-down mode (I/O7, I/O6, I/O5, I/O4) 1000B. I/O3 depends sector-protect status, changed Clear Status Register Command Write State Machine. I/O2 depends Sleep status, During Sleep mode Abort mode I/O2 "1"; I/O2 reset Read Array command.
Dense-Pac Microsystems, Inc.
Table allowing system software control resetting these bits, several operations performed (such cumulatively programming several pages erasing multiple blocks sequence). Status register then read determine error occurred during that programming erasing series. This adds flexibility device programmed erased. Additionally, once program (erase) fail happens program (erase) operation performed further. program (erase) fail must reset system software before further page program sector (chip) erase attempted. clear status register, Clear Status Register command written CIR. Then, other command issued CIR. Note again that before read cycle initiated, Read command must written specify whether read data come from Array, Status Register Silicon
SLEEP MODE
device features software controlled low-power modes: Sleep Abort modes. Sleep mode allowable during current operations except that once Suspend command issued, Sleep command ignored. Abort mode executed only during page Programming Chip/Sector Erase mode. activate Sleep mode, three-bus cycle operation required. command (refer Table puts device Sleep mode. Once Sleep mode CMOS input level applied, power device reduced deep power-down current levels. only threshold condition, input leakage, output leakage. Sleep command allows device COMPLETE current operations before going into Sleep mode. Once current operation done, device stays read status register mode. status
CLEAR STATUS REGISTER
Erase fail status (I/O5) Program fail status (I/O4) write state machine, only reset system software. These bits indicate various failure conditions (see
Table Status Register
STATUS
PROGRAM PROGRESS ERASE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
Note
SUSPEND (NOT COMPLETE) SUSPEND (COMPLETE) PROGRAM ERASE
COMPLETE FAIL
PROGRAM ERASE
AFTER CLEARING STATUS REGISTER
NOTES: I/O7: Write State Machine Status Ready, Busy I/O6: Erase Suspend Status Suspend, Suspend I/O5: Erase Fail Status Fail Erase, Successful Erase I/O4: Program Fail Status Fail Program, Successful Program I/O3: Sector-Protect Status (Not Used) I/O2: Sleep Status Device Sleep Status, Device Sleep Status I/O1 I/O0 Reserved further enhancements. These bits reserved future use; mask them when polling Status Register.
Program Status status during Page Programming Sector Unprotect mode. Erase Status status during Sector/Chip Erase Sector Protection mode. Suspend Status both Sector Chip Erase mode. Fail Status (I/O4 I/O5) provided during Page Program Sector/Chip Erase modes respectively. I/O2 depends whether device Sleep mode not. Once Sleep mode, I/O2 "1", reset read array command only.
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registers reset during sleep command. Program Erase fail have been during program/erase mode device retry exceeds maximum count. During Sleep mode, status registers, Silicon codes remain valid still read. device Sleep Status I/O2 will indicate that device sleep mode. Write Read Array command wakes device Sleep mode, I/O2 reset device returns standby current level.
DP5Z4MW16Pn3
that exit during power transitions. During power-up device automatically resets internal state machine read array mode. Also, with control register architecture, alterations memory contents only occurs after successful completion specific multi-bus cycles command sequences. device also incorporates several features prevent inadvertent write cycles resulting from power-up power-down transitions system noise.
ABORT MODE
activate Abort mode, three-bus cycle operation required. command (refer Table only stops page program Sector/Chip erase operations currently progress puts device Sleep mode. unlike Sleep command, program erase operation will completed. Since data some page/sectors longer valid incomplete program erase operation, program fail (I/O4) erase fail (I/O5) will set. After abort command executed with CMOS input levels applied, device current reduced same level deep power-down sleep modes. Device stays read register mode. During Abort mode, status register, Silicon codes remain valid still read. device Sleep Status I/O2 will indicate that device sleep mode.
WRITE INHIBIT
avoid initiation write cycle during power-up power-down, write cycle locked less than (=3.2V, typically 3.5V). LKO, command register disabled internal program/erase circuits disabled. Under this condition device will reset read mode. Subsequent writes will ignored until level greater than LKO. logically correct prevent unintentional write when above LKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses less than 10ns (typical) will initiate write cycle.
LOGICAL INHIBIT
Writing inhibited holding VIH. initiate write cycle must logical zero while logical one.
DATA PROTECTION
device designed offer protection against accidental erasure programming caused spurious system level signals
ERASE PROGRAMMING PERFORMANCE
PARAMETER
Chip/Sector Erase Time Page Programming Time Chip Program Time Erase/Program Cycles Byte Program Time 1Mx16 device. Module program time 10,000
LIMITS
MIN. TYP. MAX.
UNITS
Cycles
2000
LATCH CHARACTERISTICS
PARAMETER
Input Voltage with Respect pins except pins Input Voltage with Respect pins Current Includes pins except Test conditions: 5.0V, time
MIN.
-1.0 -1.0 -100
AMX. 13.5 +1.0 +100
UNITS
30A161-24 REV.
DP5Z4MW16Pn3
PRELIMINARY
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
Symbol
ABSOLUTE MAXIMUM RATINGS
Unit
Characteristic
Supply Voltage Input Voltage Input HIGH Voltage Operating Temperature
Min. Typ.
-0.52
Max.
VDD+0.5 +125 12.5
Symbol
TSTC TBIAS IOUT VI/O
Parameter
Storage Temperature Temperature Under Bias Operating Temperature Output Short Circuit Current Input/Output Voltage Supply Voltage
Value
+125 +125 +125 -0.5 +7.0 -0.5 +7.0
Unit
I.D. Input/Output
11.5
CAPACITANCE 25°C, 1.0MHz
Symbol
CADR CI/O
OUTPUT CHARACTERISTICS
Symbol
Parameter
Address Input Chip Enable Write Enable Output Enable Data Input/Output
Max.
Unit
Condition
Parameter
HIGH Voltage Voltage
Condition
IOH= -400µA IOL=2.1mA
Min. Max. Unit
0.45
VIN2
OPERATING CHARACTERISTICS: Over operating ranges
Symbol
ISB1 ISB2 ICC1 ICC2 ICC3 ICC4 ICC5
Characteristics
Input Load Current Output Leakage Current Standby Current (CMOS) Standby Current (TTL) Read Current Read Current Erase Suspend Current Program Current Erase Current
Test Conditions
max., =VDD max., =VDD max., 0.2V max., max., Inputs VIH, 10MHz, max., Inputs VIH, 5MHz, Block Erase Suspend, Program Progress Erase Progress
Limits
Min. Typ. Max.
Unit
-3.0
VDD+0.3 0.45
Input Voltage Input High Voltage Output Voltage Output High Voltage 2.1mA -400mA
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DP5Z4MW16Pn3
FIGURE AUTOMATIC PAGE PROGRAM FLOW CHART
NOTE: Status Register
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DP5Z4MW16Pn3
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Dense-Pac Microsystems, Inc.
FIGURE AUTOMATIC CHIP ERASE FLOW CHART
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DP5Z4MW16Pn3
FIGURE AUTOMATIC SECTOR ERASE FLOW CHART
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DP5Z4MW16Pn3
PRELIMINARY
Dense-Pac Microsystems, Inc.
FIGURE ERASE SUSPEND/ERASE RESUME FLOW CHART
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DP5Z4MW16Pn3
TEST CONDITIONS
Input Pulse Levels Input Pulse Rise Fall Times Input Output Timing Reference Levels 0.45V 2.4V 10ns 0.8V, 2.0V
OUTPUT LOAD
Load
30pF
Parameters Measured
except tOLZ tDF,
OUTPUT LOAD
DEVICE UNDER TEST
1.8K
6.2K
DIODES IN3064 Equivalent
Including Probe Capacitance.
INPUT OUTPUT REFERENCE WAVEFORM
test inputs driven (2.4 TTL) Logic "1'' (0.45 TTL) Logic `'0''. Input timing begins (2.0 TTL) (0.8 TTL). Output timing ends Input rise fall times (10% ()%) 10ns.
Operating Conditions Characteristics Read Cycle:
Symbol
tACC
Parameter
Address Output Delay Chip Enable Output Delay Output Enable Output Delay Output Enable Output Delay Address Output Hold
120ns
Min. Max.
Over operating ranges 150ns 200ns
Max. Min. Max.
Min.
Unit
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DP5Z4MW16Pn3
PRELIMINARY
Dense-Pac Microsystems, Inc.
Figure READ CYCLE
ADDRESS
DATA
Operating Conditions Characteristics Write/Erase/Program Cycle: Over operating ranges
Symbol
tOES tCES tGHWL tWPH tBALC tBAL tSRA tCESR tVCS
Parameter
Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Chip Enable Setup Time Read Recovery Time before Write Chip Enable Setup Time Chip Enable Hold Hold Time Write Pulse Width Write Pulse Width HIGH Byte Address Load Cycle Byte Address Load Time Status Register Access Time Chip Enable Setup before Read Setup Time
120ns
Min. Max.
150ns
Min. Max.
200ns
Min. Max.
Unit
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DP5Z4MW16Pn3
Figure WRITE CYCLE
ADDRESS
DATA
Figure AUTOMATIC PAGE PROGRAM CYCLE
DATA
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PRELIMINARY
Dense-Pac Microsystems, Inc.
Figure AUTOMATIC SECTOR/CHIP ERASE CYCLE
DATA
NOTE:
Don't Care,
Sector Address, Refer page detail Page Program Operation.
Operating Conditions Characteristics Write/Erase/Program Operation Alternate Controlled Writes: Over operating ranges
Symbol
tOES tCES tGHWL tCPH tVCS Write Cycle time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Chip Enable Setup time Read Recovery Time before Write Write Enable Setup Write Enable Hold Time Chip Enable Pulse Width Chip Enable Pulse Width High Setup time
Parameter
120ns
Min. Max.
150ns
Min. Max.
200ns
Min. Max.
Unit
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Dense-Pac Microsystems, Inc. PRELIMINARY
Figure COMMAND WRITE TIMING
DP5Z4MW16Pn3
(Alternate Controlled)
ADDRESS
DATA
Figure AUTOMATIC PAGE PROGRAM TIMING CYCLE
A15-A19
DATA
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PRELIMINARY
Dense-Pac Microsystems, Inc.
NOTES:
voltages with respect VSS.
-2.0V min. pulse width less than 20ns min. -0.5V level). Maximum voltage over shoot +14.0V periods less than 20ns. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. This parameter guaranteed 100% tested. currents unless otherwise noted. Typical values 5.0V, 25°C. These currents valid product versions (package speeds.). ICC3 specified with device de-selected. device read while erase suspend mode, current draw ICC3 ICC1/ICC2. min. -1.0V pulse width 50ns. min. -2.0V pulse width 20ns. Refer page detail Page Program Operation.
WAVEFORM
Data Valid
Transition from HIGH
Transition from HIGH
Data Undefined Don't Care
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Leadless SLCC) MECHANICAL DRAWING
DP5Z4MW16Pn3
Straight Leaded SLCC) MECHANICAL DRAWING
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DP5Z4MW16Pn3
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`'J'' Leaded SLCC) MECHANICAL DRAWING
Gullwing Leaded SLCC) MECHANICAL DRAWING
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PGA) MECHANICAL DRAWING
DP5Z4MW16Pn3
ORDERING INFORMATION
(714) 898-0007
30A161-24 REV.
7321 Lincoln Way, Garden Grove, California 92841-1431 (800) 642-4477 FAX: (714) 897-1772 http://www.dense-pac.com
Dense-Pac Microsystems, Inc.
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