File Number 902.2 CMOS Analog Multiplexers/Demultiplexers with Lo
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CD4051B, CD4052B, CD4053B
File Number 902.2
CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion
CD4051B, CD4052B, CD4053B analog multiplexers digitally-controlled analog switches having impedance very leakage current. Control analog signals 20VP-P achieved digital signal amplitudes 4.5V -VSS -VEE controlled; -VDD level differences above 13V, -VDD least 4.5V required). example, +4.5V, -13.5V, analog signals from -13.5V +4.5V controlled digital inputs These multiplexer circuits dissipate extremely quiescent power over full -VDD -VDD supply-voltage ranges, independent logic state control signals. When logic present inhibit input terminal, channels off. CD4051B single 8-Channel multiplexer having three binary control inputs, inhibit input. three binary signals select channels turned connect inputs output. CD4052B differential 4-Channel multiplexer having binary control inputs, inhibit input. binary input signals select pairs channels turned connect analog inputs outputs. CD4053B triple 2-Channel multiplexer having three separate digital control inputs, inhibit input. Each control input selects pair channels which connected single-pole, double-throw configuration. When these devices used demultiplexers, "CHANNEL IN/OUT" terminals outputs "COMMON OUT/IN" terminals inputs.
Features
Wide Range Digital Analog Signal Levels Digital Analog. 20VP-P Resistance, (Typ) Over 15VP-P Signal Input Range -VEE High Resistance, Channel Leakage ±100pA (Typ) -VEE Logic-Level Conversion Digital Addressing Signals (VDD -VSS 20V) Switch Analog Signals 20VP-P (VDD -VEE 20V) Matched Switch Characteristics, (Typ) -VEE Very Quiescent Power Dissipation Under DigitalControl Input Supply Conditions, 0.2µW (Typ) -VSS -VEE Binary Address Decoding Chip Parametric Ratings Tested Quiescent Current Maximum Input Current Over Full Package Temperature Range, 100nA 25oC Break-Before-Make Switching Eliminates Channel Overlap
Applications
Analog Digital Multiplexing Demultiplexing Conversion Signal Gating
Ordering Information
PART NUMBER CD4051BF, CD4052BF, CD4053BF CD4051BE, CD4052BE, CD4053BE CD4051BM, CD4052BM, CD4053BM TEMP. RANGE (oC) PACKAGE PKG.
CERDIP F16.3
PDIP
E16.3
SOIC
M16.15
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. Copyright Harris Corporation 1998
CD4051B, CD4052B, CD4053B Pinouts
CD4051B (PDIP, CERDIP, SOIC) VIEW
CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT COMMON OUT/IN CHANNELS IN/OUT
CD4052B (PDIP, CERDIP) VIEW
CHANNELS IN/OUT
CHANNELS IN/OUT
CHANNELS IN/OUT
OUT/IN
COMMON OUT/IN
CD4053B (PDIP, CERDIP) VIEW
IN/OUT OUT/IN IN/OUT OUT/IN OUT/IN IN/OUT
Functional Block Diagrams
CD4051B
CHANNEL IN/OUT
COMMON OUT/IN
LOGIC LEVEL CONVERSION
BINARY DECODER WITH INHIBIT
CD4051B, CD4052B, CD4053B Functional Block Diagrams
(Continued) CD4052B
CHANNELS IN/OUT
COMMON OUT/IN COMMON OUT/IN
LOGIC LEVEL CONVERSION
BINARY DECODER WITH INHIBIT
CHANNELS IN/OUT
CD4053B
BINARY DECODERS WITH INHIBIT
LOGIC LEVEL CONVERSION
IN/OUT COMMON OUT/IN
COMMON OUT/IN
COMMON OUT/IN
inputs protected standard CMOS protection network
CD4051B, CD4052B, CD4053B
TRUTH TABLES INPUT STATES INHIBIT CD4051B CD4052B INHIBIT CD4053B INHIBIT Don't Care None None None "ON" CHANNEL(S)
CD4051B, CD4052B, CD4053B
Absolute Maximum Ratings Supply Voltage Voltages Referenced Terminal -0.5V Input Voltage Range -0.5V +0.5V Input Current, Input. ±10mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PDIP Package CERDIP Package. SOIC Package Maximum Junction Temperature (Ceramic Package) .175oC Maximum Junction Temperature (Plastic Package) .150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .265oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range -55oC 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
Common Conditions Here: Whole Table Full Temp. Range, VSUPPLY ±5V, 100, Unless Otherwise Specified (Note CONDITIONS LIMITS INDICATED TEMPERATURES (oC)
PARAMETER
UNITS
SIGNAL INPUTS (VIS) OUTPUTS (VOS) Quiescent Device Current, Drain Source Resistance Change Resistance (Between Channels), Channel Leakage Current: Channel (Max) Channels (Common OUT/IN) (Max) Capacitance: Input, Output, CD4051 CD4052 CD4053 Feedthrough CIOS Propagation Delay Time (Signal Input Output 200k, 50pF, 20ns 3000 1200 3000 1300 0.04 0.04 0.04 0.08 ±0.01 1050 ±100 (Note
±100 (Note
±1000 (Note
CD4051B, CD4052B, CD4053B
Electrical Specifications
Common Conditions Here: Whole Table Full Temp. Range, VSUPPLY ±5V, 100, Unless Otherwise Specified (Continued) (Note CONDITIONS LIMITS INDICATED TEMPERATURES (oC) PARAMETER UNITS
CONTROL (ADDRESS INHIBIT), through through Input High Voltage, Input Voltage, Channels Input Current, (Max) Propagation Delay Time: Address-to-Signal 20ns, (Channels 50pF, OFF) Figures Propagation Delay Time: Inhibit-to-Signal 20ns, (Channel Turning 50pF, Figure Propagation Delay Time: Inhibit-to-Signal (Channel Turning OFF) Figure 20ns, 50pF, Input Capacitance, (Any Address Inhibit Input) NOTE: Determined minimum feasible leakage measurement automatic testing. ±0.1 ±0.1 ±10-5 ±0.1
Electrical Specifications
TEST CONDITIONS PARAMETER Cutoff (-3dB) Frequency Channel (Sine Wave Input) (Note 20Log Common OUT/IN CD4053 CD4052 CD4051 Channel LIMITS UNITS
CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS PARAMETER Total Harmonic Distortion, (Note (Note (Note LIMITS 0.12 UNITS Common OUT/IN CD4053 CD4052 CD4051 Channel Between Channels Between Sections, CD4052 Only Measured Common Measured Channel mVPEAK mVPEAK
VSS, 1kHz Sine Wave -40dB Feedthrough Frequency (All Channels OFF) (Note 20Log 40dB -40dB Signal Crosstalk Frequency (Note 20Log 40dB
Between Sections, CD4053 Only Address-or-Inhibit-to-Signal Crosstalk (Note
20ns, (Square Wave) NOTES: Peak-to-Peak voltage symmetrical about Both ends channel.
Typical Performance Curves
CHANNEL RESISTANCE CHANNEL RESISTANCE 125oC
125oC 25oC -55oC
25oC -55oC
INPUT SIGNAL VOLTAGE
-7.5
-2.5 INPUT SIGNAL VOLTAGE
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
CD4051B, CD4052B, CD4053B Typical Performance Curves
CHANNEL RESISTANCE CHANNEL RESISTANCE 25oC
(Continued)
125oC
25oC -55oC
-7.5
-2.5
-7.5
-2.5
INPUT SIGNAL VOLTAGE
INPUT SIGNAL VOLTAGE
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
OUTPUT SIGNAL VOLTAGE 25oC 100k,
FIGURE CHANNEL RESISTANCE INPUT SIGNAL VOLTAGE (ALL TYPES)
POWER DISSIPATION PACKAGE (µW)
25oC ALTERNATING PATTERN 50pF
TEST CIRCUIT CD4029
15pF
CD4051
INPUT SIGNAL VOLTAGE
SWITCHING FREQUENCY (kHz)
FIGURE CHARACTERISTICS CHANNELS (CD4051B)
FIGURE DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4051B)
POWER DISSIPATION PACKAGE (µW)
POWER DISSIPATION PACKAGE (µW)
25oC ALTERNATING PATTERN 50pF
15pF
CD4029 CD4052
TEST CIRCUIT
25oC ALTERNATING PATTERN 50pF
TEST CIRCUIT CD4053
15pF
SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
FIGURE DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4052B)
FIGURE DYNAMIC POWER DISSIPATION SWITCHING FREQUENCY (CD4053B)
CD4051B, CD4052B, CD4053B Test Circuits Waveforms
7.5V
7.5V
-7.5V
-10V
NOTE: ADDRESS (digital-control inputs) INHIBIT logic levels are: VDD. analog signal (through swing from VDD. FIGURE TYPICAL BIAS VOLTAGES
20ns TURN-ON TIME TURN-OFF TIME
20ns
20ns
20ns
TURN-OFF TIME tPHZ TURN-ON TIME
FIGURE WAVEFORMS, CHANNEL BEING TURNED
FIGURE WAVEFORMS, CHANNEL BEING TURNED
CD4051
CD4052
CD4053
FIGURE CHANNEL LEAKAGE CURRENT CHANNEL
CD4051B, CD4052B, CD4053B Test Circuits Waveforms (Continued)
CD4051
CD4052
CD4053
FIGURE CHANNEL LEAKAGE CURRENT CHANNELS
OUTPUT
OUTPUT CD4052 CD4053
OUTPUT
CD4051
CLOCK
CLOCK
CLOCK
FIGURE PROPAGATION DELAY ADDRESS INPUT SIGNAL OUTPUT
OUTPUT 50pF CLOCK
OUTPUT 50pF CLOCK
OUTPUT 50pF
CLOCK
tPHL tPLH CD4051
tPHL tPLH CD4052
tPHL tPLH CD4053
FIGURE PROPAGATION DELAY INHIBIT INPUT SIGNAL OUTPUT
MEASURE "OFF" CHANNELS (e.g., CHANNEL MEASURE "OFF" CHANNELS (e.g., CHANNEL
CD4051B
CD4052B
CD4053B
MEASURE "OFF" CHANNELS (e.g., CHANNEL
FIGURE INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
CD4051B, CD4052B, CD4053B Test Circuits Waveforms (Continued)
KEITHLEY DIGITAL MULTIMETER "ON" RANGE
PLOTTER
CD4051 CD4053
CD4052
H.P. MOSELEY 7030A
FIGURE QUIESCENT DEVICE CURRENT
FIGURE CHANNEL RESISTANCE MEASUREMENT CIRCUIT
CD4051 CD4053 CD4052
NOTE: Measure inputs sequentially, both connect unused inputs either
NOTE: Measure inputs sequentially, both connect unused inputs either
FIGURE INPUT CURRENT
CHANNEL 5VP-P CHANNEL CHANNEL COMMON
5VP-P
CHANNEL
CHANNEL
FIGURE FEEDTHROUGH (ALL TYPES)
FIGURE CROSSTALK BETWEEN CHANNELS (ALL TYPES)
5VP-P
CHANNEL
CHANNEL
FIGURE CROSSTALK BETWEEN DUALS TRIPLETS (CD4052B, CD4053B)
CD4051B, CD4052B, CD4053B Test Circuits Waveforms (Continued)
DIFFERENTIAL SIGNALS CD4052 CD4052
COMMUNICATIONS LINK
DIFF. AMPLIFIER/ LINE DRIVER
DIFF. RECEIVER
DIFF. MULTIPLEXING
DEMULTIPLEXING
FIGURE TYPICAL TIME-DIVISION APPLICATION CD4052B
Special Considerations
applications where separate power sources used drive signal inputs, current capability should exceed VDD/RL effective external load). This provision avoids permanent current flow clamp action supply when power applied removed from CD4051B, CD4052B CD4053B.
CD4051B CD4556 COMMON OUTPUT
CD4051B
CD4051B
FIGURE 24-TO-1 ADDRESSING
CD4051B, CD4052B, CD4053B Dual-In-Line Plastic Packages (PDIP)
INDEX AREA
E16.3 (JEDEC MS-001-BB ISSUE
LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES Rev. 12/93
0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
BASE PLANE SEATING PLANE 0.010 (0.25)
NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm).
0.100 0.300 0.115 0.430 0.150
2.54 7.62 2.93 10.92 3.81
CD4051B, CD4052B, CD4053B Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A-DBASE METAL -Bbbb BASE PLANE SEATING PLANE SECTION LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION
LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL 0.014 0.014 0.045 0.023 0.008 0.008 0.220 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS 0.36 0.36 1.14 0.58 0.20 0.20 5.59 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES Rev. 4/94
eA/2
eA/2
0.100 0.300 0.150 0.125 0.015 0.005 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 7.62 3.81 3.18 0.38 0.13 5.08 1.52 105o 0.38 0.76 0.25 0.038
NOTES: Index area: notch identification mark shall located adjacent shall located within shaded area shown. manufacturer's identification shall used identification mark. maximum limits lead dimensions shall measured centroid finished lead surfaces, when solder plate lead finish applied. Dimensions apply lead base metal only. Dimension applies lead plating finish thickness. Corner leads N/2, N/2+1) configured with partial lead paddle. this configuration dimension replaces dimension This dimension allows off-center lid, meniscus, glass overrun. Dimension shall measured from seating plane base plane. Measure dimension four corners. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH.
CD4051B, CD4052B, CD4053B Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M16.15 (JEDEC MS-012-AC ISSUE
LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 1.35 0.10 0.33 0.19 9.80 3.80 1.75 0.25 0.51 0.25 10.00 4.00 NOTES Rev. 12/93
0.0532 0.0040 0.013 0.0075 0.3859 0.1497
0.0688 0.0098 0.020 0.0098 0.3937 0.1574
0.10(0.004)
0.25(0.010)
0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050
1.27 5.80 0.25 0.40 6.20 0.50 1.27
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
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