Data Sheet August 2005 FN3931.1 Noise, High Performance Operation

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Data Sheet August 2005 FN3931.1 Noise, High Performance Operation

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HA-5101/883
Data Sheet August 2005 FN3931.1
Noise, High Performance Operational Amplifier
HA-5101/883 dielectrically isolated operational amplifier featuring noise high performance. This amplifier excellent noise voltage density 4.5nV/Hz (max) 1kHz. unity gain stable HA-5101/883 yields 10MHz unity gain bandwidth 6V/µs slew rate. characteristics HA-5101/883 assure accurate performance. (max) offset voltage externally adjustable offset voltage drift just 3µV/°C. bias currents (200nA max) reduce input current errors high open loop voltage gain 100kV/V, over temperature, increases loop gain distortion amplification. HA-5101/883 ideal audio applications, especially low-level signal amplifiers such microphone, tape head preamplifiers. Additionally, well suited distortion oscillators, noise function generators high filters.
Features
This Circuit Processed Accordance MIL-STD-883 Fully Conformant Under Provisions Paragraph 1.2.1. Noise Voltage 1kHz 4.5nV/Hz Noise Current 1kHz 3pA/Hz Wide Unity Gain Bandwidth 10MHz High Gain (Full Temp) .100kV/V (Room Temp) 1MV/V Slew Rate. 6V/µs High CMRR/PSRR (Full Temp) 80dB High Output Drive Capability (Full Temp) 25mA
Applications
High Quality Audio Preamplifiers High Active Filters Noise Function Generators Distortion Oscillators Noise Comparators
Ordering Information
PART NUMBER HA7-5101/883 5962-89636012A TEMP. RANGE (°C) PACKAGE CerDIP PKG. DWG. F8.3A
Ceramic J20.A
Pinouts
HA7-5101/883 (CERDIP) VIEW
5962-896360 (CLCC) VIEW
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 1994, 2005. Rights Reserved other trademarks mentioned property their respective owners.
HA-5101/883
Absolute Maximum Ratings
Voltage Between Terminals Differential Input Voltage Voltage Either Input Terminal VInput Current 25mA Output Short Circuit Duration. Indefinite Junction Temperature (TJ). +175°C Storage Temperature Range .-65°C +150°C Rating .<2000V Lead Temperature (Soldering 10s) +300°C
Thermal Information
Thermal Resistance (°C/W) (°C/W) Ceramic Package Ceramic Package. Package Power Dissipation Limit +75°C +175°C Ceramic Package .1.22W Ceramic Package. .1.35W Package Power Dissipation Derating Factor Above +75°C Ceramic Package .12.2mW/°C Ceramic Package. .13.5mW/°C
Operating Conditions
Operating Temperature Range -55°C +125°C Operating Supply Voltage ±15V VINcm
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
TABLE D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested ±15V, 100, 500k, VOUT Unless Otherwise Specified GROUP SUBGROUP TEMP (°C) Input Bias Current 100k 100k 100k 100k -27V VOUT +10V VOUT -10V +10V =+5V -25V VOUT -10V -10V +25V VOUT +10V +125, +125, +125, +125, +125, +125, +125, +125, +125, LIMITS -200 -325 -200 -325 -125 UNITS kV/V kV/V kV/V kV/V
PARAMETER Input Offset Voltage
SYMBOL
TEST CONDITIONS
Input Offset Current
Common Mode Range
+CMR
-CMR
Large Signal Voltage Gain
+AVOL
-AVOL
Common Mode Rejection Ratio
+CMRR
-CMRR
+125,
FN3931.1 August 2005
HA-5101/883
TABLE D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested ±15V, 100, 500k, VOUT Unless Otherwise Specified GROUP SUBGROUP TEMP (°C) -VOUT1 ±18V ±18V VOUT -15V ±18V VOUT +15V ±18V VOUT IOUT VOUT IOUT +10V, -15V +20V, -15V +15V, -10V +15V, -20V Note 50pF +1V/V +VOUT2 +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, LIMITS VIO-1 VIO-1 VIO+1 VIO+1 UNITS
PARAMETER Output Voltage Swing
SYMBOL +VOUT1
TEST CONDITIONS
-VOUT2
Output Current
+IOUT
-IOUT
Quiescent Power Supply Current
+ICC
-ICC
Power Supply Rejection Ratio
+PSRR
-PSRR
Offset Voltage Adjustment
+VIOAdj
-VIOAdj
TABLE A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested ±15V, 50pF, AVCL +1V/V, Unless Otherwise Specified GROUP SUBGROUP TEMP (°C) VOUT -200mV +125, +125, +125, +125, LIMITS UNITS V/µs V/µs
PARAMETER Slew Rate
SYMBOL
TEST CONDITIONS VOUT VOUT VOUT +200mV VOUT -200mV VOUT +200mV
Rise Fall Time
Overshoot
FN3931.1 August 2005
HA-5101/883
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized ±15V, 50pF, Unless Otherwise Specified LIMITS PARAMETER Differential Input Resistance Frequency Peak-to-Peak Noise Input Noise Voltage Density Input Noise Current Density Unity Gain Bandwidth Full Power Bandwidth Minimum Closed Loop Stable Gain Output Resistance Quiescent Power Consumption NOTES: Parameters listed Table controlled design process parameters directly tested final production. These parameters characterized upon initial design release, upon design changes. These parameters guaranteed characterization based upon data from multiple production runs which reflect within variation. Full Power Bandwidth guarantee based Slew Rate measurement using FPBW Slew Rate/(2VPEAK). Quiescent Power Consumption based upon Quiescent Supply Current test maximum. load outputs.) Offset adjustment range [VIO (Measured) ±1mV] minimum referred output. This test functionality only assure adjustment through SYMBOL EnP-P UGBW FPBW CLSG ROUT Open Loop VOUT IOUT TEST CONDITIONS 0.1Hz 10Hz 1000Hz 1000Hz 100mV VPEAK NOTES TEMP (°C) +125 +125 UNITS µVP-P nV/Hz pA/Hz
TABLE ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters Group Test Requirements Groups Endpoints *PDA applies Subgroup only. SUBGROUPS (SEE TABLES
FN3931.1 August 2005
HA-5101/883
FN3931.1 August 2005
HA-5101/883 Burn-in Circuits
CERAMIC MINI-DIP
CERAMIC
NOTES: ±5%, 1/4W (Min) 0.01µF/Socket (Min) 0.1µF/Row, (Min) 0.01µF/Socket, 1N4002 Equivalent/Board (V+) (V-)
FN3931.1 August 2005
HA-5101/883 Schematic
Q19B
QL41
OUTPUT
R17A
Q19A
3.65K
3.65K
R19A
R19B
FN3931.1 August 2005
HA-5101/883 Characteristics
DIMENSIONS mils ±1mil 1790 1780 483µm ±25.4µm METALLIZATION Type: Thickness: GLASSIVATION Type: Nitride (Si3N4) over Silox (SiO2, Phos.) Silox Thickness: Nitride Thickness: WORST CASE CURRENT DENSITY: 1.38 105A/cm2 SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5101/883
FN3931.1 August 2005
HA-5101/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A-DBASE METAL -Bbbb BASE PLANE SEATING PLANE SECTION LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION
LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL 0.014 0.014 0.045 0.023 0.008 0.008 0.220 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS 0.36 0.36 1.14 0.58 0.20 0.20 5.59 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 2.54 7.62 3.81 3.18 0.38 0.13 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES Rev. 4/94
eA/2
eA/2
0.100 0.300 0.150 0.125 0.015 0.005 0.200 0.060 105o 0.015 0.030 0.010 0.0015
NOTES: Index area: notch identification mark shall located adjacent shall located within shaded area shown. manufacturer's identification shall used identification mark. maximum limits lead dimensions shall measured centroid finished lead surfaces, when solder plate lead finish applied. Dimensions apply lead base metal only. Dimension applies lead plating finish thickness. Corner leads N/2, N/2+1) configured with partial lead paddle. this configuration dimension replaces dimension This dimension allows off-center lid, meniscus, glass overrun. Dimension shall measured from seating plane base plane. Measure dimension four corners. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH
FN3931.1 August 2005
HA-5101/883 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010
J20.A
MIL-STD-1835 CQCC1-N20 (C-2) CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL 0.060 0.050 0.022 0.006 0.342 0.100 0.088 0.028 0.022 0.358 MILLIMETERS 1.52 1.27 0.56 0.15 8.69 1.83 0.56 9.09 2.54 2.23 0.71 NOTES Rev. 5/18/94
0.072
0.200 0.100 0.342 0.358 0.358
5.08 2.54 9.09 9.09 5.08 2.54 0.38 1.02 0.51 1.14 1.14 1.91 0.08 1.40 1.40 2.41 0.38 9.09 1.27 8.69
0.010 PLANE PLANE
0.007
0.200 0.100 0.015 0.358 0.050 0.040 0.020 0.045 0.045 0.075 0.003 0.055 0.055 0.095 0.015
-FE1
NOTES: Metallized castellations shall connected plane terminals extend toward plane across least layers ceramic completely across ceramic layers make electrical connection with optional plane terminals. Unless otherwise specified, minimum clearance 0.015 inch (0.38mm) shall maintained between metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) Symbol maximum number terminals. Symbols "ND" "NE" number terminals along sides length "E", respectively. required plane terminals optional plane terminals used) shall electrically connected. corner shape (square, notch, radius, etc.) vary manufacturer's option, from that shown drawing. Chip carriers shall constructed minimum ceramic layers. Dimension controls overall package thickness. maximum dimension package height before being solder dipped. Dimensioning tolerancing ANSI Y14.5M-1982. Controlling dimension: INCH.
FN3931.1 August 2005
HA-5101
Data Sheet August 2005 FN3931.1
information contained following pages been developed through characterization Intersil Semiconductor application design information only. guarantee implied.
Typical Performance Curves
Unless Otherwise Specified: ±15V, +25°C
1500 INPUT NOISE CURRENT (pA/Hz)
INPUT NOISE VOLTAGE (nV/Hz)
FREQUENCY (Hz) CURRENT VOLTAGE
OFFSET VOLTAGE (µV)
1000
100K
TEMPERATURE (°C)
FIGURE NOISE SPECTRUM
FIGURE OFFSET VOLTAGE TEMPERATURE
25,000, ±15V (0.09nVP-P RTI) PEAK-TO-PEAK NOISE 0.1Hz 10Hz
25,000, ±15V (12.89mVP-P 0.52µVP-P RTI) PEAK-TO-PEAK TOTAL NOISE 0.1Hz 1MHz
HA-5101 Typical Performance Curves
INPUT OFFSET CURRENT (nA)
Unless Otherwise Specified: ±15V, +25°C (Continued)
BIAS CURRENT (nA)
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE INPUT OFFSET CURRENT TEMPERATURE
FIGURE INPUT BIAS CURRENT TEMPERATURE
MAXIMUM
SUPPLY CURRENT (mA) OFFSET CHANGE (µV)
MINIMUM TYPICAL
TIME
SUPPLY VOLTAGE (±V)
FIGURE INPUT OFFSET WARMUP DRIFT TIME (NORMALIZED ZERO FINAL VALUE) (SIX REPRESENTATIVE UNITS)
FIGURE SUPPLY CURRENT SUPPLY VOLTAGE
RISE TIME SLEW RATE (NORMALIZED)
RISE TIME (NORMALIZED) OUTPUT CURRENT (mA) +15mV -15mV +15mV -15mV VOUT ±15V ±15V TIME
SLEW RATE
50pF
TEMPERATURE (°C)
FIGURE SLEW RATE/RISE TIME TEMPERATURE
FIGURE SHORT CIRCUIT CURRENT TIME
FN3931.1 August 2005
HA-5101 Typical Performance Curves
(140) OPEN LOOP VOLTAGE GAIN V/V(dB) VERROR (120)
Unless Otherwise Specified: ±15V, +25°C (Continued)
100K (100)
2.65µs
(80)
TIME (1.5µs/DIV)
SUPPLY VOLTAGE (±V)
FIGURE OPEN-LOOP VOLTAGE GAIN SUPPLY VOLTAGE
FIGURE SETTLING WAVEFORM
CLOSED LOOP VOLTAGE GAIN (dB) 125°C PHASE -55°C PHASE -135 1V/V 50pF 100K FREQUENCY (Hz) -180 -225 100M 125°C GAIN -55°C GAIN PHASE SHIFT (DEGREES) GAIN (dB) 50pF 100K FREQUENCY (Hz) 100M
FIGURE CLOSED LOOP GAIN PHASE HIGH TEMPERATURES
FIGURE CLOSED-LOOP VOLTAGE GAIN FREQUENCY DIFFERENT CLOSED LOOP GAINS
FN3931.1 August 2005
HA-5101 Typical Performance Curves
PHASE SHIFT (DEGREES) VOLTAGE GAIN (dB) PHASE GAIN 100K 100M -120 FREQUENCY (Hz) 100K REJECTION RATIO (dB)
Unless Otherwise Specified: ±15V, +25°C (Continued)
-PSRR/CMRR
+PSRR -100
FREQUENCY (Hz)
FIGURE OPEN-LOOP GAIN/PHASE FREQUENCY
FIGURE REJECTION RATIOS FREQUENCY
VOUT ±3V, 50pF Timescale 500ns/Div., Scale: Input 5V/Div, Output 2V/Div FIGURE SLEW RATE WAVEFORM
Rise Time Overshoot VOUT +200mV, 50pF Timescale 20ns/Div. FIGURE SMALL SIGNAL WAVEFORM
FN3931.1 August 2005
HA-5101 Applications Information
Operation Supply
HA-5101 performs well exhibiting typical characteristics listed below:
IBIAS. AVOL ±3V) VOUT IOUT CMRR (VCM ±2.5V) PSRR (VCC 0.5V). Unity Gain Bandwidth Slew Rate. 3.7mA 0.5mV 56nA 106kV/V 3.7V 13mA 90dB 90dB 10MHz 7V/µs
(NOTE)
Offset Adjustment
following recommended adjust configuration:
+15V (NOTE) 100k -15V
NOTE: Proper decoupling always recommended, 0.1µF high quality capacitor should very near device's supply pins.
Input Protection
HA-5101 built-in back-to-back protection diodes which will limit differential input voltage approximately HA-5101 will used conditions where that voltage exceeded, then current limiting resistors must used. more than 25mA should allowed flow HA-5101's input.
Comparator Circuit
RLIM
RLIM
Output Saturation
When overdriven, output devices saturate sometimes take long time recover. Saturation avoided (sometimes) using circuits such
Choose RLIM Such That:
25mA
VSOURCE
saturation cannot avoided HA-5101 recovers from overdrive about 6.5µs (see photo).
Top: Input Bottom: Output, 5V/Div., 2µs/Div. Output overdriven negative recovers 6µs.
FN3931.1 August 2005
HA-5101
TABLE TYPICAL PERFORMANCE CHARACTERISTICS Device Characterized ±15V, 50pF, AVCL +1V/V, Unless Otherwise Specified PARAMETER Offset Voltage Offset Voltage Average Drift Offset Current Average Drift Input Bias Current Input Offset Current Differential Input Resistance Input Noise Voltage Density Versus Temperature Versus Temperature 10Hz 100Hz 1kHz Input Noise Current Density 10Hz 100Hz 1kHz Large Signal Voltage Gain VOUT ±10V TEST CONDITIONS TEMP (°C) +125 +125 +125 Slew Rate Full Power Bandwidth Rise Fall Times Overshoot Settling Time VOUT VPEAK 10V, (Note VOUT ±200mV VOUT ±200mV 0.1% Step 0.01% Step Output Short Circuit Current Output Resistance Supply Current Minimum Supply Voltage 10s, VOUT ±15V Open Loop Load Functional Operation Only, Other Parameters Will Vary +125 +125 +125 +125 0.52 400K DESIGN LIMITS Table Table Table Table Table Table Table Table Table Table Table Table UNITS µV/°C pA/°C nV/Hz nV/Hz nV/Hz pA/Hz pA/Hz pA/Hz V/µs
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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FN3931.1 August 2005

Data Sheet August 2005 FN3931.1 Noise, High Performance Operation

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