DN007 Applications Parallel printer port protection protection se

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

DN007 Applications Parallel printer port protection protection se

Datasheet Thumbnail

Top Searches for this datasheet

DN007
Applications Parallel printer port protection protection sensitive electronic equipment.
CHANNEL PROTECTION ARRAY
Features channel protection 15KV protection (HBM) contact, 15KV protection 1000-4-2 loading capacitance, typ. 24-pin QSOP package
ABSOLUTE MAXIMUM RATINGS
Product Description DN007 diode array designed provide channel protection electronic components subsystems. Each channel consists pair diodes which steers current pulse either positive (VP) negative (VN) supply. DN007 will protect against pulses Human Body Model, contact discharge International Standard IEC1000-4-2. This device particularly well-suited provide additional protection parallel printer ports. exhibits loading capacitance signal lines. SCHEMATIC CONFIGURATION
Diode Forward Current (Note 20mA Storage Temperature -65°C 150°C Operating Temperature Range 70°C Voltage Channel Input VN-0.5V VP+0.5V
Note Only diode conducting time.
STANDARD SPECIFICATIONS Param Min. Operating Supply Voltage 0.65 Diode Forward Voltage, 20mA, 25°C Diode reverse breakdown voltage, 25°C 000Top Diode (Cathode 19.0 28.0 000Bottom Diode (Anode Protection Peak Discharge Voltage Channel Input, in-system (Note 000Human Body Model, Method 3015 (Note 000Contact 1000-4-2 (Note -8KV 000Air Discharge 1000-4-2 (Note -15KV Channel Clamp Voltage 15KV HBM, 25°C 000Positive transients 000Negative transients Channel Leakage Current, 25°C Channel Input Capacitance (Measured MHz) Package Power Rating
(Notes
Typ.
0.85
+8KV +15KV
+13.0 -13.0 12pF 1.00W
Note Note Note Note
From pins only. bypassed with ceramic capacitor. Human Body Model MIL-STD-883, Method 3015, CDischarge=100pF, RDischarge=1.5K, VP=5.0V, VN=GND. This parameter guaranteed characterization only. Standard IEC1000-4-2 with CDischarge=150pF, RDischarge=330, VP=5V, VN=GND.
1998 California Micro Devices Corp. rights reserved. P/Active trademarks California Micro Devices. California Micro Devices manufactures products covered more U.S. Pat. Nos. 5,355,014, 5,370,766, 5,514,612, 5,706,163, other pending Corp. rights ©1993, 1998 California Micro Devicesapplications. reserved.
3/98
C0211297D
Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
STANDARD PART ORDERING INFORMATION Orde ring Part Style Tube Tape
QSOP PACDN007Q/T PACDN007Q/R
DN007
Pins
Part Mark
PDN007Q
Application Information order realize maximum protection against pulses with DN007, care must taken layout minimize parasitic series inductance Supply Ground rails. Refer Figure which illustrates case positive pulse applied between input channel Chassis Ground. parasitic series inductance back power supply represented voltage line being protected Forward voltage drop d(Iesd)/dt VSupply where Iesd current pulse, VSupply positive supply voltage.
PATH CURRENT PULSE Iesd
CHANNEL DN007
CHANNEL INPUT
current pulse rise from zero peak value very short time. example, consider case pulse that rises from zero Amps 1nS. Here d(Iesd)/dt approximated Iesd/t, 10/(1x10-9). each nano Henry series inductance (L1) will lead increment Similarly negative pulses, parasitic series inductance from ground rail will lead increased negative voltage line being protected. Another consideration output impedance power supply fast transient currents. Most power supplies exhibit much higher output impedance fast transient current spikes. equation above, VSupply term, reality, given (VDC Iesd Rout), where Rout nominal supply output voltage effective output impedance power supply respectively. example, would result increment peak Iesd 10A. mitigate this effect, high frequency bypass capacitor should connected between DN007 ground plane. value this bypass capacitor should chosen such that will absorb charge transferred pulse with minimal change Typically value range adequate IEC-1000-4-2, level contact discharge protection (8KV). Ceramic chip capacitors mounted with short printed circuit board traces good choice this application. Electrolytic capacitors should avoided they have poor high frequency characteristics. extra protection, connect zener diode parallel with bypass capacitor mitigate effects parasitic series inductance inherent capacitor. breakdown voltage zener diode should slightly higher than maximum supply voltage. general rule, DN007 should located close possible point entry expected electrostatic discharges. power supply bypass capacitor mentioned above should close DN006 possible, with minimum trace lengths power supply ground planes minimize stray series inductance.
1993, 1998 California Micro Devices Corp. rights reserved.
Topaz Street, Milpitas, California 95035
Figure
POSITIVE SUPPLY RAIL LINE BEING PROTECTED SYSTEM CIRCUITRY BEING PROTECTED GROUND RAIL CHASSIS GROUND
Tel: (408) 263-3214
Fax: (408) 263-7846
3/98
QSOP VIEW
DN007
Power Derating Curve
Package Dimensions, Power Dissipation Information Package QSOP Pins JEDEC MO137 inches 1.35 1.75 0.053 0.069 0.10 0.25 0.004 0.010 0.20 0.30 0.008 0.012 0.18 0.25 0.007 0.010 8.56 8.73 0.337 0.344 3.81 3.98 0.150 0.157 0.64 0.025 5.79 6.19 0.228 0.244 0.40 1.27 0.016 0.050 1.00W tube tape reel 2,500
©1993, 1998 California Micro Devices Corp. rights reserved. 3/98
Tel: (408) 263-3214 Fax: (408) 263-7846
Mechanical Specifications Lead Plating Tin-Lead Lead Material Copper Alloy Lead Coplanarity 0.004" (0.102mm) Substrate Material Silicon Body Material Molded Epoxy Flammability UL94V-0
Topaz Street, Milpitas, California 95035

DN007 Applications Parallel printer port protection protection se

Top Searches for this datasheet

Other recent searches