CMOS Gate Array CG61P Series This series features first gate
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CG61P
CMOS Gate Array
CG61P Series
This series features first gate array incorporating analog PLL. Four frames available capacity range from 300K: types provided analog PLLs low-frequency version MHz); other those high-frequency version (150 MHz).
Product Description
ASIC products have recently been adopted variety electronics equipment designed address diverse needs consumers. There also been recent demand PLLs with more advanced features. Analog PLL-mounted products have conventionally been based E/A, S/C, other design protocols that involve higher development costs longer prototyping (turnaround time). meet today's more diversified needs, FUJITSU successfully developed CG61P Series, market's first gate array incorporating analog PLL. device package, FUJITSU making consistent efforts achieve compact size lightweight, profile design.
Available number gates This series provides four frams, ranging from 300K. Package lineup Most packages surface-mounted plastic models LQFP/QFP. Table shows package lineup available with CG61P Series. future, bump chip carrier (BCC) will also included. Features package illustrated Fig.1. Analog mounted chip. options selected logic netthe low-frequency version 160MHz) high-frequency version (150 200MHz).
Photo Schematic View
Product Features
Process technology 0.35m CMOS gate three-layer wiring process. Typical gate delay time CG61P typical gate delay time 85ps (under 3.3V single power supply, 2-input NAND, F/O2, normal load). Supply voltage 3.3V±0.3V (The standard specifications; Similar voltage APLL specifications) Electrical characteristics shown Tables
2002
No.1
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CG61P
Fig.2 illustrates features analog PLL-incorporated CG61P.
Buffer Cell Crystal-Oscillator Circuit
Table Maximum Rating
VSS0V Parameter Supply Voltage Input Voltage1 Output Voltage Supply Terminal Current2 Symbol Rating VSS-0.5 VSS-0.5 VDD0.5 VSS-0.5 VDD4.0 VSS-0.5 VDD0.5 VSS-0.5 VDD0.5 L/H-State VSS-0.5 VDD4.0 Z-State CMOS Output IOL2 Output Current3 CMOS Output IOL12 CMOS Output IOL24 PCML Output Tolerant Type (IOL2, Overshoot Undershoot4 Ambient Storage Temperature
Operating Junction Temperature5
Three models under development; low-frequency version (32kHz), medium-frequency version 20MHz), high-frequency version 40MHz). them will equipped with oscillation shutdown option.
Table Recommended Operating Conditions
VDD3.3V±0.3V(Single Power Supply) Rating Parameter Supply Voltage CMOS Tolerant Normal Schmidt Normal Schmidt Symbol Min. Typ. Max. VDD0.3 Unit VSS0V
Unit L-Level Input Voltage
VDD1.0 VSS-1.0
H-Level Input Voltage
CMOS Normal Tolerant Schmidt
Operating Junction Temperature
Standard Type Plastic-55125
VDD2.5V±0.25V(Single Power Supply) Rating Parameter Symbol Normal Schmidt Normal Schmidt Min. 2.25 Typ.
VSS0V Unit
Max. 2.75 VDD0.3
-40125
Supply Voltage H-Level Input Voltage L-Level Input Voltage CMOS CMOS
1Voltage 1.1V greater should applied between differential input pins LVDS 2Allowable maximum supply current value steady-state condition 3Allowable maximum output current value steady-state condition less 5Continuous operation always guaranteed 6For V-tolerant type
Operating Junction Temperature
Table CG61P Package Lineup
CG61723P incorporated Package name LQFP48 LQFP64 LQFP80 LQFP100 LQFP120 LQFP144 LQFP176 LQFP208 TQFP100 TQFP120 QFP240 QFP256 70718 42/40 58/56 72/70 88/86 102/100 126/124 88/86 CG61134P 130372 58/56 72/70 88/86 102/100 126/124 152/150 88/86 CG61204P 207068 58/56 72/70 88/86 102/100 126/124 152/150 178/176 88/86 102/100 206/204 CG61304P 301184 72/70 88/86 102/100 126/124 152/150 178/176 88/86 102/100 206/204 220/218
1No. incorporated BCs: APLL domain included2Maximum signal counts: Shown presence/absence APLL Available, Development under consideration, supported
FIND Vol.20
No.1
2002
CG61P
Chip Configuration
parts device analog PLL-dedicated domain, logic circuit formed basic cells installed non-masking method. (Fig.2).
Development Support
same development tools FUJITSU CG61P Series used without addition/modification. e.g.: Superwindow (GISTA) Verilog-XL (Cadence Design Systems, Inc.) Composer (Concept) (Cadence Design Systems, Inc.) (ViewLogic Systems, Inc.) (Synopsys, Inc.)
Applicable Cells
unit cells, cells, RAMs FUJITSU CG61P Series applicable. domains available arrangement vary from series series.
Figure Features Package
BCC48
Comparison between outside dimensions FBGA (48-pin) Package Sizemm BCC48 FBGA48
BCCBump Chip Carrier
Packages available compact size equivalent bare chip.
Figure Features CG61P
100K
200K
300K
400K
500K (No. incorporated gates)
CG61P
configured with built-in analog select Analog
Fixed Layout
Schematic view chip
2002
No.1
FIND Vol.20
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