4401035 Metastability Pohlman email: pohlman@poci.amis.com

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4401035 Metastability Pohlman email: pohlman@poci.amis.com

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Metastability
4401035
Metastability
Pohlman email: pohlman@poci.amis.com
included this section. these simulations, fast rising (0.01ns) clock asserted while voltage input being slowly ramped down. slope signal applied input time clock assertion varied until metastability just occurs. time valid data level, using 30%/ 70%, (delay meta) then compared same simulation with input held (delay norm). difference between these metastable time. test circuit consists flip-flop under test with each driving INV3 provide typical loading. parameters commercial limits worst-case-speed process, 4.5V 80C. This worst case condition metastability. worst-case-zero worstcase-one conditions, imbalance between P-type N-type transistors cause quicker recovery from metastability. metastable time scales between best-case-speed, typical, worstcase-speed process corners commercial, industrial military temperature ranges.
Introduction
Digital design engineers normally live nice predictable world where everything controlled master clock. However, sooner later have connect with outside asynchronous world. Synchronizing asynchronous signals where metastability most frequently rears head. Metastability occurs when flip-flop balancing peak potential energy curve. flip-flop enter this condition when setup hold times violated when attempt made clock invalid logic level. flip-flop that metastable have outputs intermediate state, oscillating, have increased delay times. AMI's micron flip-flops exhibit increased delay times. Metastability becomes problem when flip-flop does reach stable condition soon enough propagate valid logic level following flip-flops. flip-flop metastable, unknown data will clocked into circuit, which cause improper operation. duration metastable condition probabilistic phenomenon, therefore there guaranteed maximum time. idea much delay expected, runs SPICE simulations test circuit. chart listing results selected flip-flops technologies
minimize problem metastability
Synchronize asynchronous inputs through path that least preferably flip-flops series. flip-flops should running same edge your system clock rest circuit. This will limit area potential problems path instead several, minimize possibility metastability entering
Metastability
4401035
main part circuit. buffered flip-flops, unbuffered flip-flops with minimum load. Design state machines whose operation affected these "synchronized" signals follow gray code pattern between states controlled these signals. This will prevent state machine from "taking off" unwanted states should synchronizing flipflops metastable. Finally, make sure clock period greater than longest clock clock delay path, setup time destination flip-flop, metastable time source flip-flop (see attached table). This will avoid gen-
eration metastable conditions inside circuit minimize propagation should they occur. following these precautions, circuit will resistant effects metastability more reliable.
Metastability times selected flip-flops Tech. type DFA11 DFA11 DFA51 DFA51 DF011 DF011 DF051 DF051 DF011 DF011 DF051 DF051 data rise fall rise fall rise fall rise fall rise fall rise fall delay norm 1.35 0.87 -1.70 1.21 -1.46 1.13 delay norm -1.16 1.10 -0.70 1.81 -0.87 1.40 delay meta 3.04 2.25 -3.63 1.85 -3.36 2.35 delay meta -2.59 2.53 -2.27 2.39 -2.62 2.83 metastable time 1.69 1.38 1.43 1.43 1.93 0.64 1.57 0.58 1.90 1.22 1.75 1.43
Metastability
4401035
Metastability times selected flip-flops Tech. type DFAA1 DFAA1 DF0A1 DF0A1 DF0A1 DF0A1 DF0A1 DF0A1 DF0A1 DF0A1 data rise fall rise fall rise fall rise fall rise fall delay norm 2.78 1.90 3.23 2.86 2.88 2.57 4.08 3.84 3.70 3.37 delay norm 1.73 1.59 0.99 2.68 1.15 2.08 1.08 3.94 1.32 2.84 delay meta 4.92 3.64 5.12 4.04 4.96 4.18 6.87 5.27 5.99 5.05 delay meta 3.87 3.34 2.89 3.88 3.26 3.70 3.87 5.39 3.62 4.54 metastable time 2.14 1.75 1.90 1.20 2.11 1.62 2.79 1.45 2.30 1.70
times nano-seconds commercial. industrial, multiply 1.034. military, multiply 1.123.
Metastability
4401035

4401035 Metastability Pohlman email: pohlman@poci.amis.com

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