COP8LGE9 8-Bit CMOS Flash Microcontroller with Memory, Virtual EEPROM,
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COP8LGE9 8-Bit CMOS Flash Microcontroller with Memory, Virtual EEPROM, 10-Bit Brownout
COP8LGE9 8-Bit CMOS Flash Microcontroller with Memory, Virtual EEPROM, 10-Bit Brownout
General Description
COP8LGE9 Flash microcontroller highly integrated COP8Feature core device, with Flash memory advanced features including Virtual EEPROM, A/D, USART Brownout Reset. This single-chip CMOS device designed applications requiring True In-(2.7V 5.5V with Device included this datasheet: Flash Program Memory (bytes) (bytes) Brownout Voltage 4.17V 4.5V Pins external components), high READ/WRITE endurance (100k cycles), superior data retention (100 years). same devices used development, pre-production volume production with range COP8 software hardware development tools.
Device
Package
Temperature
COP8LGE9
TSSOP
-40°C +85°C
Features
FEATURES kbytes Flash Program Memory with High Security Virtual EEPROM using Flash Program Memory byte volatile 10-bit Successive Approximation Analog Digital Converter channels) USART True In-System Programmability Flash Memory with 100k Read/Write cycles High current I/O's drive Touch Screen 16-bit timer: Processor Independent mode External Event counter mode Input Capture mode Brown-out Reset OTHER FEATURES Single supply operation: 4.5V-5.5V Quiet Design (low radiated emissions) Multi-Input Wake-up with optional interrupts MICROWIRE/PLUS (Serial Peripheral Interface Compatible) Clock Doubler operation from Oscillator
Nine multi-source vectored interrupts servicing: External Interrupt USART Idle Timer Timer (with interrupts) MICROWIRE/PLUS Serial peripheral interface Multi-Input Wake-Up Software Trap Idle Timer with programmable interrupt interval 8-bit Stack Pointer (stack RAM) 8-bit Register Indirect Data Memory Pointers True manipulation WATCHDOG Clock Monitor logic Software selectable options TRI-STATE Output/High Impedance Input Push-Pull Output Weak Pull Input Schmitt trigger inputs ports High Current I/Os Temperature range: -40°C +85°C Packaging: TSSOP True In-System, Real time emulation full program debug offered MetaLink's Development Systems
COP8is trademark National Semiconductor Corporation.
2002 National Semiconductor Corporation
DS200096
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COP8LGE9
Block Diagram
20009601
Connection Diagram
20009655
View Thin Shrink Small Outline Package (TSSOP) Package Number MTD48
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COP8LGE9
Pinouts 48-Pin Package Port DVCC DGND AVCC AGND RESET RESET ADCH8 ADCH9 ADCH10 ADCH11 ADCH12 ADCH13 ADCH14 ADCH15 Type MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU WDOUT
Alt. Function
System Emulation Mode
48-Pin TSSOP
Input POUT Output Clock
operation WDOUT controlled Option Register
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COP8LGE9
Ordering Information
Part Numbering Scheme COP8 Family Feature Indicator Program Memory Size Program Memory Type Flash Pins Package Type TSSOP Temperature +85°C
General Description
REDUCTION COP8LGE9 devices incorporate circuitry that guards against electromagnetic interference increasing problem today's microcontroller board designs. National's patented reduction technology offers clock circuitry, gradual turn-on output drivers (GTOs) internal smoothing filters, help circumvent many issues influencing embedded control designs. National achieved dB-20 reduction transmissions when designs have incorporated patented reducing circuitry. IN-SYSTEM PROGRAMMING VIRTUAL EEPROM device includes program boot that provides capability, through MICROWIRE/PLUS serial interface, erase, program read contents Flash memory. Additional routines included boot ROM, which called user program, enable user customize system software update capability MICROWIRE/ PLUS desired. Additional functions will copy blocks data between Flash Memory. These functions provide virtual EEPROM capability allowing user emulate variable amount EEPROM initializing nonvolatile variables from Flash Memory occasionally restoring these variables Flash Memory. contents boot have been defined National. Execution code from boot dependent state FLEX Option Register exit from RESET. FLEX zero, Flash Memory assumed empty execution from boot begins. further information FLEX bit, refer Section 4.5, Option Register. CLOCK DOUBLER operation will clock twice frequency selected oscillator MHz). This doubled clock will referred this document `MCLK'. frequency oscillator will referred CKI. Instruction execution occurs tenth MCLK rate. TRUE IN-SYSTEM EMULATION On-chip emulation capability been added which allows user perform true in-system emulation using final production boards devices. This simplifies testing evaluation software real environmental conditions. user, merely providing standard connector which bypassed jumpers final application board, provide software hardware debugging using actual production units.
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ARCHITECTURE COP8 family based modified Harvard architecture, which allows data tables accessed directly from program memory. This very important with modern microcontroller-based applications, since program memory usually non-volatile (ROM, EPROM Flash), while data memory usually RAM. Consequently constant data tables need contained non-volatile memory, they lost when microcontroller powered down. modified Harvard architecture, instruction fetch memory data transfers overlapped with stage pipeline, which allows next instruction fetched from program memory while current instruction being executed using data memory. This possible with Neumann single-address architecture. COP8 family supports software stack scheme that allows user incorporate many subroutine calls. This capability important when using High Level Languages. With hardware stack, user limited small fixed number stack levels. INSTRUCTION today's 8-bit microcontroller application arena cost/ performance, flexibility time market several issues that system designers face attempting build well-engineered products that compete marketplace. Many these issues addressed through manner which microcontroller's instruction handles processing tasks. that's COP8 family offers unique code-efficient instruction that provides flexibility, functionality, reduced costs faster time market that today's microcontroller based products require. Code efficiency important because enables designers pack more on-chip functionality into less program memory space (ROM, Flash). Selecting microcontroller with less program memory size translates into lower system costs, added security knowing that more code packed into available program memory space. 1.6.1 Instruction Features COP8 family incorporates unique combination instruction features, which provide designers with optimum code efficiency program memory utilization. 1.6.2 Single Byte/Single Cycle Code Execution efficiency fact that majority instructions single byte variety, resulting minimum program space. Because compact code does occupy substantial amount program memory space, designers integrate additional features functionality into microcontroller program memory space. Also, majority instructions executed device single cycle, resulting minimum program execution time. fact, instructions single byte single cycle, providing greater code efficiency, faster code execution.
COP8LGE9
General Description
(Continued)
1.6.4 Bit-Level Control Bit-level control over many microcontroller's ports provides flexible means ease layout concerns save board space. members COP8 family provide ability set, reset test individual data memory address space, including memory-mapped ports associated registers. 1.6.5 Register Three memory-mapped pointers handle register indirect addressing software stack pointer functions. memory data pointers allow option post-incrementing postdecrementing with data movement instructions (LOAD/ EXCHANGE). memory-mapped registers allow designers optimize precise implementation certain specific instructions. PACKAGING/PIN EFFICIENCY Real estate board configuration considerations demand maximum space efficiency, particularly given today's high integration small product form factors. Microcontroller users avoid using large packages needed. Large packages take valuable board space increase device cost, trade-offs that microcontroller designs afford. COP8 family offers wide range packages does waste pins.
1.6.3 Many Single-Byte, Multi-Function Instructions COP8 instruction utilizes many single-byte, multifunction instructions. This enables single instruction accomplish multiple functions, such DRSZ, DCOR, JID, (Load) (Exchange) instructions with postincrementing post-decrementing, name just examples. many cases, instruction simultaneously execute many three functions with same single-byte instruction. JID: (Jump Indirect); Single byte instruction decodes external events jumps corresponding service routines (analogous CASE" statements higher level languages). LAID: (Load Accumulator-Indirect); Single byte look table instruction provides efficient data path from program memory CPU. This instruction used table lookup read entire program memory checksum calculations. RETSK: (Return Skip); Single byte instruction allows return from subroutine skips next instruction. Decision branch made subroutine itself, saving code. AUTOINC/DEC: These instructions memory pointers efficiently process block data (simplifying "FOR NEXT" other loop structures higher level languages).
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COP8LGE9
Absolute Maximum Ratings
(Note
Total Current (Sink) Storage Temperature Range Protection Level
-65°C +140°C (Human Body Model)
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage Total Current into (Source) -0.3V +0.3V
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics
TABLE Electrical Characteristics (-40°C +85°C) Datasheet min/max specification limits guaranteed design, test, statistical analysis. Parameter Operating Voltage Power Supply Rise Time Power Supply Ripple (Note Supply Current (Note 3.33 HALT Current with (Note Idle Current (Note 3.33 Brownout Trip Level (BOR Enabled) Input Levels (VIH, VIL) Logic High Logic Internal Bias Resistor Crystal/Resonator Oscillator Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels B0-B3 Outputs Source (Weak Pull-Up Mode) Source (Push-Pull Mode) (Note Sink (Push-Pull Mode) (Note Allowable Source Sink Current Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) (Note Sink (Push-Pull Mode) (Note Allowable Source Sink Current TRI-STATE Leakage Maximum Input Current without Latchup (Note Retention Voltage, HALT Mode) Input Capacitance Voltage Force Execution from Boot rise time must slower (Note than Rise Time Force Execution from Boot Input Current when Input Flash Memory Data Retention 11V, 5.5V 25°C 5.5V -0.5 4.5V, 3.8V 4.5V, 3.8V 4.5V, 1.0V +0.5 4.5V, 3.8V 4.5V, 4.0V 4.5V, 0.5V 5.5V 5.5V, 0.25 0.16 -210 5.5V, 4.5V, 4.17 4.28 5.5V, 4.5V, 5.5V, 13.2 Peak-to-Peak Conditions Units
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COP8LGE9
Electrical Characteristics
Parameter Flash Memory Number Erase/Write Cycles
(Continued)
TABLE Electrical Characteristics (-40°C +85°C) (Continued) Datasheet min/max specification limits guaranteed design, test, statistical analysis. Conditions Table Typical Flash Memory Endurance Units cycles
TABLE Electrical Characteristics (-40°C +85°C) Datasheet min/max specification limits guaranteed design, test, statistical analysis. Parameter Instruction Cycle Time (tC) Crystal/Resonator Flash Memory Page Erase Time 4.5V 5.5V Table Typical Flash Memory Endurance Conditions Units
Flash Memory Mass Erase Time Frequency MICROWIRE/PLUS Slave Mode MICROWIRE/PLUS Setup Time (tUWS) MICROWIRE/PLUS Hold Time (tUWH) MICROWIRE/PLUS Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time USART Time when using External USART Frequency when being Driven Internal Baud Rate Generator Reset Pulse Width
instruction cycle time. Note Maximum rate voltage change must
periods
V/ms.
Note Supply IDLE currents measured with driven with square wave Oscillator, driven 180° phase with CKI, inputs connected outputs driven connected load. Note HALT mode will stop from oscillating. Measurement HALT done with device neither sourcing sinking current; with G2-G5 programmed outputs driving load; inputs tied VCC; converter clock monitor disabled. Parameter refers HALT mode entered setting Port data register. Note Pins RESET designed with high voltage input network. These pins allow input voltages pins will have sink current when biased voltages (the pins have source current when biased voltage below VCC). These pins will latch voltage pins must limited 14V. WARNING: Voltages excess will cause damage pins. This warning excludes transients. Note Absolute Maximum Ratings should exceeded. Note must valid stable before raised high voltage.
TABLE Converter Electrical Characteristics (-40°C +85°C) (Single-ended mode only) Datasheet min/max specification limits guaranteed design, test, statistical analysis. Parameter Resolution Offset Error Gain Error Input Voltage Range Analog Input Leakage Current 4.5V 5.5V Conditions Units Bits
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COP8LGE9
TABLE Converter Electrical Characteristics (-40°C +85°C) (Single-ended mode only) (Continued) Datasheet min/max specification limits guaranteed design, test, statistical analysis. Parameter Analog Input Resistance (Note Analog Input Capacitance Conversion Clock Period Conversion Time (including Time) 4.5V 5.5V Conditions Units Conversion Clock Cycles
Operating Current AVCC
AVCC 5.5V
Note Resistance between device input internal sample hold capacitance.
20009605
FIGURE MICROWIRE/PLUS Timing
Descriptions
COP8LGE9 structure enables designers reconfigure microcontroller's functions with single instruction. Each individual independently configured output low, output high, input with high impedance input with weak pull-up device. typical example pins keyboard matrix input lines. input lines programmed with internal weak pull-ups that input lines read logic high when keys open. With closure, corresponding input line will read logic zero since weak pull-up easily overdriven. When released, internal weak pull-up will pull input line back logic high. This eliminates need external pull-up resistors. high current options available driving LEDs, motors speakers. This flexibility helps ensure cleaner design, with less external components lower costs. Below general description available pins. power supply pins. pins must connected. clock input. This connected conjunction with CKO) external crystal circuit form crystal oscillator. Oscillator Description section. RESET master reset input. Reset description section. AVCC Analog Supply converter. should connected externally. This also resistor ladder converter used within converter. AGND ground converter. should connected externally. This also bottom resistor ladder converter used within converter.
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device contains five bidirectional 8-bit ports where each individual independently configured input (Schmitt trigger inputs ports), output TRI-STATE under program control. Three data memory address locations allocated each these ports. Each port three associated 8-bit memory mapped registers, CONFIGURATION register, output DATA register input register. (See memory various addresses associated with ports.) Figure shows port configurations. DATA CONFIGURATION registers allow each port individually configured under software control shown below:
CONFIGURATION Register DATA Register Port Set-Up Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull Output
Port 8-bit port. pins have Schmitt triggers inputs. Port 8-bit port. pins have Schmitt triggers inputs. Port being used with some combination digital inputs analog inputs, analog inputs will read undetermined values. application software should mask these unknown bits when reading Port register, only bit-access program instructions when accessing Port Port supports analog inputs converter. Port following alternate functions:
COP8LGE9
Descriptions
(Continued)
Multi-Input Wake-up (USART Transmit) Multi-Input Wake-up and/or (USART Clock) Multi-Input Wake-up
Analog Channel Input Analog Channel Analog Multiplexor Output Analog Channel Analog Multiplexor Output Analog Channel Analog Analog Analog Analog Channel Channel Channel Channel (High current) (High current) (High current) (High current)
Port 8-bit port. G2-G5 bi-directional ports. always general purpose Hi-Z input. pins have Schmitt Triggers their inputs. serves dedicated WATCHDOG output with weak pull-up WATCHDOG feature selected Option register. general purpose WATCHDOG feature selected. WATCHDOG feature selected, Port configuration data register does have effect setup. serves dedicated output clock output. Since input only dedicated clock output pin, associated bits data configuration registers used special purpose functions outlined below. Reading data bits will return zeros. device will placed HALT mode writing Port Data Register. Similarly device will placed IDLE mode writing Port Data Register. Writing Port Configuration Register enables MICROWIRE/PLUS operate with alternate phase clock. configuration bit, high, enables clock start delay after HALT when clock configuration used. Config. Reg. CLKDLY Alternate Data Reg. HALT IDLE
20009606
FIGURE Port Configurations
20009607
FIGURE Port Configurations Output Mode
Port following alternate features: Oscillator dedicated output (MICROWIRE/PLUS Serial Data Input) (MICROWIRE/PLUS Serial Clock) (MICROWIRE/PLUS Serial Data Output) (Timer I/O) (Timer Capture Input) WDOUT WATCHDOG and/or Clock Monitor WATCHDOG enabled, otherwise general purpose INTR (External Interrupt Input) through also used In-System Emulation. Port 8-bit Port. H-pins have Schmitt triggers inputs. Port 8-bit port. L-pins have Schmitt triggers inputs. Port supports Multi-Input Wake-Up feature eight pins. Port following alternate functions: Multi-Input Wake-up Multi-Input Wake-up Multi-Input Wake-up Multi-Input Wake-up Multi-Input Wake-up and/or (USART Receive)
20009608
FIGURE Port Configurations Input Mode EMULATION CONNECTION Connection emulation system made connector which interrupts continuity RESET, signals between COP8 device rest target system shown Figure This connector designed into production board
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COP8LGE9
Descriptions
(Continued)
REGISTERS 8-bit addition, subtraction, logical shift operation instruction (tC) cycle time. There registers: 8-bit Accumulator Register 15-bit Program Counter Register upper bits program counter (PC) lower bits program counter (PC) 8-bit address pointer, which optionally post auto incremented decremented. 8-bit alternate address pointer, which optionally post auto incremented decremented. 8-bit Data Segment Address Register used extend lower half address range into data segments bytes each. 8-bit stack pointer, which points subroutine/ interrupt stack RAM). With reset initialized address Hex. decremented items pushed onto stack. points next available location stack. registers memory mapped with exception Accumulator Program Counter (PC). PROGRAM MEMORY program memory consists 8192 bytes Flash Memory. These bytes hold program instructions constant data (data tables LAID instruction, jump vectors instruction, interrupt vectors instruction). program memory addressed 15-bit program counter (PC). interrupts device vector program memory location 00FF Hex. program memory reads erased state. Program execution starts location after RESET. Return instruction executed when contains (hex), instruction execution will continue from Program Memory location 7FFF (hex). location 7FFF accessed instruction fetch, Flash Memory will return value This opcode INTR instruction will cause Software Trap. purpose erasing rewriting Flash Memory, organized pages bytes. Refer Table program memory size available address ranges.
replaced jumpers signal traces when emulation longer necessary. emulator will replicate functions RESET. proper operation, connection should made device side emulator connector.
20009609
FIGURE Emulation Connection
Functional Description
architecture device modified Harvard architecture. With Harvard architecture, program memory (Flash) separate from data store memory (RAM). Both Program Memory Data Memory have their separate addressing space with separate address buses. architecture, though based Harvard architecture, permits transfer data from Flash Memory RAM.
TABLE Available Memory Address Ranges Program Memory Size (Flash) 8192 Flash Memory Option Register Page Size Address (Hex) (Bytes) 1FFF Data Memory Size (RAM) Segments Available Maximum Address (HEX) 017F
Device
COP8LGE9
DATA MEMORY data memory address space includes on-chip data registers, registers (Configuration, Data Pin), control registers, MICROWIRE/PLUS shift register, various registers, counters associated with timers USART (with exception IDLE timer). Data memory addressed directly instruction indirectly pointers. data memory consists bytes RAM. Sixteen bytes mapped "registers" addresses Hex. These registers loaded immediately,
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also decremented tested with DRSZ (decrement register skip zero) instruction. memory pointer registers memory mapped into this space address locations respectively, with other registers being available general usage. instruction permits memory set, reset tested. registers (except memory mapped; therefore, bits register bits directly individually set, reset tested. accumulator bits also directly individually tested. Note: contents undefined upon power-up.
COP8LGE9
Functional Description
(Continued)
Refer Table data memory size available address ranges. DATA MEMORY SEGMENT EXTENSION Data memory address used memory mapped location Data Segment Address Register (S). data store memory either addressed directly single byte address within instruction, indirectly relative reference pointers (each contains single-byte address). This single-byte address allows addressing range locations from hex. upper this single-byte address divides data store memory into separate sections outlined previously. With exception register memory from address locations 00F0 00FF, memory memory mapped with upper single-byte address being equal zero. This allows upper single-byte address determine whether base address range (from 0000 00FF) extended. this upper equals (representing address range 0080 00FF), then address extension does take place. Alternatively, this upper equals zero, then data segment extension register used extend base address range (from 0000 007F) from XX00 XX7F, where represents bits from register. Thus 128-byte data segment extensions located from addresses 0100 017F data segment 0200 027F data segment etc., FF00 FF7F data segment 255. base address range from 0000 007F represents data segment Refer Table determine available segments this device.
range hex) into data segments bytes each, with total addressing range kbytes from XX00 XX7F. This organization allows total data segments bytes each with additional upper base segment bytes. Furthermore, addressing modes available data segments. register must changed under program control move from data segment (128 bytes) another. However, upper base segment (containing memory registers, registers, control registers, etc.) always available regardless contents register, since upper base segment (address range 0080 00FF) independent data segment extension. instructions that utilize stack pointer (SP) always reference stack part base segment (Segment regardless contents register. register changed these instructions. Consequently, stack (used with subroutine linkage interrupts) always located base segment. stack pointer will initialized point data memory location 006F result reset. bytes contained base segment split between lower upper base segments. first bytes resident from address 0000 006F lower base segment, while remaining bytes represent data memory registers located addresses 00F0 00FF upper base segment. located upper sixteen addresses (0070 007F) lower base segment. Additional beyond these initial bytes, however, will always memory mapped groups bytes less) data segment address extensions (XX00 XX7F) lower base segment.
Figure illustrates register data memory extension used extending lower half base address
20009610
FIGURE Organization
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COP8LGE9
Functional Description
4.4.1 Virtual EEPROM
(Continued)
value
byte, ;configures ;options
Flash memory User functions (see Section 5.7), provide user with capability flash program memory back user defined sections RAM. This effectively provides user with same nonvolatile data storage EEPROM. Management, even amount memory used, responsibility user, however flash memory read write functions have been provided boot ROM. typical method using Virtual EEPROM feature would user copy data during system initialization, periodically, necessary, erase page Flash copy contents back Flash. OPTION REGISTER Option register, located address 1FFF (hex) Flash Program Memory, used configure user selectable security, WATCHDOG, HALT options. register programmed only external Flash Memory programming Programming modes. Therefore, register must programmed same time program memory. contents Option register shipped from factory read Hex. format Option register follows:
SECURITY WATCH HALT FLEX
.endsect Example: following sets value Option Register User Identification COP8LGE9HLQ. Option Register values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled execution will commence from Flash Memory. .chip 8LGE .sect option, conf 0x01 ;wd, halt, flex .endsect .end start Note: programmers certified programming this family parts will support programming Option Register. Please contact National your device programmer supplier more information. SECURITY device security feature which, when enabled, prevents external reading Flash program memory. security Option Register determines, whether security enabled disabled. security feature disabled, contents internal Flash Memory read external programmers built MICROWIRE/PLUS serial interface ISP. Security must enforced user when contents Flash Memory accessed user Virtual EEPROM capability. security feature enabled, then attempt externally read contents Flash Memory will result value (hex) being read from program locations (except Option Register). addition, with security feature enabled, write operation Flash program memory Option Register inhibited. Page Erases also inhibited when security feature enabled. Option Register readable regardless state security accessing location FFFF (hex). Mass Erase Operations possible regardless state security bit. security erased only Mass Erase entire contents Flash unless Flash operation under control User functions. Note: actual memory address Option Register 1FFF (hex), however MICROWIRE/PLUS routines require address FFFF (hex) used read Option Register when Flash Memory secured. entire Option Register must programmed time cannot rewritten without first erasing entire last page Flash Memory. RESET device initialized when RESET pulled On-chip Brownout Reset activated. Brownout Reset feature available COP8CDR9.
Reserved
Reserved
Bits These bits reserved must Security enabled. Flash Memory read write allowed except User ISP/Virtual commands. Mass Erase allowed. Security disabled. Flash Memory read write allowed. Bits These bits reserved must WATCHDOG feature disabled. general purpose I/O. WATCHDOG feature enabled. WATCHDOG output with weak pullup. HALT mode disabled. HALT mode enabled. Execution following RESET will from Flash Memory. Flash Memory erased. Execution following RESET will from Boot with MICROWIRE/ PLUS routines. COP8 assembler defines special section type, CONF, into which Option Register data coded. Option Register programmed automatically programmers that certified National. user needs ensure that FLEX will when device programmed. following examples illustrate declaration Option Register. Syntax: [label:].sect config, conf
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COP8LGE9
Functional Description
(Continued)
20009611
FIGURE Reset Logic following occurs upon initialization: Port TRI-STATE (High Impedance Input) Port TRI-STATE (High Impedance Input) Port TRI-STATE (High Impedance Input) Port TRI-STATE (High Impedance Input)Port TRISTATE (High Impedance Input). Exceptions: Watchdog enabled, then Watchdog output. have their weak pull-up enabled during RESET. Port TRI-STATE (High Impedance Input) CLEARED 0000 PSW, CNTRL ICNTRL registers: CLEARED SIOR: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on ITMR: Cleared except Accumulator, Timer RANDOM after RESET WKEN, WKEDG: CLEARED WKPND: RANDOM (Stack Pointer): Initialized address Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on Register: CLEARED RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on USART: PSR, ENU, ENUR, ENUI: Cleared except TBMT which one. ANALOG DIGITAL CONVERTER: ENAD: CLEARED ADRSTH: RANDOM ADRSTL: RANDOM CONTROL: ISPADLO: CLEARED ISPADHI: CLEARED PGMTIM: PRESET VALUE WATCHDOG enabled): device comes reset with both WATCHDOG
logic Clock Monitor detector armed, with WATCHDOG service window bits Clock Monitor set. WATCHDOG Clock Monitor circuits inhibited during reset. WATCHDOG service window bits being initialized high default maximum WATCHDOG service window clock cycles. Clock Monitor being initialized high will cause Clock Monitor error following reset clock reached minimum specified frequency termination reset. Clock Monitor error will cause active error output This error output will continue until 16-32 clock cycles following clock frequency reaching minimum specified value, which time output will high. 4.7.1 External Reset RESET input when pulled initializes device. RESET must held minimum instruction cycle guarantee valid reset. During Power-Up initialization, user must ensure that RESET device without Brownout Reset feature held until device within specified voltage. circuit RESET with delay times (5x) greater than power supply rise time recommended. Reset should also wide enough ensure crystal start-up upon Power-Up. RESET also used cause exit from HALT mode. recommended reset circuit this device shown Figure
20009612
FIGURE Reset Circuit Using External Reset 4.7.2 On-Chip Brownout Reset When enabled, device generates internal reset rises. While less than specified brownout voltage (Vbor), device held reset condition Idle Timer preset with 00Fx (240-256 tC). When reaches value greater than Vbor, Idle Timer starts counting down. Upon underflow Idle Timer, internal reset released device will start executing instructions. This internal reset will perform same functions external reset. Once above Vbor this initial Idle Timer time-out takes place, instruction execution begins Idle Timer used normally. however, drops below selected Vbor, internal reset generated, Idle Timer preset with 00Fx. device waits until greater than Vbor countdown starts over. When enabled, functional operation device guaranteed down Vbor level.
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COP8LGE9
Functional Description
(Continued)
20009613
FIGURE Brownout Reset Operation exception above that brownout circuit will insert delay approximately power time drops below voltage about 1.8V. device will held Reset duration this delay before Idle Timer starts counting This delay starts soon rises above trigger voltage (approximately 1.8V). This behavior shown Figure Case rises from on-chip RESET undefined until supply greater than approximately 1.0V. this time brownout circuit becomes active holds device RESET. supply passes level about 1.8V, delay about (td) started Idle Timer preset value between 00F0 00FF (hex). Once greater than Vbor expired, Idle Timer allowed count down (tid). Case shows subsequent supply voltage which goes below approximate 1.8V level. drops below Vbor, internal RESET signal asserted. When rises back above 1.8V level, started. Since power supply rise time longer this case, expired before rises above Vbor starts immediately when greater than Vbor. Case shows supply where drops below Vbor, below 1.8V. On-chip RESET asserted when goes below Vbor starts soon supply goes back above Vbor. Brownout Reset feature enabled, internal reset will turned until Idle Timer underflows. internal reset will perform same functions external reset. device guaranteed operate specified frequency down specified brownout voltage. After underflow, logic designed such that additional internal resets occur long remains above brownout voltage. device relatively immune short duration negativegoing transients (glitches). essential that good
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filtering done ensure that brownout feature works correctly. Power supply decoupling vital even battery powered systems. Refer device specifications actual Vborvoltages. Under circumstances should RESET allowed float. on-chip Brownout Reset feature being used, RESET should connected directly VCC. RESET input also connected external pull-up resistor other external circuitry. output brownout reset detector will always preset Idle Timer value between 00F0 00FF (240 tC). this time, internal reset will generated. feature disabled, then internal resets generated Idle Timer will power-up with unknown value. this case, external RESET must used. When disabled, this on-chip circuitry disabled draws current. contents data registers unknown following on-chip reset.
20009614
FIGURE Reset Circuit Using Power-On Reset
COP8LGE9
Functional Description
OSCILLATOR CIRCUIT
(Continued) Oscillator
4.8.1 Oscillator clock input while G7/CKO clock generator output crystal. on-chip bias resistor connected between provided reduce system part count. value resistor range 0.5M (typically 1.0M). Table shows component values required various standard crystal values. Resistor on-chip shown reference. Figure shows crystal oscillator connection diagram. ceramic resonator required frequency used place crystal accuracy requirements quite strict.
20009615
TABLE Crystal Oscillator Configuration, 25°C, Chip Chip Chip Chip (pF) 18-36 (pF) 18-36 100-156 Freq. (MHz) 0.455
FIGURE Crystal Oscillator CONTROL REGISTERS CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
crystal other oscillator components should placed close proximity pins minimize printed circuit trace length. values external capacitors should chosen obtain manufacturer's specified load capacitance crystal when combined with parasitic capacitance trace, socket, package (which vary from pF). guideline choosing these capacitors Manufacturer's specified load Cparasitic trimmed obtain desired frequency. should less than equal TABLE Startup Times Frequency 3.33 Startup Time 1-10 3-10 3-20 10-30
Timer1 (T1) MICROWIRE/PLUS control register contains following bits: T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control timer modes Underflow Interrupt Pending Flag timer mode MSEL Selects MICROWIRE/PLUS signals respectively IEDG External interrupt edge polarity select Rising edge, Falling edge) Select MICROWIRE/PLUS clock divide Register (Address X'00EF)
T1PNDA T1ENA EXPND BUSY EXEN
4.8.2 Clock Doubler This device contains frequency doubler that doubles frequency oscillator. When oscillator connected operates MHz, internal clock frequency MHz, resulting instruction cycle time output clock doubler called MCLK referenced many places within this document.
register contains following select bits: Half Carry Flag Carry Flag T1PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow Mode capture edge mode T1ENA Timer Interrupt Enable Timer Underflow Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt Global interrupt enable (enables interrupts) Half-Carry flag also affected instructions that affect Carry flag. (Set Carry) (Reset Carry) instructions will respectively clear both carry flags. addition instructions, ADC, SUBC, instructions affect Carry Half Carry flags.
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COP8LGE9
Functional Description
ICNTRL Register (Address X'00E8)
Unused LPEN T0PND T0EN µWPND µWEN
(Continued)
ADCH2 channel select ADCH1 channel select ADCH0 channel select
T1PNDB
T1ENB
ADMOD Places single-ended differential mode. Enables multiplexor output. Switches clock between divide divide sixteen MCLK. ADBSY Signifies that currently busy performing conversion. When user, starts conversion.
ICNTRL register contains following bits: LPEN Port Interrupt Enable (Multi-Input Wake-up/Interrupt) T0PND Timer Interrupt pending T0EN Timer Interrupt Enable (Bit toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer Interrupt Pending Flag capture edge T1ENB Timer Interrupt Enable Input capture edge ITMR Register (Address X'00CF)
RSVD RSVD1 RSVD RSVD RSVD ITSEL2 ITSEL1 ITSEL0
In-System Programming
INTRODUCTION This device provides capability program program memory while installed application board. This feature called System Programming (ISP). provides means using MICROWIRE/PLUS, user provide own, customized routine. factory installed uses MICROWIRE/PLUS port. user provide routine that uses capabilities device, such USART, parallel port, etc. FUNCTIONAL DESCRIPTION organization feature consists user flash program memory, factory boot ROM, some registers dedicated performing function. Figure simplified block diagram. factory installed that uses MICROWIRE/PLUS located Boot ROM. size Boot bytes also contains code facilitate system emulation capability. user chooses write routine, must located flash program memory.
ITMR RSVD RSVD1 ITSEL2 ITSEL1 ITSEL0
register contains following bits: These bits reserved must This reserved must Idle Timer period select bit. Idle Timer period select bit. Idle Timer period select bit.
ENAD Register (Address X'00CB)
ADCH3 ADCH2 ADCH1 ADCH0 ADMOD Mode Select ADBSY Busy Channel Select Prescale
ENAD register contains following bits: ADCH3 channel select
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FIGURE Block Diagram described OPTION REGISTER, there bit, FLEX, that controls whether device exits RESET executwww.national.com
from flash memory Boot ROM. user must program FLEX appropriate application.
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In-System Programming
(Continued) erased state, FLEX device will power-up executing from Boot ROM. When FLEX this assumes that either MICROWIRE/PLUS routine external programming being used program device. using MICROWIRE/PLUS routine, software boot will monitor MICROWIRE/PLUS commands program flash memory. When programming flash program memory complete, FLEX will have programmed device will have reset, either pulling external Reset ground MICROWIRE/PLUS EXIT command, before execution from flash program memory will occur. FLEX upon exiting Reset, device will begin executing from location 0000 flash program memory. assumption, here, that either application using ISP, using MICROWIRE/PLUS jumping within application code, using customized routine. customized routine being used, then must programmed into flash memory means MICROWIRE/PLUS external programming described preceding paragraph. REGISTERS There registers required support ISP: Address Register byte (ISPADHI), Address Register byte (ISPADLO), Read Data Register (ISPRD), Write Data Register (ISPWR), Write Timing Register (PGMTIM), Control Register (ISPCNTRL). ISPCNTRL Register available user. 5.3.1 Address Registers address registers (ISPADHI ISPADLO) used specify address byte data being written read. page erase operations, address beginning page should loaded. mass erase operations, 0000 must placed into address registers. When reading Option register, FFFF (hex) should placed into address registers. Registers ISPADHI ISPADLO cleared Reset. These registers loaded from either flash program memory Boot must maintained entire duration operation. Note: actual memory address Option Register 1FFF (hex), however MICROWIRE/PLUS routines require address FFFF (hex) used read Option Register when Flash Memory secured.
Addr
TABLE High Byte Address
ISPADHi Addr Addr Addr Addr Addr Addr Addr
TABLE Byte Address
ISPADLO Addr Addr Addr Addr Addr Addr Addr Addr
5.3.2 Read Data Register Read Data Register (ISPRD) contains value read back from read operation. This register accessed from either flash program memory Boot ROM. This register undefined Reset. TABLE Read Data Register
ISPRD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
5.3.3 Write Data Register Write Data Register (ISPWR) contains data written into specified address. This register undetermined Reset. This register accessed from either flash program memory Boot ROM. Write Data register must maintained entire duration operation. TABLE Write Data Register
ISPWR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
5.3.4 Write Timing Register Write Timing Register (PGMTIM) used control width timing pulses write erase operations. value written into this register dependent frequency shown Table This register must written before write erase operation take place. only needs loaded once, each value frequency. This register loaded from either flash program memory Boot must maintained entire duration operation. MICROWIRE/PLUS routine that resident boot requires that this Register defined prior access Flash memory. Refer MICROWIRE/PLUS more information available commands. Reset, PGMTIM register loaded with value that corresponds frequency CKI.
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In-System Programming
(Continued)
TABLE PGMTIM Register Format PGMTIM Register frozen until breakpoint condition cleared. register memory mapped register. format when writing shown Table normal operation, necessary test before using JSRB instruction. additional instructions required test cause time-out before JSRB executed. TABLE Register Write Format
When Writing
Frequency Range kHz-33.3 37.5 kHz-50 kHz-66.67 62.5 kHz-83.3 kHz-100 kHz-133 112.5 kHz-150 kHz-200 kHz-266.67 kHz-300 kHz-400 kHz-500 kHz-666.67 kHz-800 kHz-1.067 MHz-1.33 1.125 MHz-1.5 MHz-2 MHz-2.67 2.625 MHz-3.5 MHz-4.67 MHz-6 MHz-8 MHz-10
MANEUVERING BACK FORTH BETWEEN FLASH MEMORY BOOT When using ISP, some point, will necessary maneuver between flash program memory Boot ROM, even when using customized routines. This because it's possible execute from flash program memory while it's being programmed. instructions available perform jumping back forth: Jump Boot (JSRB) Return Flash (RETF). JSRB instruction used jump from flash memory Boot ROM, RETF used return from Boot back flash program memory. 14.0 Instruction specific details operation these instructions. JSRB instruction must used conjunction with register. This prevent jumping Boot event run-away software. JSRB instruction actually jump Boot ROM, must set. This done writing value shown Table register. matches, will instruction cycles. JSRB instruction must executed while set. does match, then will JSRB will jump specified location flash memory. emulation mode, breakpoint encountered while set, counter that counts instruction cycles will
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Bits 7-2: value that must written bit. Bits 1-0: Don't care. FORCED EXECUTION FROM BOOT When user developing customized routine, code lockups software errors encountered. normal, preferred, method recover from these conditions reprogram device with corrected code either external parallel programmer emulation tools. last resort, when this equipment available, there hardware method these lockups
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In-System Programming
(Continued) force execution from Boot MICROWIRE/PLUS routine. customer will then able erase Flash Memory code start over. method force this condition drive high voltage VCC) activate Reset. high voltage condition must applied before valid stable, must held least instruction cycles longer than Reset active. This special condition will bypass checking state Flex Option Register will start execution from location 0000 Boot ROM. this state, user input appropriate commands, using MICROWIRE/PLUS, erase flash program memory reprogram device subsequently reset before Flex been erased specific Page Erase Mass Erase commands, execution will start from location 0000 Flash program memory. high voltage VCC) will erase either Flex Security Option Register. Security bit, set, only erased Mass Erase entire contents Flash Memory unless under control User routines Application Program. While high voltage, Load Clock will output onto which will look like clock MICROWIRE/PLUS routine executing slave mode. However, when high voltage, input will also look like logic MICROWIRE/PLUS routine Boot monitors input, waits low, debounces then enables routine. CAUTION: Load clock could conflict with user's external user resolve this conflict, this condition considered minor issue that's only encountered during software development. user should also cautious high voltage applied pin. This high voltage could damage other circuitry connected (e.g. parallel port PC). user wish disconnect other circuitry while connected high voltage. must valid stable before high voltage applied correct sequence used force execution from Boot Disconnect from source data MICROWIRE/ PLUS ISP. Apply device. Pull RESET Low. After valid stable, connect voltage between VCC+7V pin. Ensure that rise time high voltage slower than minimum Electrical Specifications. Figure shows possible circuit dliagram implementing VCC. aware typical input current when high voltage applied. resistor used network, high voltage used, should chosen keep high voltage between VCC+7V.
Pull RESET High. After delay least three instruction cycles, remove high voltage from
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FIGURE Circuit Diagram Implementing RETURN FLASH MEMORY WITHOUT HARDWARE RESET After programming entire program memory, including options, necessary exit Boot return flash program memory program execution. Upon receipt completion EXIT command through MICROWIRE/PLUS ISP, code will reset part begin execution from flash program memory described Reset section. This assumes that FLEX Option register programmed MICROWIRE/PLUS National Semiconductor provides program, which available from site www.national.com/cop8, that capable programming device from parallel port software accepts manually input commands capable downloading standard Intel Format files. Users wish write their MICROWIRE/PLUS host software should refer COP8 FLASH User Manual, available from same site. This document includes details command format delays necessary between command bytes. MICROWIRE/PLUS supports following features commands:
Write value Write Timing Register. NOTE: This must first command after entering MICROWIRE/PLUS mode. Erase entire flash program memory (mass erase). Erase page specified address. Read Option register. Read byte from specified address. Write byte specified address. Read multiple bytes starting specified address. Write multiple bytes starting specified address. Exit return execution flash program memory.
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In-System Programming
(Continued) following table lists MICROWIRE/PLUS commands provides information required parameters return values. TABLE MICROWIRE/PLUS Commands Command PGMTIM_SET PAGE_ERASE MASS_ERASE READ_BYTE Function Write Pulse Timing Register Page Erase Mass Erase Read Byte Command Value (Hex) 0x3B 0xB3 0xBF 0x1D Value Starting Address Page Confirmation Code Address High, Address Parameters (The entire Flash Memory will erased) Data Byte Security set. 0xFF Security set. Option Register address 0xFFFF, regardless Security Data Bytes Security set. Bytes 0xFF Security set. Return Data
BLOCKR
Block Read
0xA3
Address High, Address Low, Byte Count High, Byte Count 32767 Address High, Address Low, Data Byte Address High, Address Low, Byte Count 16), Data Bytes other invalid command will ignored
WRITE_BYTE BLOCKW
Write Byte Block Write
0x71 0x8F
EXIT INVALID
EXIT
0xD3
(Device will Reset)
Note: user must ensure that Block Writes cross half page boundary within operation.
USER VIRTUAL following commands will support transferring blocks data from flash program memory, vice-versa. user expected enforce application security this case.
Copy block data from into flash program memory.
Erase entire flash program memory (mass erase). NOTE: Execution this command will force device into MICROWIRE/PLUS mode. Erase page flash memory specified address. Read byte from specified address. Write byte specified address.
Copy block data from program flash memory RAM. following table lists User ISP/Virtual commands, required parameters return data, applicable. command entry point used argument JSRB instruction. Table lists locations Peripheral Registers, used User Virtual their expected contents. Please refer COP8 FLASH User Manual additional information programming examples User Virtual
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In-System Programming
Command/ Label cpgerase Function Page Erase Command Entry Point 0x17
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TABLE User ISP/Virtual Entry Points Parameters Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Accumulator contains confirmation 0x55. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. pointer contains beginning address where result(s) will returned. Register BYTECOUNTLO contains number bytes read 255). user setup segment register. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Register ISPWR contains Data Byte written. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Register BYTECOUNTLO contains number bytes write 16). combination BYTECOUNTLO ISPADLO registers must such that operation will cross half page bytes) boundary. pointer contains beginning address data written. user setup segment register. Return Data page memory beginning ISPADHI, ISPADLO will erased)
cmserase creadbf
Mass Erase Read Byte
0x1A 0x11
(The entire Flash Memory will erased) Data Byte Register ISPRD.
cblockr
Block Read
0x26
Data Bytes, Data will returned beginning location pointed address
cwritebf
Write Byte
0x14
cblockw
Block Write
0x23
exit
EXIT
0x62
(Device will Reset)
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In-System Programming
Register Name ISPADHI ISPADLO ISPWR ISPRD ISPKEY BYTECOUNTLO PGMTIM
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TABLE Register Name Definitions Purpose High byte Flash Memory Address byte Flash Memory Address user must store byte written into this register before jumping into write byte routine. Data will returned this register after read byte routine execution. ISPKEY Register required validate JSRB instruction must loaded within instruction cycles before JSRB. Holds count number bytes read written block operations. Write Timing Register. This register must loaded, user, with proper value before execution USER Write Erase operation. Refer Table correct value. user must place this code accumulator before execution Flash Memory Mass Erase command. Must transferred ISPKEY register before execution JSRB instruction. Location 0xA9 0xA8 0xAB 0xAA 0xE2 0xF1 0xE1
Confirmation Code
0x98
RESTRICTIONS SOFTWARE WHEN CALLING ROUTINES BOOT hardware will disable interrupts from occurring. hardware will leave current state, set, hardware interrupts will occur when execution returned Flash Memory. Subsequent interrupts, during operation, from same interrupt source will lost. Interrupts occur between setting executing JSRB instruction. this case, will expire before JSRB executed. therefore, recommended that software globally disable interrupts before setting Key. security feature MICROWIRE/PLUS guaranteed software hardware. When executing MICROWIRE/PLUS routine, security checked prior performing instructions. Only mass erase command, write PGMTIM register, reading Option register permitted within MICROWIRE/PLUS routine. When user performing ISP, commands permitted. entry points from user's code check security. burden user guarantee security. Security description OPTION REGISTER more details security. When using functions Boot ROM, routines will service WATCHDOG within selected upper window. Upon return flash memory, WATCHDOG serviced, lower window enabled, user service WATCHDOG anytime following exit from Boot ROM, must service within selected upper window avoid WATCHDOG error. Block Writes start anywhere page Flash memory, cannot cross half page full page boundaries. user must ensure that page erase mass erase executed between consecutive writes same location Flash memory. writes same location without intervening erase will produce unpredicatable results including possible disturbance unassociated locations.
5.10 FLASH MEMORY DURABILITY CONSIDERATIONS endurance Flash Memory (number possible Erase/Write cycles) function erase time lowest temperature which erasure occurs. device used temperature, additional erase operations used extend erase time. user determine many times erase page based what endurance desired application (e.g. four page erase cycles, each time page erase done, required achieve typical 100k Erase/Write cycles application which operating down 0°C). Also, customer verify that entire page erased, with software, request additional erase operations desired. TABLE Typical Flash Memory Endurance Operating Temp Range Erase Time -40°C 100k -20°C 100k 100k 100k 100k 100k 100k 25°C 100k 100k 100k 100k 100k 100k 100k 100k
25°C
100k 100k 100k 100k 100k 100k 100k 100k
Timers
device contains very versatile timers (T0, T1). Timer associated autoreload/capture registers power containing random data.
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Timers
(Continued)
TIMER (IDLE TIMER) device supports applications that require maintaining real time power with IDLE mode. This IDLE mode support furnished IDLE Timer which 16-bit timer. user cannot read write IDLE Timer which count down timer. clock IDLE Timer instruction cycle clock (one-fifth frequency) addition time base function, Timer supports following functions:
Bits through ITMR register selected triggering IDLE Timer interrupt. Each time selected underflows (every 16k, clocks), IDLE Timer interrupt pending T0PND set, thus generating interrupt enabled), Port data register reset, thus causing exit from IDLE mode device that mode. order interrupt generated, IDLE Timer interrupt enable T0EN must set, (Global Interrupt Enable) must also set. T0PND flag T0EN bits ICNTRL register, respectively. interrupt used purpose. Typically, used perform task upon exit from IDLE mode. more information IDLE mode, refer Power Saving Features. Idle Timer period selected bits ITMR register Bits through ITMR Register reserved must used software flags.
Exit Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start delay HALT mode Start delay from Figure functional block diagram showing structure IDLE Timer associated interrupt logic.
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FIGURE Functional Block Diagram Idle Timer TABLE Idle Timer Window Length
ITSEL2 ITSEL1 ITSEL0 Idle Timer Period 4,096 inst. cycles 8,192 inst. cycles 16,384 inst. cycles 32,768 inst. cycles 65,536 inst. cycles Reserved Undefined Reserved Undefined Reserved Undefined
write zero high order bits ITMR Register. existing programs updated this device, writing zero these bits will cause device reset. RSVD: These bits reserved must RSVD1: This reserved must ITSEL2:0: Selects Idle Timer period described Table Idle Timer Window Length. time IDLE Timer period changed there possibility generating spurious IDLE Timer interrupt setting T0PND bit. user advised disable IDLE Timer interrupts prior changing value ITSEL bits ITMR Register then clear T0PND before attempting synchronize operation IDLE Timer. TIMER main functions microcontroller provide timing counting capability real-time control tasks. COP8 family offers very versatile 16-bit timer/counter structure, supporting 16-bit autoreload/capture registers (R1A R1B), optimized reduce software burdens real-time control applications. timer block pins
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ITSEL bits ITMR register cleared Reset Idle Timer period reset 4,096 instruction cycles. ITMR Register
RSVD RSVD1 RSVD RSVD RSVD ITSEL2 ITSEL1 ITSEL0
Note: Documentation previous COP8 devices, which included Programmable Idle Timer, recommended user
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(Continued)
associated with T1B. supports required timer block, while input timer block. timer block three operating modes: Processor Independent mode, External Event Counter mode, Input Capture mode. control bits T1C3, T1C2, T1C1 allow selection different modes operation. 6.2.1 Mode Processor Independent Mode timer's operating modes Processor Independent mode. this mode, timer generates "Processor Independent" signal because once timer setup, more action required from which translates less software overhead greater throughput. user software services timer block only when parameters require updating. This capability provided fact that timer separate 16-bit reload registers. reload registers contains "ON" timer while other holds "OFF" time. contrast, microcontroller that only single reload register requires additional software update reload value (alternate between on-time/off-time). timer generate output with width duty cycle controlled values stored reload registers. reload registers control countdown values reload values automatically written into timer when counts down through generating interrupt each reload. Under software control with minimal overhead, outputs useful controlling motors, triacs, intensity displays, providing inputs data acquisition sine wave generators. this mode, timer counts down fixed rate Upon every underflow timer alternately reloaded with contents supporting registers, R1B. very first underflow timer causes timer reload from register R1A. Subsequent underflows cause timer reloaded from registers alternately beginning with register R1B. Timer control bits, T1C3, T1C2 T1C1 timer mode operation.
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FIGURE Timer Mode 6.2.2 Mode External Event Counter Mode This mode quite similar processor independent mode described above. main difference that timer, clocked input signal from pin. timer control bits, T1C3, T1C2 T1C1 allow timer clocked either positive negative edge from pin. Underflows from timer latched into T1PNDA pending flag. Setting T1ENA control flag will cause interrupt when timer underflows. this mode input used independent positive edge sensitive interrupt input T1ENB control flag set. occurrence positive edge input latched into T1PNDB flag.
Figure shows block diagram timer External Event Counter mode.
Note: output available this mode since being used counter input clock.
Figure shows block diagram timer mode. underflows programmed toggle output pin. underflows also programmed generate interrupts. Underflows from timer alternately latched into pending flags, T1PNDA T1PNDB. user must reset these pending flags under software control. control enable flags, T1ENA T1ENB, allow interrupts from timer underflow enabled disabled. Setting timer enable flag T1ENA will cause interrupt when timer underflow causes register reloaded into timer. Setting timer enable flag T1ENB will cause interrupt when timer underflow causes register reloaded into timer. Resetting timer enable flags will disable associated interrupts. Either both timer underflow interrupts enabled. This gives user flexibility interrupting once period either rising falling edge output. Alternatively, user choose interrupt both edges output.
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FIGURE Timer External Event Counter Mode
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Timers
(Continued)
6.2.3 Mode Input Capture Mode device precisely measure external frequencies time external events placing timer block, input capture mode. this mode, reload registers serve independent capture registers, capturing contents timer when external event occurs (transition timer input pin). capture registers read while maintaining count, feature that lets user measure elapsed time time between events. saving timer value when external event occurs, time external event recorded. Most microcontrollers have latency time because they cannot determine timer value when external event occurs. capture register eliminates latency time, thereby allowing applications program retrieve timer value stored capture register. this mode, timer constantly running fixed rate. registers, R1B, capture registers. Each register acts conjunction with pin. register acts conjunction with register acts conjunction with pin. timer value gets copied over into register when trigger event occurs corresponding pin. Control bits, T1C3, T1C2 T1C1, allow trigger events specified either positive negative edge. trigger condition each input specified independently. trigger conditions also programmed generate interrupts. occurrence specified trigger condition pins will respectively latched into pending flags, T1PNDA T1PNDB. control flag T1ENA allows interrupt either enabled disabled. Setting T1ENA flag enables interrupts generated when selected trigger condition occurs pin. Similarly, flag T1ENB controls interrupts from pin. Underflows from timer also programmed generate interrupts. Underflows latched into timer T1C0 pending flag (the T1C0 control serves timer underflow interrupt pending flag Input Capture mode). Consequently, T1C0 control should reset when entering Input Capture mode. timer underflow interrupt enabled with T1ENA control flag. When interrupt occurs Input Capture mode, user must check both T1PNDA T1C0 pending flags order determine whether input capture timer underflow both) caused interrupt.
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FIGURE Timer Input Capture Mode TIMER CONTROL FLAGS control bits their functions summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control TxC0 Timer Start/Stop control Modes (Processor Independent External Event Counter), where Start, Stop Timer Underflow Interrupt Pending Flag Mode (Input Capture) T1PNDA Timer Interrupt Pending Flag T1ENA Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled T1PNDB Timer Interrupt Pending Flag T1ENB Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled timer mode control bits (T1C3, T1C2 T1C1) detailed Table Timer Operating Modes. When high speed timers counting high speed mode, directly altering contents timer upper lower registers, reload registers recommended. operations particularly problematic. Since these registers change many times single instruction cycle, performing SBIT RBIT operation with timer running produce unpredictable results. recommended procedure stop timer, perform changes timer reload register values, then re-start timer. This warning does apply timer control register. type read/write operation, including SBIT RBIT performed this register operating mode.
Figure shows block diagram timer Input Capture mode.
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Timers
Mode T1C3
(Continued) TABLE Timer Operating Modes T1C2 T1C1 Description PWM: Toggle PWM: Toggle External Event Counter External Event Counter Captures: Pos. Edge Pos. Edge Interrupt Source Autoreload Autoreload Timer Underflow Timer Underflow Pos. Edge Timer Underflow Pos. Edge Timer Underflow Neg. Edge Timer Underflow Neg. Edge Timer Underflow logic devices disabled during HALT mode. However, clock monitor circuitry, enabled, remains active will cause WATCHDOG output (WDOUT) low. HALT mode used user does want activate WDOUT pin, Clock Monitor should disabled after devices come reset (resetting Clock Monitor control with first write WDSVR register). device supports different ways exiting HALT mode. first method exiting HALT mode with Multi-Input Wake-up feature Port second method pulling RESET low. wake-up from Port device resumes execution from HALT point. wake-up from RESET execution will resume from location PC=0 RESET conditions apply. crystal ceramic resonator selected oscillator, Wake-up signal allowed start chip running immediately since crystal oscillators ceramic resonators have delayed start time reach full amplitude frequency stability. IDLE timer used generate fixed delay ensure that oscillator indeed stabilized before allowing instruction execution. this case, upon detecting valid Wake-up signal, only oscillator circuitry enabled. IDLE timer loaded with value clocked with instruction cycle clock. clock derived dividing oscillator clock down factor Schmitt trigger following inverter chip ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop. start-up time-out from IDLE timer enables clock signals routed rest chip. device options associated with HALT mode. first option enables HALT mode feature, while
Interrupt Source Autoreload Autoreload Pos. Edge Pos. Edge Pos. Edge
Timer Counts Pos. Edge Neg. Edge
Captures: Pos. Edge Neg. Edge
Neg. Edge Pos. Edge Neg. Edge
Captures: Neg. Edge Pos. Edge
MCLK
Captures: Neg. Edge Neg. Edge
Power Saving Features
Today, proliferation battery-operated based applications placed demands designers drive power consumption down. Battery-operated systems only type applications demanding power. power budget constraints also imposed those consumer/ industrial applications where well regulated expensive power supply costs cannot tolerated. Such applications rely cost power supply voltage derived directly from "mains" using voltage rectifier passive components. power demanded even automotive applications, increased vehicle electronics content. This required ease burden from battery. power 8-bit microcontrollers supply smarts control battery-operated, consumer/industrial, automotive applications. device offers system designers variety low-power consumption features that enable them meet demanding requirements today's increasing range low-power applications. These features include voltage operation, current drain, power saving features such HALT, IDLE, Multi-Input Wake-Up (MIWU). device offers user power save modes operation: HALT IDLE. HALT mode, microcontroller activities stopped. IDLE mode, on-board oscillator circuitry timer active other microcontroller activities stopped. either mode, on-board RAM, registers, states, timers (with exception unaltered. Clock Monitor, enabled, active both modes. HALT MODE device placed HALT mode writing HALT flag data bit). microcontroller activities, including clock timers, stopped. WATCHwww.national.com
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Power Saving Features
(Continued)
second option disables HALT mode selected through Option register. With HALT mode enable option, device will enter exit HALT mode described above. With HALT disable option, device cannot placed HALT mode (writing HALT flag will have effect, HALT flag will remain "0"). WATCHDOG detector circuit inhibited during HALT mode. However, clock monitor circuit enabled remains active during HALT mode order ensure clock monitor error device inadvertently enters HALT mode result runaway program power glitch.
recommended that user halt device merely stopping clock external oscillator mode. this method used, there possibility greater than specified HALT current. user wishes stop external clock, recommended that halted setting Halt flag first clock stopped only after halted.
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FIGURE Wake-up from HALT IDLE MODE device placed IDLE mode writing IDLE flag data bit). this mode, activities, except associated on-board oscillator circuitry, WATCHDOG logic, clock monitor IDLE Timer stopped. power supply requirements microcontroller this mode operation significantly lower than normal power requirement microcontroller. with HALT mode, device returned normal operation with reset, with Multi-Input Wake-up from Port. Alternatively, microcontroller also awakened from IDLE mode after selectable amount time 65,536 Idle Timer Clocks 32.768 milliseconds with internal clock frequency MHz. IDLE timer period selectable from five values, 16k, Idle Timer Clocks. Selection this value made through ITMR register. When selected IDLE Timer toggles, T0PND ICNTRL Register set. user option being interrupted when T0PND set. interrupt enabled disabled T0EN control bit. Setting T0EN flag enables interrupt vice versa. user enter IDLE mode with Timer interrupt enabled. this case, when T0PND gets set, device will first execute Timer interrupt service routine then return instruction following 'Enter Idle Mode' instruction. Alternatively, user enter IDLE mode with IDLE Timer interrupt disabled. this case, device will resume normal operation with instruction immediately following 'Enter IDLE Mode' instruction.
Note: necessary program instructions following both HALT mode IDLE mode instructions. These instructions necessary allow clock resynchronization following HALT IDLE modes.
more information IDLE Timer associated interrupt, description Section Timers.
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Power Saving Features
(Continued)
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FIGURE Wake-up from IDLE MULTI-INPUT WAKE-UP Multi-Input Wake-up feature used return (wake-up) device from either HALT IDLE modes. Alternately Multi-Input Wake-up/Interrupt feature also used generate edge selectable external interrupts. RBIT WKEN Disable MIWU SBIT WKEDG Change edge polarity RBIT WKPND Reset pending flag SBIT WKEN Enable MIWU port bits have been used outputs then changed inputs with Multi-Input Wake-up/Interrupt, safety procedure should also followed avoid wake-up conditions. After selected port bits have been changed from output input before associated WKEN bits enabled, associated edge select bits WKEDG should reset desired edge selects, followed associated WKPND bits being cleared. This same procedure should used following reset, since port inputs left floating result reset. occurrence selected trigger condition MultiInput Wake-up latched into pending register called WKPND. respective bits WKPND register will occurrence selected trigger edge corresponding Port pin. user responsibility clearing these pending flags. Since WKPND pending register occurrence selected wake-up conditions, device will enter HALT mode Wake-up both enabled pending. Consequently, user must clear pending flags before attempting enter HALT mode. WKEN WKEDG read/write registers, cleared reset. WKPND register contains random value after reset.
Figure shows Multi-Input Wake-up logic. Multi-Input Wake-up feature utilizes Port. user selects which particular port combination Port bits) will cause device exit HALT IDLE modes. selection done through register WKEN. register WKEN 8-bit read/write register, which contains control every port bit. Setting particular WKEN enables Wake-up from associated port pin. user select whether trigger condition selected Port going either positive edge (low high transition) negative edge (high transition). This selection made register WKEDG, which 8-bit control register with assigned each Port pin. Setting control will select trigger condition negative edge that particular Port pin. Resetting selects trigger condition positive edge. Changing edge select entails several steps order avoid Wake-up condition result edge change. First, associated WKEN should reset, followed edge select change WKEDG. Next, associated WKPND should cleared, followed associated WKEN being re-enabled. example serve clarify this procedure. Suppose wish change edge select from positive (low going high) negative (high going low) Port where previously been enabled input interrupt. program would follows:
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Power Saving Features
(Continued)
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FIGURE Multi-Input Wake-Up Logic
USART
device contains full-duplex software programmable USART. USART (Figure consists transmit shift register, receive shift register seven addressable registers, follows: transmit buffer register (TBUF), receiver buffer register (RBUF), USART control status register (ENU), USART receive control status register (ENUR), USART interrupt clock source register (ENUI), prescaler select register (PSR) baud (BAUD) register. register contains flags transmit receive functions; this register also determines length data frame bits), value ninth transmission, parity selection bits. ENUR register flags framing, data overrun, parity errors line breaks while USART receiving.
Other functions ENUR register include saving ninth received data frame, enabling disabling USART's attention mode operation providing additional receiver/transmitter status information RCVG XMTG bits. determination internal external clock source done ENUI register, well selecting number stop bits enabling disabling transmit receive interrupts. control flag this register also select USART mode operation: asynchronous synchronous.
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USART
(Continued)
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FIGURE USART Block Diagram USART CONTROL STATUS REGISTERS operation USART programmed through three registers: ENU, ENUR ENUI. DESCRIPTION USART REGISTER BITS USART CONTROL STATUS REGISTER (Address 0BA)
PSEL1 XBIT9/ PSEL0 CHL1 CHL0 RBFL TBMT
PEN: This enables/disables Parity 8-bit modes only). Read/Write, cleared reset. Parity disabled. Parity enabled. PSEL1, PSEL0: Parity select bits. Read/Write, cleared reset. PSEL1 PSEL0 Parity Parity enabled) PSEL1 PSEL1 Even Parity Parity enabled) PSEL1 PSEL0 Mark(1) Parity enabled) PSEL1 PSEL1 Space(0) Parity enabled)
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COP8LGE9
USART
(Continued)
XBIT9/PSEL0: Programs ninth transmission when USART operating with nine data bits frame. seven eight data bits frame, this conjunction with PSEL1 selects parity. Read/Write, cleared reset. CHL1, CHL0: These bits select character frame format. Parity included generated/verified hardware. Read/Write, cleared reset. CHL1 CHL0 frame contains eight data bits. CHL1 CHL0 frame contains seven data bits. CHL1 CHL0 frame contains nine data bits. CHL1 CHL0 Loopback Mode selected. Transmitter output internally looped back receiver input. Nine framing format used. ERR: This global USART error flag which gets combination errors (DOE, occur. Read only; cannot written software, cleared reset. RBFL: This when USART received complete character copied into RBUF register. automatically reset when software reads character from RBUF. Read only; cannot written software, cleared reset. TBMT: This when USART transfers byte data from TBUF register into TSFT register transmission. automatically reset when software writes into TBUF register. Read only, "one" reset; cannot written software. ENUR USART RECEIVE CONTROL STATUS REGISTER (Address 0BB)
RBIT9 ATTN XMTG RCVG
XMTG: This indicate that USART transmitting. gets reset last frame (end last Stop bit). Read only, cleared reset. RCVG: This high whenever framing error break detect occurs goes when goes high. Read only, cleared reset. ENUI USART INTERRUPT CLOCK SOURCE REGISTER (Address 0BC)
STP2 ETDX SSEL XRCLK XTCLK
STP2: This programs number Stop bits transmitted. Read/Write, cleared reset. STP2 Stop transmitted. STP2 Stop bits transmitted. BRK: Holds (USART Transmit Pin) generate Line Break. Timing Line Break under software control. ETDX: (USART Transmit Pin) alternate function assigned Port selected setting ETDX bit. SSEL: USART mode select. Read only, cleared reset. SSEL Asynchronous Mode. SSEL Synchronous Mode. XRCLK: This selects clock source receiver section. Read/Write, cleared reset. XRCLK clock source selected through BAUD registers. XRCLK Signal (L1) used clock. XTCLK: This selects clock source transmitter section. Read/Write, cleared reset. XTCLK clock source selected through BAUD registers. XTCLK Signal (L1) used clock. ERI: This enables/disables interrupt from receiver section. Read/Write, cleared reset. Interrupt from receiver disabled. Interrupt from receiver enabled. ETI: This enables/disables interrupt from transmitter section. Read/Write, cleared reset. Interrupt from transmitter disabled. Interrupt from transmitter enabled.
DOE: Flags Data Overrun Error. Read only, cleared read, cleared reset. Indicates Data Overrun Error been detected since last time ENUR register read. Indicates occurrence Data Overrun Error. Flags Framing Error. Read only, cleared read, cleared reset. Indicates Framing Error been detected since last time ENUR register read. Indicates occurrence Framing Error. Flags Parity Error. Read only, cleared read, cleared reset. Indicates Parity Error been detected since last time ENUR register read. Indicates occurrence Parity Error. Flags line break. Indicates Line Break been detected since last time ENUR register read. Indicates occurrence Line Break. RBIT9: Contains ninth data received when USART operating with nine data bits frame. Read only, cleared reset. ATTN: ATTENTION Mode enabled while this set. This cleared automatically receiving character with data nine set. Read/Write, cleared reset.
ASSOCIATED PINS Data transmitted received pin. alternate function assigned Port selected setting ETDX ENUI register) one. inherent function Port requiring setup. Port must configured output Port Configuration Register order used pin. baud rate clock USART generated onchip, taken from external source. Port (CKX) external clock pin. either input output, determined Port Configuration Data registers (Bit input, accepts clock signal which selected drive transmitter and/or receiver. output, presents internal Baud Rate Generator output. Note: unavailable Port used Speed Oscillator.
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COP8LGE9
USART
(Continued)
USART OPERATION USART modes operation: asynchronous mode synchronous mode. 8.4.1 Asynchronous Mode This mode selected resetting SSEL ENUI register) zero. input frequency USART times baud rate. TSFT TBUF registers double-buffer data transmission. While TSFT shifting current character pin, TBUF register loaded software with next byte transmitted. When TSFT finishes transmitting current character contents TBUF transferred TSFT register Transmit Buffer Empty Flag (TBMT register) set. TBMT flag automatically reset USART when software loads character into TBUF register. There also XMTG which indicate that USART transmitting. This gets reset last frame (end last Stop bit). TBUF read/write register. RSFT RBUF registers double-buffer data being received. USART receiver continually monitors signal level detect beginning Start bit. Upon sensing this level, waits half time samples again. still low, receiver considers this valid Start bit, remaining bits character frame each sampled three times around center time. Serial data input shifted into RSFT register. Upon receiving complete character, contents RSFT register copied into RBUF register Received Buffer Full Flag (RBFL) set. RBFL automatically reset when software reads character from RBUF register. RBUF read only register. There also RCVG which high when framing error break detect occurs goes once goes high. 8.4.2 Synchronous Mode this mode data transferred synchronously with clock. Data transmitted rising edge received falling edge synchronous clock. This mode selected setting SSEL ENUI register. input frequency USART same baud rate. When external clock input selected pin, data transmit receive performed synchronously with this clock through TDX/RDX pins.
data transmit receive selected with clock output, device generates synchronous clock output pin. internal baud rate generator used produce synchronous clock. Data transmit receive performed synchronously with this clock. FRAMING FORMATS USART supports several serial framing formats (Figure 22). format selected using control bits ENU, ENUR ENUI registers. first format data transmission (CHL0 CHL1 consists Start bit, seven Data bits (excluding parity) Stop bits. applications using parity, parity generated verified hardware. second format (CHL0 CHL1 consists Start bit, eight Data bits (excluding parity) 7/8, Stop bits. Parity generated verified hardware. third format transmission (CHL0 CHL1 consists Start bit, nine Data bits Stop bits. This format also supports USART "ATTENTION" feature. When operating this format, eight bits TBUF RBUF used data. ninth data transmitted received using bits ENUR registers, called XBIT9 RBIT9. RBIT9 read only bit. Parity generated verified this mode. parity enabled/disabled located register. Parity selected 8-bit modes only. parity enabled (PEN parity selection then performed PSEL0 PSEL1 bits located register. Note that XBIT9/PSEL0 located register serves mutually exclusive functions. This programs ninth transmission when USART operating with nine data bits frame. There parity selection this framing format. other framing formats XBIT9 needed PSEL0 used conjunction with PSEL1 select parity. frame formats receiver differ from transmitter number Stop bits required. receiver only requires Stop frame, regardless setting Stop selection bits control register. Note that implicit assumption made full duplex USART operation that framing formats same transmitter receiver.
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COP8LGE9
USART
(Continued)
20009626
FIGURE Framing Formats USART INTERRUPTS USART capable generating interrupts. Interrupts generated Receive Buffer Full Transmit Buffer Empty. Both interrupts have individual interrupt vectors. bytes program memory space reserved each interrupt vector. vectors located addresses 0xEC 0xEF program memory space. interrupts individually enabled disabled using Enable Transmit Interrupt (ETI) Enable Receive Interrupt (ERI) bits ENUI register. interrupt from Transmitter pending, remains pending, long both TBMT bits set. remove this interrupt, software must either clear write TBUF register (thus clearing TBMT bit). interrupt from receiver pending, remains pending, long both RBFL bits set. remove this interrupt, software must either clear read from RBUF register (thus clearing RBFL bit).
BAUD CLOCK GENERATION clock inputs transmitter receiver sections USART individually selected come either from external source (port from source selected BAUD registers. Internally, basic baud clock created from MCLK through two-stage divider chain consisting 1-16 (increments 0.5) prescaler 11-bit binary counter (Figure 23). divide factors specified through read/write registers shown Figure Note that 11-bit Baud Rate Divisor spills over into Prescaler Select Register (PSR). cleared upon reset. shown Table Prescaler Factor corresponds CLOCK. This condition USART power down mode where USART clock turned power saving purpose. user must also turn USART clock when different baud rate chosen. correspondences between 5-bit Prescaler Select Prescaler factors shown Table There
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COP8LGE9
USART
(Continued)
Prescaler Select 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Prescaler Factor 10.5 11.5 12.5 13.5 14.5 15.5
many ways calculate divisor factors, particularly effective method would achieve 1.8432 frequency coming first stage. 1.8432 prescaler output then used drive software programmable baud rate counter create clock following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 38400 (Table 19). Other baud rates created using appropriate divisors. clock then divided provide rate serial shift registers transmitter receiver. TABLE Baud Rate Divisors (1.8432 Prescaler Output) Baud Rate (110.03) 134.5 (134.58) 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor (N-1) 1046
Note: entries Table assume prescaler output 1.8432 MHz. asynchronous mode baud rate could high 1250k.
example, considering Asynchronous Mode crystal frequency 4.608 MHz, prescaler factor selected (4.608 2)/1.8432 entry available Table 1.8432 prescaler output then used with proper Baud Rate Divisor (Table obtain different baud rates. baud rate 19200 e.g., entry Table value from Table Baud Rate Divisor) Baud Rate 1.8432 MHz/(16 19200 divide performed because asynchronous mode, input frequency USART times baud rate. equation calculate baud rates given below. actual Baud Rate found from: 2)/(16 Where: Baud Rate crystal frequency Baud Rate Divisor (Table Prescaler Divide Factor selected value Prescaler Select Register (Table Note: Synchronous Mode, divisor replaced two. Example: Asynchronous Mode: Crystal Frequency Desired baud rate 19200
20009627
FIGURE USART BAUD Clock Generation
TABLE Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 Prescaler Factor CLOCK
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COP8LGE9
USART
(Continued)
Using above equation calculated first. 2)/(16 19200) 32.552 32.552 divided each Prescaler Factor (Table obtain value closest integer. This factor happens 6.5).
32.552/6.5 5.008 programmed value (from Table should Using above values calculated 2)/(16 6.5) 19230.769 error (19230.769 19200) 100/19200 0.16%
20009628
FIGURE USART BAUD Clock Divisor Registers EFFECT HALT/IDLE USART logic reinitialized when either HALT IDLE modes entered. This reinitialization sets TBMT flag resets read only bits USART control status registers. Read/Write bits remain unchanged. Transmit Buffer (TBUF) affected, Transmit Shift register (TSFT) bits one. receiver registers RBUF RSFT affected. device will exit from HALT/IDLE modes when Start character detected (L3) pin. This feature obtained using Multi-Input Wake-up scheme provided device. Before entering HALT IDLE modes user program must select Wake-up source pin. This selection done setting WKEN (Wake-up Enable) register. Wake-up trigger condition then selected high transition. This done WKEDG register (Bit one). device halted crystal oscillator used, Wake-up signal will start chip running immediately because finite start time requirement crystal oscillator. idle timer (T0) generates fixed (256 delay ensure that oscillator indeed stabilized before allowing device execute code. user consider this delay when data transfer expected immediately after exiting HALT mode. DIAGNOSTIC Bits CHL0 CHL1 register provide loopback feature diagnostic testing USART. When both bits one, following occurs: receiver input (RDX) internally connected transmitter output (TDX); output Transmitter Shift Register "looped back" into Receive Shift Register input. this mode, data that transmitted immediately received. This feature allows processor verify transmit receive data paths USART. Note that framing format this mode nine format; Start bit, nine data bits, Stop bits. Parity generated verified this mode. 8.10 ATTENTION MODE USART Receiver section supports alternate mode operation, referred ATTENTION Mode. This mode operation selected ATTN ENUR register. data format transmission must also selected having nine Data bits either Stop bits. ATTENTION mode operation intended networking device with other processors. Typically such environments messages consists device addresses, indicating which several destinations should receive them, actual data. This Mode supports scheme which addresses flagged having ninth data field ninth reset zero byte Data byte. While ATTENTION mode, USART monitors communication flow, ignores characters until address character received. Upon receiving address character, USART signals that character ready setting RBFL flag, which turn interrupts processor USART Receiver interrupts enabled. ATTN also cleared automatically this point, that data characters well address characters recognized. Software examines contents RBUF responds deciding either accept subsequent data stream leaving ATTN reset) wait until next address character seen setting ATTN again). Operation USART Transmitter affected selection this Mode. value ninth transmitted programmed setting XBIT9 appropriately. value ninth received obtained reading RBIT9. Since this located ENUR register where error flags reside, operation will reset error flags. 8.11 BREAK GENERATION generate line break, user software should ENUI register. This will force hold there until reset. inputs alternate functions Port
Converter
This device contains 8-channel, multiplexed input, successive approximation, Analog-to-Digital Converter. Pins AVCC AGND used voltage reference. inputs alternate functions Port
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COP8LGE9
Converter
OPERATING MODES
(Continued)
supports both Single Ended Differential modes operation. specific analog channel selection modes supported. These follows: Allow specific channel selected time. Converter performs specific conversion requested stops. Allow differential channel pair selected time. Converter performs specific differential conversion requested stops. both Single Ended Differential modes, there capability connect analog multiplexor output converter input external pins. This provides ability externally connect common filter/signal conditioning circuit Converter. Converter supported three memory mapped registers: result registers control register. When device reset, mode control register (ENAD) cleared, powered down result registers have unknown data. 9.1.1 Control Register control register, ENAD, contains bits channel selection, mode selection, multiplexor output selection, prescaler selection, Busy bit.
conversion initiated setting ADBSY ENAD control register. result conversion available user result registers, ADRSTH ADRSTL, when ADBSY cleared hardware completion conversion. TABLE ENAD
Channel Select ADCH3 ADCH2 ADCH1 ADCH0 Mode Select Mux/Out Prescale ADMOD Busy ADBSY
CHANNEL SELECT This 4-bit field selects eight channels VIN+. mode selection output determine VINinput. When eight channels available, shown Table When only channels available, shown Table port pins which used, application, operations must configured high-impedance inputs. ports configured outputs inputs with weak pull-up there will conflict between analog signal digitally driven output.
TABLE Converter Channel Selection when Multiplexor Output Disabled Select Bits ADCH3 ADCH2 ADCH1 ADCH0 Mode Select ADMOD Single Ended Mode Channel Mode Select ADMOD Differential Mode Channel Pairs Output Disabled
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COP8LGE9
Converter
(Continued)
TABLE Converter Channel Selection when Multiplexor Output Enabled Select Bits ADCH3 ADCH2 ADCH1 ADCH0 Mode Select ADMOD Single Ended Mode Channel Mode Select ADMOD Differential Mode Channel Pairs Used (Note ADC13 Output (Note ADCH14 Output (Note ADCH15 Input (Note Output Enabled
ADCH14 Output (Note ADCH15 Input (Note
Note This Input Channel Selection should used when Multiplexor Output enabled. Note This Input Channel Selection should used Differential Mode when Multiplexor Output enabled.
MULTIPLEXOR OUTPUT SELECT This 1-bit field allows output multiplexor input connected directly external pins. This allows external, common filter/signal conditioning circuit applied channels. output external conditioning circuit then connected directly input Sample Hold input Converter. Figure single ended mode diagram. Multiplexor output connected ADCH14 input connected ADCH15. Differential mode, differential multiplexor outputs available should converted single ended voltage connection Converter Input. Figure channel assignments this mode shown Table When using Output feature, delay though internal multiplexor pin, plus delay external filter circuit, plus internal delay Sample Hold will exceed three clock cycles that's allowed conversion. This adds requirement that, whenever that channel selected ADCH3:0 bits enabled, even when ADBSY gated output pin. input path converter also enabled. This allows input channel selected settled before starting conversion. sequence perform conversions using feature multistep process listed below. Select desired channel operating modes load them into ENAD without setting ADBSY. Wait appropriate time until analog input settled. This will depend application response external circuit. Select same desired channel operating modes used step load them into ENAD also ADBSY ADBSY using SBIT instruction. This will start conversion. Poll ADBSY until cleared hardware. This indicates completion conversion.
Obtain results from result registers. port pins used multiplexor output must configured high impedance inputs. port pins configured outputs, inputs with weak pull-up, there will conflict between analog signal output digitally driven output.
20009629
FIGURE with Single Ended Output Feature Enabled
20009630
FIGURE with Differential Output Feature Enabled MODE SELECT This 1-bit field used select mode operation (single ended differential) shown following Table
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COP8LGE9
Converter
ADMOD
(Continued)
TABLE Conversion Mode Selection Mode Single Ended Mode Differential Mode
thus powering A/D. first edge Converter clock following write operation, sample signal turns three clock cycles. conversion, internal conversion complete signal will clear ADBSY power down A/D. 10-bit result immediately loaded into result registers (ADRSTH ADRSTL) upon completion. Inadvertent changes ENAD register during conversion prevented control logic A/D. attempt write ENAD Register except ADBSY, while ADBSY one, ignored. ADBSY must cleared either completion conversion user before prescaler, conversion mode channel select values changed. After stopping current conversion, user load different values prescaler, conversion mode channel select start conversion instruction. PRESCALER Converter (A/D) contains prescaler option that allows different clock speed selections shown Table clock frequency equal MCLK divided prescaler value. Note that prescaler value must chosen such that clock falls within specified range. maximum frequency 1.25 MHz. This equates clock cycle. Converter takes clock cycles complete conversion. Thus minimum conversion time 12.0 when prescaler been selected with MCLK MHz. clock cycles needed conversion consist cycles sampling, cycle auto-zeroing comparator, cycles converting, cycle loading result into result registers, stopping re-initializing. ADBSY flag provides clock inhibit function, which saves power powering down when use. Note: Converter also powered down when device either HALT IDLE modes. running when device enters HALT IDLE modes, powers down then restarts conversion from beginning with corrupted sampled voltage (and thus invalid result) when device comes HALT IDLE modes. ANALOG INPUT SOURCE RESISTANCE CONSIDERATIONS
PRESCALER SELECT This 1-bit field used select prescaler clocks Converter. following Table shows various prescaler options. Care must taken, when selecting this bit, keep clock frequency within specified range. TABLE Converter Clock Prescale Clock Select MCLK Divide MCLK Divide
BUSY ADBSY ENAD register used control starting stopping conversion. When ADBSY cleared, prescale logic disabled clock turned off, drawing minimal power. Setting ADBSY starts clock initiates conversion based values currently ENAD register. Normal completion conversion clears ADBSY turns Converter. user wishes restart conversion which already progress, this accomplished only writing zero ADBSY stop current conversion then writing ADBSY start conversion. This done consecutive instructions. 9.1.2 Result Registers There result registers converter: high bits result 2-bits result. format these registers shown Figures Both registers read/write registers, normal operation, hardware writes value into register when conversion complete software reads value. Both registers undefined upon Reset. They hold previous value until conversion overwrites them. When reading ADRSTL, bits will read TABLE ADRSTH
TABLE ADRSTL
OPERATION conversion completed within fifteen converter clocks. Converter interface works follows. Setting ADBSY control register ENAD initiates conversion. conversion sequence starts beginning write ENAD operation which sets ADBSY,
Figure shows model single ended mode. differential mode similar model. leads analog inputs should kept short possible. Both noise digital clock coupling input cause conversion errors. clock lead should kept away from analog input line reduce coupling. Source impedances greater than analog input lines will adversely affect internal charging time during input sampling. shown Figure analog switch array closed only during cycle sample time. Large source impedances analog inputs result array being charged correct voltage levels, causing scale errors. large source resistance necessary, recommended solution slow down clock speed proportion source resistance. Converter operated maximum speed less than greater than clock speed needs reduced. example, with Converter operated half maximum speed. Converter clock speed
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COP8LGE9
Converter
(Continued)
slowed down either increasing prescaler divide-by decreasing clock frequency. minimum clock speed 65.536 kHz.
20009641
*The analog switch closed only during sample time.
FIGURE Model (Single Ended Mode)
10.0 Interrupts
10.1 INTRODUCTION device supports fourteen vectored interrupts. Interrupt sources include Timer Timer Timer Timer Port Wake-up, Software Trap, MICROWIRE/PLUS, USART External Input. interrupts force branch location 00FF program memory. instruction used vector appropriate service routine from location 00FF Hex.
Software trap highest priority while default lowest priority. Each maskable inputs fixed arbitration ranking vector.
Figure shows Interrupt block diagram.
20009632
FIGURE Interrupt Block Diagram 10.2 MASKABLE INTERRUPTS interrupts other than Software Trap maskable. Each maskable interrupt associated enable pending flag bit. pending when interrupt
condition occurs. state interrupt enable bit, combined with determines whether active pending
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10.0 Interrupts
(Continued)
flag actually triggers interrupt. maskable interrupt pending enable bits contained mapped control registers, thus controlled software. maskable interrupt condition triggers interrupt under following conditions: enable associated with that interrupt set. set. device processing non-maskable interrupt. non-maskable interrupt being serviced, maskable interrupt must wait until that service routine completed.) interrupt triggered only when these conditions beginning instruction. different maskable interrupts meet these conditions simultaneously, highestpriority interrupt will serviced first, other pending interrupts must wait. Upon Reset, pending bits, individual enable bits, reset zero. Thus, maskable interrupt condition cannot trigger interrupt until program enables setting both individual enable bit. When enabling interrupt, user should consider whether previously activated (set) pending should acknowledged. time interrupt enabled, previous occurrences interrupt should ignored, associated pending must reset zero prior enabling interrupt. Otherwise, interrupt simply enabled; pending already set, will immediately trigger interrupt. maskable interrupt active associated enable pending bits set. interrupt asychronous event which occur before, during, after instruction cycle. interrupt which occurs during execution instruction acknowledged until start next normally executed instruction. next normally executed instruction skipped, skip performed before pending interrupt acknowledged. start interrupt acknowledgment, following actions occur: automatically reset zero, preventing subsequent maskable interrupt from interrupting current service routine. This feature prevents maskable interrupt from interrupting another being serviced. address instruction about executed pushed onto stack. program counter (PC) loaded with 00FF Hex, causing jump that program memory location. device requires seven instruction cycles perform actions listed above. user wishes allow nested interrupts, interrupts service routine writing register, thus allow other maskable interrupts interrupt current service routine. nested interrupts allowed, caution must exercised. user must write program such prevent stack overflow, loss saved context information, other unwanted conditions. interrupt service routine stored location 00FF should instruction determine cause interrupt, jump interrupt handling routine corresponding highest priority enabled active interrupt. Alternately, user choose poll interrupt pending
enable bits determine source(s) interrupt. more than interrupt active, user's program must decide which interrupt service. Within specific interrupt service routine, associated pending should cleared. This typically done early possible service routine order avoid missing next occurrence same type interrupt event. Thus, same event occurs second time, even while first occurrence still being serviced, second occurrence will serviced immediately upon return from current interrupt routine. interrupt service routine typically ends with RETI instruction. This instruction back pops address stored stack, restores that address program counter. Program execution then proceeds with next instruction that would have been executed there been interrupt. there valid interrupts pending, highest-priority interrupt serviced immediately upon return from previous interrupt. Note: While executing from Boot virtual operations, hardware will disable interrupts from occurring. hardware will leave current state, set, hardware interrupts will occur when execution returned Flash Memory. Subsequent interrupts, during operation, from same interrupt source will lost. 10.3 INSTRUCTION general interrupt service routine, which starts address 00FF Hex, must capable handling types interrupts. instruction, together with interrupt vector table, directs device specific interrupt handling routine based cause interrupt. single-byte instruction, typically used very beginning general interrupt service routine address 00FF Hex, shortly after that point, just after code used context switching. instruction determines which enabled pending interrupt highest priority, causes indirect jump address corresponding that interrupt source. jump addresses (vectors) possible interrupts sources stored vector table. vector table long bytes (maximum vectors) resides 256-byte block containing instruction. However, instruction very 256-byte block (such 00FF Hex), vector table resides next 256-byte block. Thus, instruction located somewhere between 00FF 01DF (the usual case), vector table located between addresses 01E0 01FF Hex. instruction located between 01FF 02DF Hex, then vector table located between addresses 02E0 02FF Hex, Each vector bits long points beginning specific interrupt service routine somewhere 32-kbyte memory space. Each vector occupies bytes vector table, with higher-order byte lower address. vectors arranged order interrupt priority. vector maskable interrupt with lowest rank located 0yE0 (higher-order byte) 0yE1 (lower-order byte). next priority interrupt located 0yE2 0yE3, forth increasing rank. Software Trap highest rand vector always located 0yFE 0yFF. number interrupts which become active defines size table.
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COP8LGE9
10.0 Interrupts
(Continued)
Table shows types interrupts, interrupt arbitration ranking, locations corresponding vectors vector table. vector table should filled user with memory locations specific interrupt service routines. example, Software Trap routine located 0310 Hex, then vector location 0yFE -0yFF should contain data Hex, respectively. When Software Trap interrupt occurs instruction executed, program jumps address specified vector table. interrupt sources vector table listed order rank, from highest lowest priority. more enabled pending interrupts detected same time, with highest priority serviced first. Upon return from interrupt service routine, next highest-level pending interrupt serviced. instruction executed, interrupts enabled pending, lowest-priority interrupt vector used, jump made corresponding address vector table. This unusual occurrence result error. legitimately result from change enable bits pending flags prior execution instruction, such executing single cycle instruction which clears enable flag same time that pending flag set. also result, however, from inadvertent execution command outside context interrupt. default interrupt vector useful applications which time critical interrupts occur during
servicing another interrupt. Rather than restoring program context etc.) executing RETI instruction, interrupt service routine terminated returning instruction. this case, interrupts will serviced turn until further interrupts pending default routine started. After testing ensure that execution erroneous, routine should restore program context execute RETI return interrupted program. This technique save fifty instruction cycles (tC), more, oscillator) latency pending interrupts with penalty fewer than instruction cycles further interrupts pending. ensure reliable operation, user should always instruction determine source interrupt. Although possible poll pending bits detect source interrupt, this practice recommended. polling allows standard arbitration ranking altered, reliability interrupt system compromised. polling routine must individually test enable pending bits each maskable interrupt. Software Trap interrupt should occur, will serviced last, even though should have highest priority. Under certain conditions, Software Trap could triggered serviced, resulting inadvertent "locking out" maskable interrupts Software Trap pending flag. Problems such this avoided using instruction.
TABLE Interrupt Vector Table Arbitration Ranking Highest (10) (11) (12) (13) (14) (15) (16) Lowest Software Reserved External Timer Timer Timer MICROWIRE/PLUS Reserved USART USART Reserved Reserved Reserved Reserved Port L/Wake-up Default Port Edge Reserved Receive Transmit Underflow T1A/Underflow BUSY Source Description INTR Instruction Vector Address (Note (Hi-Low Byte) 0yFE-0yFF 0yFC-0yFD 0yFA-0yFB 0yF8-0yF9 0yF6-0yF7 0yF4-0yF5 0yF2-0yF3 0yF0-0yF1 0yEE-0yEF 0yEC-0yED 0yEA-0yEB 0yE8-0yE9 0yE6-0yE7 0yE4-0yE5 0yE2-0yE3 0yE0-0yE1
Note variable which represents block. vector table must located same 256-byte block except located last address block. this case, table must next block.
10.3.1 Execution When instruction executed activates arbitration logic. arbitration logic generates even number between (E0, etc.) depending which active interrupt highest arbitration ranking time cycle executed. example, software trap interrupt active, generated.
external interrupt active software trap interrupt not, then generated forth. active interrupt pending, than generated. This number replaces lower byte upper byte remains unchanged. therefore pointing vector active interrupt with highest arbitration ranking. This vector read from program memory placed into
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10.0 Interrupts
(Continued)
which pointed instruction service routine active interrupt with highest arbitration ranking.
non-maskable interrupt pending flag cleared RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) upon RESET.
Figure illustrates different steps performed instruction. Figure shows flowchart instruction.
20009633
FIGURE Operation 10.4 NON-MASKABLE INTERRUPT 10.4.1 Pending Flag There pending flag associated with non-maskable Software Trap interrupt, called STPND. This pending flag memory-mapped cannot accessed directly software. pending flag reset zero when device Reset occurs. When non-maskable interrupt occurs, associated pending interrupt service routine should contain RPND instruction reset pending flag zero. RPND instruction always resets STPND flag. 10.4.2 Software Trap Software Trap special kind non-maskable interrupt which occurs when INTR instruction (used acknowledge interrupts) fetched from program memory placed instruction register. This happen variety ways, usually because error condition. Some examples causes
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