ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS Single Chip M

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ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS Single Chip M

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FEATURES Seven Analog Input Channels Acquisition Synchronized Switching Frequency Three-Phase 12-Bit Generator Programmable Deadtime Narrow Pulse Deletion Minimum Switching Frequency Control Mode Output Control Space Vector Modulation Gate Drive Block (Pulsed Output Capability) Hardwired Output Polarity Control External Trip Input 8-Bit Auxiliary Timers Synthesized Analog Output Frequency 99.6% Duty Cycle Eight Bits Digital Port Configurable Input Output Change State Interrupt Support MIPS Fixed Point Core Powerful Program Sequencer Zero Overhead Looping Conditional Instruction Execution Independent Computational Units Multiplier/Accumulator Barrel Shifter Multifunction Instructions Single-Cycle Instruction Execution Single-Cycle Context Switch ADSP-2100 Family Code Function Compatible with Instruction Enhancements 16-Bit Watchdog Timer Programmable 16-Bit Interval Timer with Prescaler Synchronous Serial Ports Full Debugger Interface Bootstrap Protocols Sport Serial UART Memory Configuration 24-Bit Word Program 16-Bit Word Data 24-Bit Word Program
ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS
Single Chip Motor Controller ADMC330
FUNCTIONAL BLOCK DIAGRAM
PROGRAM PROGRAM MEMORY DATA MEMORY WATCHDOG TIMER
PROGRAM SEQUENCER
8-BIT
PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA
ARITHMETIC UNITS SHIFTER
SERIAL PORTS
SPORT SPORT
TIMER
8-BIT
ANALOG INPUTS
12-BIT 3-PHASE
GENERAL DESCRIPTION
ADMC330 cost single chip microcontroller optimized stand alone motor control applications. device based fixed-point core (ADSP2171) motor control peripherals including seven analog input channels 12-bit three-phase generator. device auxiliary 8-bit channels adds expansion capability through serial ports 8-bit digital port. ADMC330 internal words program RAM, words data RAM, which loaded from external device serial port. There also words internal program ROM, which includes monitor that adds software debugging features through serial port. ADMC330 core combines ADSP-2100 base architecture (three computational units, data address generators program sequencer) with serial ports, programmable timer, extensive interrupt capabilities on-chip program data memory. addition, ADMC330 supports instructions, which include manipulations-bit set, clear, toggle, test- constants, multiplication instruction squared), biased rounding global interrupt masking, increased flexibility.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1997
ADMC330-SPECIFICATIONS
Parameter ANALOG-TO-DIGITAL CONVERTER Signal Input Resolution Converter Linearity Zero Offset Channel-to-Channel Comparator Match Comparator Delay Current Source Current Source Linearity ELECTRICAL CHARACTERISTICS Logic Logic High Low-Level Output Voltage Low-Level Output Voltage (XTAL) High-Level Output Voltage Low-Level Input Current High-Level Input Current Supply Current (Power-Down Mode) Supply Current (Static) CLOCK Input Clock (tCK) Clock (tCK/2) REFERENCE VOLTAGE OUTPUT Voltage Level Output Voltage Change TMIN TMAX 12-BIT TIMER Counter Resolution Edge Resolution Programmable Deadtime Range Programmable Deadtime Increments Programmable Pulse Deletion Range Programmable Pulse Deletion Increments Frequency Range PWMSYNC Pulsewidth (TCRST) Gate Drive Chop Frequency Range AUXILIARY TIMERS Resolution Frequency
10%, SGND unless otherwise noted)
Units Conditions/Comments Charging Capacitor 1000 Sample Frequency 3.21 13.5 Bits Bits Bits Bits Missing Codes
2.55
Clock Input (CLKIN) Clock (CLKOUT) Load
0.08 12.5 12.5
CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN
1/256 CLKIN Clock
NOTES 1Signal input 2Resolution varies with switching frequency Clock), bits, bits. Specifications subject change without notice.
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ADMC330
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (VDD) -0.3 +7.0 Digital Input Voltage -0.3 Analog Input Voltage -0.3 Analog Reference Input Voltage -0.3 Digital Output Voltage Swing -0.3 Analog Reference Output Swing -0.3 Operating Temperature -40°C +85°C Lead Temperature (Soldering, sec) +280°C
*Stresses greater than those listed above cause permanent damage device. These stress ratings only; functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Instruction Rate
Package Description 80-Lead Plastic Thin Quad Flatpack (TQFP)
Package Option ST-80
ADMC330BST -40°C +85°C
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADMC330 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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ADMC330
FUNCTION DESCRIPTIONS
Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR
Name VAUX3 REFOUT PIO7 PIO6 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 AUX1 AUX0 PWMTRIP
Type
Name PWMSYNC
Type BIDIR BIDIR BIDIR BIDIR
Name XTAL CLKIN PWMPOL RESET CLKOUT TFS1 RFS1 DR1A DR1B SCLK1
Type
Name TFS0 RFS0 SCLK0 AGND CAPIN ICONST SGND VAUX0 VAUX1 VAUX2
BIDIR BIDIR BIDIR BIDIR
CONFIGURATION 80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80)
PWMPOL CLKIN CLKOUT
SCLK1 DR1B
RESET
DR1A
RFS1
TFS1
XTAL
TFS0 RFS0 SCLK0 AGND CAPIN ICONST SGND VAUX0 VAUX1 VAUX2
IDENTIFIER
PWMSYNC
ADMC330
VIEW (Not Scale)
PIO0
PIO3
PIO2
PIO1
AUX0
PWMTRIP
VAUX3
REFOUT
CONNECT
AUX1
PIO5
PIO4
PIO7
PIO6
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ADMC330
ADMC330 operates with instruction cycle time. Every instruction execute single processor cycle. flexible architecture comprehensive instruction ADMC330 allow processor perform multiple operations parallel. processor cycle ADMC330 can: generate next program address fetch next instruction perform data moves update data address pointers perform computational operation This takes place while processor continues receive transmit data through serial ports decrement timer Independently peripheral blocks can: generate three-phase waveforms power inverter generate signals using 8-bit auxiliary timers acquire four analog signals control eight digital lines decrement watchdog timer
Code Functions
executable file. simulator provides interactive instruction-level simulation with reconfigurable user interface display different portions hardware environment. MAKEPROM utility splitter generates PROM programmer compatible files. Compiler, based Free Software Foundation's Compiler, generates ADMC330 assembly source code. runtime library includes over ANSIstandard mathematical DSP-specific functions. cost, easy-to-use hardware development tools include ADMC330-EVAL board windows based software debugger. This debugger with either ADMC330-EVAL board target system communicating over two-wire asynchronous link
FUNCTIONAL DESCRIPTION ADMC330 Peripherals Overview
ADMC330 Boot that contains following: Monitor Program: Serial Boot Loader EEPROM UART Debugger Interface Loader Math Utilities/Tables: Sine, cosine, tangent, inverse tangent, log, inverse log, square root, 1/X, 1/(sine rms), unsigned division, Cartesian polar conversion, interpolation ADMC330 similar ADSP-2172 booting sequence. MMAP BMODE pins tied high, which enables on-chip starts execution monitor program power-up reset. monitor program first attempts boot load through SPORT1 from serial memory device. loader uses two-wire (data clock) serial protocol. ADMC330 provides serial clock device equal 1/20 CLKOUT. Default input from Xilinx XC1765D Atmel AT17C65 EEPROM; other devices possible long they adhere loader protocol. serial load successful, code that downloaded executed start user memory space. Failing synchronous boot load, ADMC330 monitor switches over debug mode waits commands over SPORT1 from UART. Debug mode uses standard RS-232 protocol which only data receive transmit lines used ADMC330. This interface used Visual DSP® Debugger, also used UART devices boot loading programs. addition monitor program, contains previously listed math utilities. These routines called from user applications.
Development System
ADMC330 peripherals specifically developed address requirements variable speed control induction motors (ACIM) electronically commutated synchronous motors (ECM). They memory mapped block data memory space allowing single cycle read and/or write peripheral registers. operation peripherals synchronized core clock HCLK, which derived from half system clock.
Three-Phase Generator
12-bit center-based generator including programmable deadtime narrow pulse deletion. crossover block. Output enable block. Hardwired output polarity control. External trip input. Pulsed output capability transformer coupled gate.
Analog
8-bit Output Timers-(Synthesized Analog Output). Comparator based Analog Input Acquisition. Analog-to-digital conversion accomplished 4-channel single slope ADC.
Digital
Eight bits programmable digital configurable interrupt sources.
THREE-PHASE GENERATOR
ADSP-2100 Family Development Software, complete tools software hardware system development, supports ADMC330. system builder provides high level method defining architecture systems under development. assembler algebraic syntax that easy program debug. linker combines object files into
Visual registered trademark Analog Devices, Inc.
ADMC330 controller self-contained programmable waveform generator that produces switching signals three-phase power inverter. includes waveform timing edge calculation unit which allows generation center based signals based only three duty cycle register updates every switching cycle. This minimizes software required service controller frees processor time motor control implementation. default configuration produces three-phase center based waveforms required three phase sinusoidal inverter. However, also configured space vector modulation schemes, controlling brushless motors (sometimes known electronically commutated motors). also functions which simplify interface power inverter gate drive protection circuits. controller synchronized core HCLK which runs half clock frequency giving waveform resolution with clock. There
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ADMC330
four configuration registers (PWMTM, PWMDT, PWMPD PWMGATE), which define basic waveform parameters such master switching frequency, deadtime, minimum pulsewidth, gate drive chopping. There output signals pins through controlled input registers (PWMCHA, PWMCHB, PWMCHC PWMSEG) control pins PWMTRIP PWMPOL.
Controller Overview
dead time duty cycle each inverter phase. There extra software overhead once duty cycle each phase been calculated loaded into channel registers. Timing Unit produces three pairs complemented variable duty cycle waveforms symmetrical about common axes form shown Figure They complemented waveforms, which means that pair waveforms AL), they never both same time. They deadtime adjusted, which means that pair waveforms, there delay between switching from being waveform being complemented waveform. pulse deletion function implemented, which means that very narrow pulses will generated. important note that deadtime compensation does take place boundary between consecutive cycles. Thus both side high side devices switch during transition from full-ON state other state. This potentially volatile condition avoided Ensuring that device never enters full-ON fullOFF states, that PWMCHx PWM-2 (PWMDT with PWMPD Using external deadtime compensation circuit. There active high PWMSYNC pulse produced beginning each cycle synchronize operation other peripherals with switching power inverter. This signal also internally connected block initiate conversions, core generate interrupt. Figure shows center-based operation. master switching frequency range from integral fraction HCLK clock frequency. value 12-bit PWMperiod register, which sets total number clock cycles cycle. required period function desired master switching frequency (fPWM) peripheral system clock frequency (fHCLK) given PWM= HCLK
controller consists three units: center-based timing unit, output control unit gate drive unit shown Figure center-based timing unit core controller produces three pairs complemented deadtime adjusted waveforms required motor control. output control unit signal switching unit that selects appropriate signals connected output pins based bits segment register (PWMSEG) required control some space vector modulation schemes. gate drive block sets logic polarity "on" signal according polarity PWMPOL match gate drive circuit requirement. also modulate "on" signal with high frequency carrier (0.08 MHz- MHz) required transformer coupled gate drive circuit. DSP-based control algorithm synchronized generator hardware interrupt signal that generated every switching cycle. This same PWMSYNC signal internally connected internal analog-to-digital converter also available output pin. Finally, hardware PWMTRIP used shut down controller event fault.
Center-Based Timing Unit
center-based timing unit programmable timer that generates three pairs fixed frequency waveforms suitable controlling three-phase power inverter. unit contains arithmetic circuits that calculate signal timing edges from waveform parameters such period,
TIMING CONTROL REGISTERS PWMPWMDT PWMPD CHANNEL REGISTERS PWMCHA PWMCHB PWMCHC
OUTPUT CONTROL REGISTER PWMSEG
GATE CONTROL REGISTER PWMGATE
CENTER-BASED TIMING UNIT
OUTPUT CONTROL UNIT
GATE DRIVE UNIT
SYNC
RESET
SYNC
HCLK PWMSYNC
PWMPOL PWMSYNC
INTERRUPT SIGNALS
PWMTRIP
Figure Controller Overview
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ADMC330
example, HCLK clock MHz. waveforms required, then PWMshould loaded with MHz/8 1250. value must written PWMregister before block used. time each pair waveforms, e.g., integer value duty cycle registers PWMCHA, PWMCHB PWMCHC. deadtime between active portions complementary waveforms value deadtime register PWMDT subtracted from value duty cycle register. final deadtime adjusted fractional duty cycle Channel example given PWMCHA PWMDT PWMOutput Control Unit
Output Control Unit contains special features that allow ADMC330 easily applied control electronically commutated motors (ECM) brushless motors (BDCM). these machines, only motor phases required conduct simultaneously that most power switches turned time. order build current motor phases, necessary turn upper switch phase lower switch another phase inverter. PWMSEG register ADMC330 block allows modification pulsewidth modulation signals from center-based block order meet requirements control. Three bits PWMSEG register (Bits permit individual crossover three signal pairs. example, setting will crossover signals Phase such that high-side signal from center-based block will ultimately appear low-side output (AL). Conversely, low-side signal from center-based block will appear
minimum pulsewidth delivered value pulse deletion register PWMPD. When calculated high pulsewidth channel less than PWMPD, switching pulse eliminated outputs saturated 100% high, other 100% low.
START PWMCHA
PWMDT
PWMCHB
PWMDT
PWMDT
PWMDT
PWMCHC
PWMDT
PWMDT
PWMPWMSYNC
Figure Three-Phase Center-Based Active Waveforms
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ADMC330
Similar modifications made Phases using Bits respectively, PWMSEG register. bits PWMSEG register (Bits used independently enable/disable individual output pins. example, setting Bits high disables outputs which keeps these outputs over full period regardless value PWMCHC register. This feature only useful control, also required some space vector modulation schemes. Modifications PWMSEG register only become effective start each cycle. transparent (default) mode, bits PWMSEG low. Consider situation shown Figure operation with power devices active. duty cycle registers, PWMCHA PWMCHB, programmed with appropriate on-time value. Since three registers must written trigger update PWM, necessary write also PWMCHC. this example, particular value written this register unimportant. Subsequently, crossover PWMSEG register Phase (Bit enable crossover Phase signals. outputs Phase high low, Phase high Phase disabled setting Bits PWMSEG register. this example, appropriate value PWMSEG register 0x00A7. addition, high side chopping signal enabled setting PWMGATE register.
START MIDPOINT PWMCHA PWMCHB PWMDT
Gate Drive Unit
Gate Drive Unit adds features that simplify interface variety gate drive circuits inverters. transformer coupled power device gate drive amplifier used, active signal must chopped high frequency MHz. chopped active signals required high side drivers only both high side side. gate drive chopping feature enabled Bits PWMGATE register. Setting enables chopped signal high side output pins setting enables chopped signal side output pins gate chopping frequency programmed using Bits PWMGATE register. gate drive chopping frequency given following equation: chop HCLK
where GATEis 6-bit value Bits PWMGATE register. Depending type power device gate drive circuit used, either active high active low, signals will required, external polarity provided. polarity PWMPOL determines active polarity output signals (i.e., PWMPOL means active PWM). This must hardware because even though ADMC330 will power with outputs off, correct polarity signal function gate drive circuit only. level PWMPOL available SYSSTAT register.
External Trip
CENTERBASED OUTPUTS
PWMDT
fault conditions power devices must switched soon possible after fault been detected, hence external hardware trip input provided. going PWMTRIP pulse will reset block which will disable outputs. This will also generate PWMTRIP interrupt signal cause interrupt. PWMTRIP accessible through SYSSTAT that determine when external fault been cleared. this point, full initialization controller will required restart PWM.
OVERVIEW
Figure Output Waveforms with Inverter Devices Active
Known limitation block. Modifying PWMSEG register while duty cycle transitions from full-ON state other state will cause both high side side devices switch This potentially volatile condition avoided Disabling channel outputs during transition from full-ON other state. Preventing full-ON condition namely limiting PWMCHx PWMCHx PWM-2 (PWMDT with PWMPD Preventing PWMSEG update operation during transition from full-ON other state.
analog input block 12-bit resolution analog data acquisition system. single slope type implemented timing crossover between analog input sawtooth reference ramp. simple voltage comparator used latch output reference counter timer circuit when crossover detected. There seven input channels which three (V1, have dedicated comparators. remaining four inputs (VAUX0, VAUX1, VAUX2 VAUX3) multiplexed into fourth comparator channel. This allows four conversions period performed ADC. particular input signal that fourth comparator input selected using ADCMUX0 ADCMUX1 bits peripheral control register, MODECTRL. settings these control bits order select appropriate auxiliary analog input shown Table
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ADMC330
PWMGATE
ENABLE DISABLE
SIDE GATE CHOPPING HIGH SIDE GATE CHOPPING
GATEGATE DRIVE CHOPPING FREQUENCY (fHCLK) /(2(GATETM+1))
PWMSEG
CHANNEL CROSSOVER CROSSOVER CROSSOVER CHANNEL CROSSOVER CHANNEL CROSSOVER
OUTPUT DISABLE OUTPUT DISABLE OUTPUT DISABLE OUTPUT DISABLE OUTPUT DISABLE OUTPUT DISABLE DISABLE ENABLE
Figure Configuration PWMSEG PWMGATE Registers
Table Auxiliary Channel Selection
Select VAUX0 VAUX1 VAUX2 VAUX3
Analog Block
MODECTRL ADCMUX1
MODECTRL ADCMUX0
appropriate 12-bit register. There four registers (ADC1, ADC2, ADC3 ADCAUX) corresponding each four comparators. reference voltage ramp, four registers should have been loaded with values that conversion data available controller after PWMSYNC interrupt. first values loaded into output registers after first PWMSYNC interrupt will invalid since latched value indeterminate. very analog inputs, less than minimum reference value, comparator output will permanently high output register will contain code 0x000. Also, input analog voltage exceeds peak capacitor ramp voltage, comparator output will permanently 0xFFF code will produced. This indicates input overvoltage condition.
REFOUT ICONST CAPIN REGISTERS SGND ADC1 TIMER BLOCK ADC2 PWMSYNC
operation block explained reference Figures reference ramp tied input each four comparators. This reference ramp generated charging external timing capacitor with constant current source. timing capacitor connected between pins CAPIN SGND. capacitor voltage reset start each cycle using PWMSYNC pulse, which held high CLKIN cycles (TCRST CLKIN). falling edge PWMSYNC, capacitor begins charge rate determined capacitor current source values. internal current source made available connection external timing capacitor ICONST pin. external current source could also used, required. four input comparators block continuously compare values four analog inputs with capacitor voltage. Each comparator output will high when capacitor voltage exceeds respective analog input voltage.
Timer Block
ADC3 VAUX0 VAUX1 VAUX2 VAUX3 ADMUX0 ADMUX1 ADCAUX
timer block consists 12-bit counter clocked constant rate HCLK, equal half clock rate. This gives timer resolution maximum CLKIN frequency MHz. counter reset falling edge PWMSYNC pulse that counter commences beginning reference voltage ramp. When output given comparator goes high, counter value latched into
HCLK
Figure Overview
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ADMC330
VCMAX
result, assuming ±10% variations both capacitance current source, nominal capacitance value required given period
CNOM
(0.9 CONST CRST (1.1)(3.5)
tVIL
TCRST TPWM TCRST PWMSYNC
largest standard value capacitor that less than this calculated value chosen. Table shows appropriate standard capacitor value various switching frequencies assuming variations both current source capacitor tolerances. required, more precise control ramp voltage possible using higher precision capacitor components, external current source and/or series parallel timing capacitor combinations.
Table III. Timing Capacitor Selection
COMPARATOR OUTPUT
Figure Analog Input Block Operation
Resolution
Frequency (kHz) 2.5-3.0 3.0-3.6 3.6-4.3 4.3-5.2 5.2-6.2 6.2-7.3 7.3-9.0 9.0-10.9 10.9-13.2 13.2-15.8 15.8-19.6 19.6-23.4 23.4-28.2
Timing Capacitor (pF)
Because operation intrinsically linked block, effective resolution function switching frequency. effective resolution determined rate which counter timer clocked. CLKIN period period TPWM, maximum count given Count
assumed CLKIN frequency MHz, effective resolution block tabulated various switching frequencies Table
Table Resolution Examples
AUXILIARY TIMERS OVERVIEW
Frequency (kHz)
Count 3980 2480 1230
Effective Resolution (Bits)
auxiliary timers used produce analog signal outputs when configured DACs. This allows ADMC330 generate reference power factor correction supply analog reference other systems application. They also used supplementary outputs other control circuits. timers generate fixed frequency edge-based variable duty cycle signals. frequency 1/256 times HCLK, kHz. duty cycle based user-supplied 8-bit value loaded into AUX0 AUX1 registers. timer output range from 99.6%, where number written register represents high time. values updated soon values written registers: value smaller than present counter value output goes low, otherwise stays high. RESET, AUX0 AUX1 registers cleared zero remain zero until value written.
Equation
External Timing Capacitor
order maximize useful input voltage range effective resolution ADC, necessary carefully select value external timing capacitor. given capacitance value, CNOM, peak ramp voltage given
CONST CRST CNOM
where ICONST nominal current source value 10.5 TCRST PWMSYNC pulsewidth. selecting capacitor value, however, necessary take into account tolerance capacitor variation current source value. ensure that full input range utilized, necessary select capacitor that maximum capacitance value minimum current source output, ramp voltage will charge least
output must filtered order produce frequency analog signal between 4.98 example, 2-pole filter with frequency will sufficiently attenuate carrier. Figure shows filter would applied.
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ADMC330
PWMDAC
WATCHDOG TIMER OVERVIEW
10nF
Figure Auxiliary Output Filter
PROGRAMMABLE DIGITAL INPUT/OUTPUT
ADMC330 eight programmable digital (PIO) pins: PIO0-PIO7. Each individually configurable either input output. Input pins also used generate interrupts. pins configured input output setting appropriate bits PIODIR register, shown Figure read/write register PIODATA used state output read state input pin. Writing PIODATA affects only pins configured outputs. default state, after ADMC330 reset, that configured inputs. configured independent edge triggered interrupt source. must first configured input then appropriate must PIOINTEN register. peripheral interrupt generated when input level changes configured interrupt source. interrupt sets appropriate PIOFLAG register. peripheral interrupt service routine (ISR) must read PIOFLAG registers determine which source interrupt. Reading PIOFLAG register will clear
PIODIR
watchdog timer used reset peripherals event software error hanging processor. watchdog timer enabled writing value watchdog timer register. event code "hanging" counter will count down from initial value zero watchdog timer hardware will force peripheral reset. normal operation section code will write timer register reset counter initial value preventing from reaching zero.
CORE ARCHITECTURE OVERVIEW
Figure block diagram ADMC330 processor core system peripherals. processor contains three independent computational units: ALU, multiplier/accumulator (MAC) shifter. computational units process 16-bit data directly have provisions support multiprecision computations. performs standard arithmetic logic operations; division primitives also supported. performs single-cycle multiply, multiply/add multiply/ subtract operations with bits accumulation. shifter performs logical arithmetic shifts, normalization, denormalization derive exponent operations. shifter used efficiently implement numeric format control including multiword block floating-point representations. internal result directly connects computational units that output unit input unit next cycle.
OUTPUT INPUT
PIODATA
(READ/WRITE)
PIOINTEN
(WRITE-ONLY) ENABLE INTERRUPT DISABLE INTERRUPT
PIOFLAG
(READ-ONLY) INTERRUPT FLAGGED INTERRUPT
PIO0
PIO7
Figure Configuration Registers
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ADMC330
INSTRUCTION REGISTER DATA ADDRESS GENERATOR DATA ADDRESS GENERATOR PROGRAM PROGRAM SRAM DATA SRAM FLAGS
PROGRAM SEQUENCER
EXCHANGE
CONTROL LOGIC COMPANDING CIRCUITRY TRANSMIT RECEIVE SERIAL PORT
INPUT REGS OUTPUT REGS
INPUT REGS OUTPUT REGS
INPUT REGS SHIFTER OUTPUT REGS
TIMER
TRANSMIT RECEIVE SERIAL PORT
Figure Core Block Diagram
powerful program sequencer dedicated data address generators ensure efficient delivery operands these computational units. sequencer supports conditional jumps, subroutine calls returns single cycle. With internal loop counters loop stacks, ADMC330 executes looped code with zero overhead; explicit jump instructions required maintain loop. data address generators (DAGs) provide addresses simultaneous dual operand fetches (from data memory program memory). Each maintains updates four address pointers. Whenever pointer used access data (indirect addressing), post-modified value four possible modify registers. length value associated with each pointer implement automatic modulo addressing circular buffers. Efficient data transfer achieved with five internal buses: Program Memory Address (PMA) Program Memory Data (PMD) Data Memory Address (DMA) Data Memory Data (DMD) Result Program memory store both instructions data, permitting ADMC330 fetch operands single cycle, from program memory from data memory. ADMC330 fetch operand from on-chip program memory next instruction same cycle.
ADMC330 respond interrupts. There internal interrupts generated Timer, Serial Ports (SPORTs), software peripheral interrupts generated PWM. There also master RESET signal. serial ports provide complete synchronous serial interface with optional companding hardware wide variety framed frameless data transmit receive modes operation. Each port generate internal programmable serial clock accept external serial clock. Boot circuitry provides automatically loading on-chip program memory from data input output pins SPORT1. SPORT1 alternatively configured input flag, output flag additional interrupt sources. programmable interval timer generates periodic interrupts. 16-bit count register (TCOUNT) decremented every processor cycles, where scaling value stored 8-bit register (TSCALE). When value count register reaches zero, interrupt generated count register reloaded from 16-bit period register (TPERIOD). ADMC330 instruction provides flexible data moves multifunction (one data moves with computation) instructions. Every instruction executed single processor cycle. ADMC330 assembly language uses algebraic syntax ease coding readability. comprehensive development tools supports program development.
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ADMC330
Serial Ports
ADMC330 incorporates complete synchronous serial ports (SPORT0 SPORT1) serial communications multiprocessor communication. Following brief list capabilities ADMC330 SPORTs. Refer ADSP-2100 Family User's Manual further details. SPORTs bidirectional have separate, double-buffered transmit receive section. SPORTs external serial clock generate their serial clock internally. SPORTs have independent framing receive transmit sections. Sections frameless mode with frame synchronization signals internally externally generated. Frame sync signals active high inverted, with either pulsewidths timings. SPORTs support serial data word lengths from bits provide optional A-law µ-law companding according CCITT recommendation G.711. SPORT receive transmit sections generate unique interrupts completing data word transfer. SPORTs receive transmit entire circular buffer data with only overhead cycle data word. interrupt generated after data buffer transfer. SPORT0 multichannel interface selectively receive transmit 32-word, time-division multiplexed, serial stream. SPORT1 configured have external interrupts (IRQ0 IRQ1) Flag Flag signals. internally generated serial clock still used this configuration. SPORT1 multiplexed data receive pins DR1A DR1B. DR1A automatically selected boot default input serial ROM. UART communication DR1B selected. full description SPORT timing parameters given Figure
Interrupts
PIOFLAG register interrupt, IRQ2 line pulled low. IRQ2 line held until pending peripheral interrupts acknowledged. Execution then begins IRQ2 peripheral) interrupt vector location (0x004). Software this location further determines source interrupt trip, PWYMSYNC, PIO, reading IRQFLAG register, vectors appropriate interrupt vector location. more than interrupt occurs simultaneously, higher priority interrupt service routine executed. software location 0x004 provided default interrupt vector table that created on-chip boot code. Therefore, user need only interrupt service routine given interrupt interrupt vector location shown Table Reading IRQFLAG register clears PWMTRIP PWMSYNC bits acknowledges interrupt, thus allowing further interrupts when interrupt service routine exits. When IRQFLAG register read, saved data memory variable user interrupt service routines check there were simultaneous PWMTRIP PWMSYNC interrupts. user's interrupt service routine must read PIOFLAG register determine which port source interrupt. Reading PIOFLAG register clears bits register acknowledges interrupt, thus allowing further interrupts when interrupt service routine exits. interrupts internally prioritized individually maskable (except power-down). interrupt vector locations priorities interrupts listed Table Interrupts masked unmasked with IMASK register. Individual interrupt requests logically ANDed with bits IMASK; higher priority unmasked interrupt then selected. software forced power-down interrupt nonmaskable. ADMC330 masks interrupts instruction cycle following execution instruction that modifies IMASK register. This does affect autobuffering.
Table Interrupt Priority Interrupt Vector Addresses
Source Interrupt Reset PWMTRIP Power-Down* PWMSYNC* PIO* SPORT0 Transmit SPORT0 Receive Software Interrupt Software Interrupt SPORT1 Transmit IRQ1 SPORT1 Receive IRQ0 Timer
Interrupt Vector Location (Hex) 0x0000 (Reserved) 0x002C (Highest Priority) 0x000C 0x0008 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 (Lowest Priority)
interrupt controller allows processor core respond nine possible interrupts with minimum overhead. ADMC330 supports eight internal interrupts from timer, serial ports, software interrupts, software forced power-down interrupt. ninth interrupt, IRQ2 2171 core, actually wired internally ADMC330 peripheral interrupt sources. This peripheral interrupt generated trip, PWMSYNC (once each cycle), from eight ports. PWMSYNC interrupt triggered high transition PWMSYNC pulse. PWMTRIP interrupt triggered high-to-low transition PWMTRIP pin. interrupt detected change state (high-to-low low-to-high) line. When peripheral interrupt detected, flag IRQFLAG register PWMSYNC PWMTRIP
*Peripheral interrupt (IRQ2) starts execution 0x004, software further vector 0x002C, 0x000C 0x0008 appropriate.
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ADMC330
interrupt control register, ICNTL, allows external interrupts either edge- level-sensitive. Since IRQ2 line combination peripheral interrupt sources, they will edge- level-sensitive. Level-sensitive recommended when using both interrupts together. When simultaneous interrupts occur, IRQ2 line brought held until both interrupts acknowledged. interrupts edge-sensitive only, IRQ2 interrupt will occur simultaneous interrupts incumbent interrupt service routine check simultaneous interrupts. however, interrupts levelsensitive, simultaneous interrupts detected because IRQ2 held until interrupts acknowledged. ICNTL register also allows interrupts sequentially processed nested with higher priority interrupts taking precedence. Since peripheral interrupts same level (IRQ2), they only nested manually unmasking them with IMASK register from inside interrupt service routine. register write-only register, which used force clear interrupts from software. On-chip stacks preserve processor status automatically maintained during interrupt handling. stacks levels deep allow interrupt nesting. shadow registers provided single context switching.
Power-Down
timing relative internal instruction clock rate, which indicated CLKOUT signal when enabled. Because ADMC330 includes on-chip oscillator circuit, external crystal used. crystal should connected across CLKIN XTAL pins, with capacitors connected shown Figure parallel-resonant, fundamental frequency, microprocessor-grade crystal should used.
CLKIN
XTAL
Figure External Crystal Connections
clock output (CLKOUT) signal generated processor processor's cycle rate.
Reset
ADMC330 lower power state from software control setting PDFORCE SPORT1 Autobuffer/ Power-Down register. This causes power-down interrupt; execution then continues power-down interrupt vector location 0x002C. power-down interrupt vector location shared with PWMTRIP interrupt, thus different interrupt service routine required, vector must changed prior setting PDFORCE bit. power-down interrupt service routine must perform peripheral reset prior entering power-down shut down signals motor. interrupt service routine then perform housekeeping operations prior executing IDLE instruction, after which ADMC330 power-down mode. only power-down perform hardware reset ADMC330.
Clock Signals
RESET signal initiates master reset ADMC330. RESET signal must asserted during power-up sequence assure proper initialization. RESET during initial power-up must held long enough allow internal clock stabilize. RESET activated time after power-up, clock continues does require stabilization time. power-up sequence defined total time required crystal oscillator circuit stabilize after valid applied processor, internal phase-locked loop (PLL) lock onto specific crystal frequency. minimum 2000 CLKIN cycles ensures that locked, does include crystal oscillator start-up time. During this power-up sequence RESET signal should held low. RESET input contains some hysteresis; however, circuit generate your RESET signal, external Schmitt trigger recommended. master reset sets internal stack pointers empty stack condition, masks interrupts clears MSTAT register. When RESET released, starts running from internal boot loading sequence performed. SROM (serial ROM) Serial EEPROM connected SPORT1 with valid program data, this code then loaded execution starts. valid device detected, then program defaults debug mode with SPORT1 configured UART running 9600 baud.
ADMC330 clocked either crystal TTLcompatible clock signal. CLKIN input cannot halted, changed during operation operated below specified frequency during normal operation. external clock used, should TTL-compatible signal running half instruction rate. signal connected processor's CLKIN input. When external clock used, XTAL input must left unconnected. ADMC330 uses input clock with frequency equal half instruction rate; input clock yields processor cycle (which equivalent MHz). Normally, instructions executed single processor cycle. device
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REV.
ADMC330
software controlled full peripheral reset (including watchdog timer) achieved toggling flag from again.
MEMORY
ADMC330 types memory: data memory program memory. Program starts 0x0000, while program area starts 0x800. data starts 0x3800 while peripherals mapped data memory block starting 0x2000.
Table Program Memory
This mode only effect when register contains 0x8000; other rounding operation work normally. This mode added allow more efficient implementation specified algorithms that specify biased rounding, such speech compression routines. Unbiased rounding preferred most algorithms. Note: BIASRND SPORT0 Autobuffer Control register.
INSTRUCTION DESCRIPTION
0x0000-0x002F 0x0030-0x07FF 0x0800-0x0BFF 0x0C00-0x0FFF
Interrupt Vector Table User Program Space Monitor Math Utilities
Table Data Memory
ADMC330 assembly language instruction algebraic syntax that designed ease coding readability. assembly language, which takes full advantage processor's unique architecture, offers following benefits: algebraic syntax eliminates need remember cryptic assembler mnemonics. example, typical arithmetic instruction, such AY0, resembles simple equation. Every instruction assembles into single, 24-bit word that execute single instruction cycle. syntax superset ADSP-2100 Family assembly language completely source object code compatible with other family members. Sixteen condition codes available. conditional jump, call, return arithmetic instructions, condition checked operation executed same instruction cycle. Multifunction instructions allow parallel execution arithmetic instruction with fetches write processor memory space during single instruction cycle. Consult ADSP-2100 Family User's Manual complete description syntax instruction reference with particular reference ADSP-2171 device.
Interrupt Enable
0x2000-0x201F 0x3800-0x3B8F 0x3B90-0x3BFF
ADMC330 Registers
Peripherals User Data Space Reserved Monitor
Some registers store values. example, stores operand; stores DAG2 pointer. Other registers consist control bits fields, status flags. example, ASTAT contains status flags from arithmetic operations, fields DWAIT control numbers wait states different zones data memory. secondary registers computational units allows single-cycle context switch. field definitions control status registers given rest this section, except IMASK, ICNTL IFC, which defined earlier this data sheet. system control register, timer registers SPORT control registers mapped into data memory; that registers accessed reading writing data memory locations rather than register names. particular data memory address shown with each memory-mapped register.
Biased Rounding
ADMC330 supports interrupt enable instruction. Interrupts enabled default reset. instruction source code specified follows: Syntax: Description: INTS; Executing INTS instruction allows unmasked interrupts serviced again.
mode allows biased rounding addition normal unbiased rounding. When BIASRND normal unbiased rounding operations occur. When BIASRND biased rounding occurs instead normal unbiased rounding. When operating biased rounding mode rounding operations with 0x8000 will round rather than only rounding values example: value before 00-0000-8000 00-0001-8000 00-0000-8001 00-0001-8001 00-0000-7FFF 00-0001-7FFF biased result 00-0001-8000 00-0002-8000 00-0001-8001 00-0002-8001 00-0000-7FFF 00-0001-7FFF unbiased result 00-0000-8000 00-0002-8000 00-0001-8001 00-0002-8001 00-0000-7FFF 00-0001-7FFF
Interrupt Disable ADMC330 supports interrupt disable instruction. instruction source code specified follows: Syntax: Description: INTS; Reset enables interrupt servicing. Executing INTS instruction causes interrupts masked without changing contents IMASK register. Disabling interrupts does affect autobuffer circuitry, which will operate normally whether interrupts enabled. disable interrupt instruction masks user interrupts including power-down interrupt.
REV.
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ADMC330
ICNTL
IMASK
ENABLE, DISABLE
IRQ0 SENSITIVITY IRQ1 SENSITIVITY IRQ2 SENSITIVITY EDGE LEVEL
IRQ2
INTERRUPT NESTING ENABLE, DISABLE
SPORT0 TRANSMIT SPORT0 RECEIVE
TIMER IRQ0 SPORT1 RECEIVE IRQ1 SPORT1 TRANSMIT SOFTWARE SOFTWARE
INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE SOFTWARE SPORT1 TRANSMIT IRQ1 SPORT1 RECEIVE IRQ0 TIMER
INTERRUPT CLEAR TIMER SPORT1 RECEIVE IRQ0 SPORT1 TRANSMIT IRQ1 SOFTWARE SOFTWARE SPORT0 RECEIVE SPORT0 TRANSMIT IRQ2
Figure Interrupt Registers
SYSTEM CONTROLLER OVERVIEW
INTERFACE MEMORY
System Controller number functions: decodes address selects appropriate peripheral registers. controls multiplexer select lines. enable PWMTRIP PWMSYNC interrupts. controls SPORT0 multiplexer select lines. resets peripherals control registers hardware, software watchdog initiated resets. handles interrupts generated peripherals generates core interrupt signal IRQ1 (IRQ2). used control peripheral test modes.
data transferred between core peripherals controlled System Controller. peripheral registers, with exception read registers, right justified, i.e., each register connected 16-bit data DSPD [15:0]. unused MSBs connected zeros. ADMC peripheral registers memory mapped words address space, starting memory location 0x2000: read registers (0-3) Registers (4-7) Set-Up Registers (8-11) Data Registers (12-15) Data Registers (16, System Registers (21-24)
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ADMC330
Table VII. Peripheral Register
Address (HEX) 0x2000 0x2001 0x2002 0x2003 0x2004 0x2005 0x2006 0x2007 0x2008 0x2009 0x200A 0x200B 0x200C 0x200D 0x200E 0x200F 0x2010 0x2011 0x2012 0x2013 0x2014 0x2015 0x2016 0x2017 0x2018 0x2019.F
Offset (Decimal) 25.31
Name ADC1 ADC2 ADC3 ADCAUX PIODIR PIODATA PIOINTEN PIOFLAG PWMPWMDT PWMPD PWMGATE PWMCHA PWMCHB PWMCHC PWMSEG AUX0 AUX1
Bits Used [4.15] [4.15] [4.15] [4.15] [0.7] [0.7] [0.7] [0.7] [0.11] [0.6] [0.6] [0.8] [0.11] [0.11] [0.11] [0.8] [0.7] [0.7]
Function Results Results Results Results VAUX Pins Direction Setting Pins Input/Output Data Pins Interrupt Enable Pins Interrupt Status Period Deadtime Pulse Deletion Time Gate Drive Configuration Channel Pulsewidth Channel Pulsewidth Channel Pulsewidth Segment Select Output Output Used Used Used System Control Register System Status Interrupt Status Watchdog Timer Used
MODECTRL SYSSTAT IRQFLAG WDTIMER
[0.15] [0.1] [0.2] [0.15]
Multiplexer, Interrupts SPORT1 Control
ADC, SPORT1 peripherals interrupts configured using MODECTRL register. bits control channel selection: ADCMUX0.1. bits enable/disable PWMTRIP PWMSYNC interrupts. bits control SPORT1 UART DR1A/B multiplexer. interrupt enable bits masking bits rather than set/reset bits. Therefore, before enabling these interrupts pending interrupts cleared reading IRQFLAG register. Setting UARTEN connects RFS1 input, which allows SPORT1 used UART port. DR1SEL selects either pins DR1A DR1B. reset condition bits this register zero.
DR1A
Peripheral Reset Functions
full system reset ADMC330 achieved pulling RESET (for clock cycles when running, 2000 clock cycles power-up). This resets core peripherals including watchdog timer. SYSSTAT register indicates fault status ADMC330 after PWMTRIP interrupt watchdog reset: status PWMTRIP (active low). status watchdog flag register (this reset RESET). status PWMPOL pin. When peripherals generates interrupt, IRQ2 line pulled flag IRQFLAG register PWMSYNC PWMTRIP PIOFLAG register interrupt. read these registers determine source interrupt. When IRQFLAG register read, PWMSYNC PWMTRIP bits cleared zero. Reading PIOFLAG register clears bits this register zero. When both registers cleared, IRQ2 line high again. reset condition bits this register zero.
ADMC330
SPORT1 TFS1 RFS1 SCLCK1 UART ENABLE DR1B SELECT
DR1B TFS1 RFS1 SCLCK1 DEFAULT SWITCH POSITION SHOWN
Figure Internal Multiplexing SPORT1 Pins
REV.
-17-
ADMC330
MODECTRL
(READ/WRITE)
CONTROL VAUX0 VAUX1 VAUX2 VAUX3 PWMTRIP INTERRUPT ENABLE PWMSYNC INTERRUPT ENABLE SPORT1 DATA RECEIVE SELECT ENABLE DISABLE DR1B DR1A UART SPORT
SPORT1 MODE SELECT
SYSSTAT
PWMTRIP STATUS
WATCHDOG STATUS
RESET OCCURRED NORMAL
PWMPOL STATUS
IRQFLAG
PWMTRIP INTERRUPT STATUS PWMSYNC INTERRUPT STATUS
PENDING CLEARED
Figure Configuration MODECTRL, SYSSTAT IRQFLAG Registers
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REV.
ADMC330
TIMING PARAMETERS
SERIAL PORTS
Parameter Timing Requirement: tSCK SCLK Period DR/TFS/RFS Setup before SCLK tSCS tSCH DR/TFS/RFS Hold after SCLK SCLKIN Width tSCP Switching Characteristic: CLKOUT High SCLKOUT tSCDE SCLK High Enable tSCDV SCLK High Valid TFS/RFSOUT Hold after SCLK High TFS/RFSOUT Delay from SCLK High tSCDH Hold after SCLK High tTDE (Alt) Enable tTDV (Alt) Valid tSCDD SCLK High Disable tRDV (Multichannel, Frame Delay Zero) Valid
12.5
13.0 76.9 19.2 34.2
13.824 MHz* 72.3 18.1 33.1
Frequency Dependency 0.25 0.25
Unit
*Maximum serial port operating frequency 13.824 processor speed grades except 12.5 ADSP-2101 13.0 ADSP-2111.
CLKOUT
SCLK
RFSIN TFSIN
RFSOUT TFSOUT
SCDV SCDE
SCDD SCDH
(ALTERNATE FRAME MODE)
(MULTICHANNEL MODE, FRAME DELAY (MFD
Figure Serial Ports
REV.
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ADMC330
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80)
0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.549 (13.95) 0.486 (12.35)
0.063 (1.60) 0.030 (0.75) 0.020 (0.50) SEATING PLANE
VIEW
(PINS DOWN)
0.004 (0.10) 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.029 (0.73) 0.022 (0.57)
0.014 (0.35) 0.010 (0.25)
0.486 (12.35) 0.553 (14.05) 0.549 (13.95 0.640 (16.25) 0.620 (15.75)
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REV.
PRINTED U.S.A.
C3043-2.5-9/97

ADSP-2100 BASE ARCHITECTURE DATA ADDRESS GENERATORS Single Chip M

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